forked from M-Labs/artiq-zynq
48 lines
1.3 KiB
Rust
48 lines
1.3 KiB
Rust
use libboard_zynq::{gic, mpcore, println, stdio};
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use libcortex_a9::{
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asm,
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regs::{MPIDR, SP},
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spin_lock_yield, notify_spin_lock
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};
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use libregister::{RegisterR, RegisterW};
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use core::sync::atomic::{AtomicBool, Ordering};
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extern "C" {
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static mut __stack1_start: u32;
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fn main_core1() -> !;
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}
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static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[naked]
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pub unsafe extern "C" fn IRQ() {
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if MPIDR.read().cpu_id() == 1 {
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let mpcore = mpcore::RegisterBlock::new();
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let mut gic = gic::InterruptController::new(mpcore);
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let id = gic.get_interrupt_id();
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if id.0 == 0 {
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gic.end_interrupt(id);
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asm::exit_irq();
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SP.write(&mut __stack1_start as *mut _ as u32);
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asm::enable_irq();
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CORE1_RESTART.store(false, Ordering::Relaxed);
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notify_spin_lock();
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main_core1();
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}
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}
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stdio::drop_uart();
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println!("IRQ");
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loop {}
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}
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pub fn restart_core1() {
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let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new());
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CORE1_RESTART.store(true, Ordering::Relaxed);
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interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
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while CORE1_RESTART.load(Ordering::Relaxed) {
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spin_lock_yield();
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}
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}
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