forked from M-Labs/artiq-zynq
246 lines
7.4 KiB
Rust
246 lines
7.4 KiB
Rust
//! Kernel prologue/epilogue that runs on the 2nd CPU core
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use core::{mem, ptr, cell::UnsafeCell};
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use alloc::borrow::ToOwned;
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use log::{debug, info, error};
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use cslice::CSlice;
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use libcortex_a9::{
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enable_fpu,
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cache::{dcci_slice, iciallu, bpiall},
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asm::{dsb, isb},
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sync_channel,
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};
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use libboard_zynq::{mpcore, gic};
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use libsupport_zynq::ram;
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use dyld::{self, Library};
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use crate::{eh_artiq, rtio};
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use super::{
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api::resolve,
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rpc::rpc_send_async,
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INIT_LOCK,
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CHANNEL_0TO1, CHANNEL_1TO0,
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KERNEL_CHANNEL_0TO1, KERNEL_CHANNEL_1TO0,
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KERNEL_IMAGE,
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Message,
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dma,
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};
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// linker symbols
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extern "C" {
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#[no_mangle]
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static __text_start: u32;
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#[no_mangle]
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static __text_end: u32;
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#[no_mangle]
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static __exidx_start: u32;
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#[no_mangle]
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static __exidx_end: u32;
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}
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unsafe fn attribute_writeback(typeinfo: *const ()) {
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struct Attr {
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offset: usize,
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tag: CSlice<'static, u8>,
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name: CSlice<'static, u8>
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}
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struct Type {
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attributes: *const *const Attr,
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objects: *const *const ()
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}
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let mut tys = typeinfo as *const *const Type;
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while !(*tys).is_null() {
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let ty = *tys;
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tys = tys.offset(1);
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let mut objects = (*ty).objects;
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while !(*objects).is_null() {
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let object = *objects;
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objects = objects.offset(1);
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let mut attributes = (*ty).attributes;
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while !(*attributes).is_null() {
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let attribute = *attributes;
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attributes = attributes.offset(1);
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if (*attribute).tag.len() > 0 {
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rpc_send_async(0, &(*attribute).tag, [
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&object as *const _ as *const (),
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&(*attribute).name as *const _ as *const (),
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(object as usize + (*attribute).offset) as *const ()
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].as_ptr());
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}
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}
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}
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}
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}
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pub struct KernelImage {
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library: UnsafeCell<Library>,
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__modinit__: u32,
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typeinfo: Option<u32>,
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}
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impl KernelImage {
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pub fn new(library: Library) -> Result<Self, dyld::Error> {
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let __modinit__ = library.lookup(b"__modinit__")
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.ok_or(dyld::Error::Lookup("__modinit__".to_owned()))?;
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let typeinfo = library.lookup(b"typeinfo");
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// clear .bss
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let bss_start = library.lookup(b"__bss_start");
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let end = library.lookup(b"_end");
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if let Some(bss_start) = bss_start {
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let end = end
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.ok_or(dyld::Error::Lookup("_end".to_owned()))?;
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unsafe {
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ptr::write_bytes(bss_start as *mut u8, 0, (end - bss_start) as usize);
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}
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}
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Ok(KernelImage {
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library: UnsafeCell::new(library),
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__modinit__,
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typeinfo,
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})
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}
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pub unsafe fn rebind(&self, name: &[u8], addr: *const ()) -> Result<(), dyld::Error> {
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let library = self.library.get().as_mut().unwrap();
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library.rebind(name, addr)
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}
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pub unsafe fn exec(&self) {
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// Flush data cache entries for the image in DDR, including
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// Memory/Instruction Synchronization Barriers
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dcci_slice(self.library.get().as_ref().unwrap().image.data);
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iciallu();
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bpiall();
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dsb();
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isb();
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(mem::transmute::<u32, fn()>(self.__modinit__))();
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if let Some(typeinfo) = self.typeinfo {
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attribute_writeback(typeinfo as *const ());
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}
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}
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pub fn get_load_addr(&self) -> usize {
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unsafe {
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self.library.get().as_ref().unwrap().image.as_ptr() as usize
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}
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}
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}
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#[no_mangle]
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pub fn main_core1() {
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enable_fpu();
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debug!("Core1 started");
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ram::init_alloc_core1();
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gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts();
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let (mut core0_tx, mut core1_rx) = sync_channel!(Message, 4);
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let (mut core1_tx, core0_rx) = sync_channel!(Message, 4);
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unsafe {
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INIT_LOCK.lock();
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core0_tx.reset();
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core1_tx.reset();
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if !KERNEL_IMAGE.is_null() {
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// indicates forceful termination of previous kernel
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KERNEL_IMAGE = core::ptr::null();
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debug!("rtio init");
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rtio::init();
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}
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dma::init_dma_recorder();
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}
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*CHANNEL_0TO1.lock() = Some(core0_tx);
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*CHANNEL_1TO0.lock() = Some(core0_rx);
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// set on load, cleared on start
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let mut loaded_kernel = None;
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loop {
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let message = core1_rx.recv();
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match message {
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Message::LoadRequest(data) => {
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let result = dyld::load(&data, &resolve)
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.and_then(KernelImage::new);
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match result {
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Ok(kernel) => {
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loaded_kernel = Some(kernel);
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debug!("kernel loaded");
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core1_tx.send(Message::LoadCompleted);
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},
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Err(error) => {
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error!("failed to load shared library: {}", error);
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core1_tx.send(Message::LoadFailed);
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}
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}
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},
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Message::StartRequest => {
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info!("kernel starting");
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if let Some(kernel) = loaded_kernel.take() {
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unsafe {
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KERNEL_CHANNEL_0TO1 = Some(core1_rx);
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KERNEL_CHANNEL_1TO0 = Some(core1_tx);
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KERNEL_IMAGE = &kernel as *const KernelImage;
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kernel.exec();
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KERNEL_IMAGE = ptr::null();
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core1_rx = KERNEL_CHANNEL_0TO1.take().unwrap();
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core1_tx = KERNEL_CHANNEL_1TO0.take().unwrap();
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}
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}
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info!("kernel finished");
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core1_tx.send(Message::KernelFinished);
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}
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_ => error!("Core1 received unexpected message: {:?}", message),
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}
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}
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}
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/// Called by eh_artiq
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pub fn terminate(exception: &'static eh_artiq::Exception<'static>, backtrace: &'static mut [usize]) -> ! {
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let load_addr = unsafe {
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KERNEL_IMAGE.as_ref().unwrap().get_load_addr()
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};
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let mut cursor = 0;
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// The address in the backtrace is relocated, so we have to convert it back to the address in
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// the original python script, and remove those Rust function backtrace.
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for i in 0..backtrace.len() {
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if backtrace[i] >= load_addr {
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backtrace[cursor] = backtrace[i] - load_addr;
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cursor += 1;
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}
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}
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{
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let core1_tx = unsafe { KERNEL_CHANNEL_1TO0.as_mut().unwrap() };
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core1_tx.send(Message::KernelException(exception, &backtrace[..cursor]));
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}
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loop {}
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}
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/// Called by llvm_libunwind
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#[no_mangle]
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extern fn dl_unwind_find_exidx(pc: *const u32, len_ptr: *mut u32) -> *const u32 {
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let length;
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let start: *const u32;
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unsafe {
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if &__text_start as *const u32 <= pc && pc < &__text_end as *const u32 {
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length = (&__exidx_end as *const u32).offset_from(&__exidx_start) as u32;
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start = &__exidx_start;
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} else {
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let exidx = KERNEL_IMAGE.as_ref()
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.expect("dl_unwind_find_exidx kernel image")
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.library.get().as_ref().unwrap().exidx();
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length = exidx.len() as u32;
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start = exidx.as_ptr();
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}
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*len_ptr = length;
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}
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start
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}
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