artiq-zynq/src/libconfig/src
pca006132 04437e876c libconfig/load_pl: added alignment for devc buffer
According to the TRM, the buffer should be 64B aligned.
Without the alignment would cause failure for the DMA transaction.
It seems that the allocator would give some alignment, but to be more
correct we should specify that with the alloc interface.
2020-09-01 14:48:19 +08:00
..
lib.rs split config code into libconfig 2020-09-01 14:48:09 +08:00
load_pl.rs libconfig/load_pl: added alignment for devc buffer 2020-09-01 14:48:19 +08:00
net_settings.rs split config code into libconfig 2020-09-01 14:48:09 +08:00
sd_reader.rs split config code into libconfig 2020-09-01 14:48:09 +08:00