test compiler-builtins changes

runtime/kernel/dma: reduced replay overhead
We can just flush the cache once when we get the handle, instead of everytime before replay.
2020-10-13 19:21:22 +08:00 · 2020-09-09 21:18:26 +08:00
98 changed files with 26113 additions and 6118 deletions
--- a/README.md
+++ b/README.md
@ -24,47 +24,48 @@ The following configuration keys are available:
 - ``ip``: IPv4 address.
 - ``ip6``: IPv6 address.
 - ``startup``: startup kernel in ELF format (as produced by ``artiq_compile``).
- ``rtio_clock``: source of RTIO clock; valid values are ``ext0_bypass`` and ``int_125``.
- ``boot``: SD card "boot.bin" file, for replacing the boot firmware/gateware. Write only.
-
-Configurations can be read/written/removed via ``artiq_coremgmt``. Config erase is
-not implemented as it seems not very useful.
+- ``rtioclk``: source of RTIO clock; valid values are ``external`` and ``internal``.

 Development instructions
 ------------------------

-ARTIQ on Zynq is packaged using the [Nix](https://nixos.org) Flakes system. Install Nix 2.4+ and enable flakes by adding ``experimental-features = nix-command flakes`` to ``nix.conf`` (e.g. ``~/.config/nix/nix.conf``). 
+Configure Nix channels:
+
+```shell
+nix-channel --add https://nixbld.m-labs.hk/channel/custom/artiq/fast-beta/artiq-fast
+nix-channel --update
+```
+
+Note: if you are using Nix channels the first time, you need to be aware of this bug: https://github.com/NixOS/nix/issues/3831

 Pure build with Nix and execution on a remote JTAG server:

 ```shell
-nix build .#zc706-nist_clock-jtag  # or zc706-nist_qc2-jtag or zc706-nist_clock_satellite-jtag etc.
+nix-build -A zc706-simple-jtag  # or zc706-nist_qc2-jtag or zc706-nist_clock-jtag
 ./remote_run.sh
 ```

 Impure incremental build and execution on a remote JTAG server:

 ```shell
-nix develop
+nix-shell
 cd src
-gateware/zc706.py -g ../build/gateware -v <variant> # build gateware
-make GWARGS="-V <variant>" <runtime/satman>    # build firmware
+gateware/zc706.py -g ../build/gateware  # build gateware
+make                                    # build firmware
 cd ..
 ./remote_run.sh -i
 ```

 Notes:

+- This is known to work with Nixpkgs 20.03 and the ``nixbld.m-labs.hk`` binary substituter can also be used here (see the ARTIQ manual for the public key and instructions).
 - The impure build process is also compatible with non-Nix systems.
- When calling make, you need to specify both the variant and firmware type.
- Firmware type must be either ``runtime`` for DRTIO-less or DRTIO master variants, or ``satman`` for DRTIO satellite.
 - If the board is connected to the local machine, use the ``local_run.sh`` script.
- To update ``zynq-rs``, update the cargo files as per usual for Rust projects, but also keep ``flake.lock`` in sync.

 License
 -------

-Copyright (C) 2019-2022 M-Labs Limited.
+Copyright (C) 2019-2020 M-Labs Limited.

 ARTIQ is free software: you can redistribute it and/or modify
 it under the terms of the GNU Lesser General Public License as published by
--- a/cargo-xbuild.nix
+++ b/cargo-xbuild.nix
@ -0,0 +1,23 @@
+{ pkgs }:
+pkgs.rustPlatform.buildRustPackage rec {
+  pname = "cargo-xbuild";
+  version = "0.5.21";
+
+  src = pkgs.fetchFromGitHub {
+    owner = "rust-osdev";
+    repo = pname;
+    rev = "v${version}";
+    sha256 = "08mpnj3l6bcm1jg22lw1gcs0lkm4320fwl4p5y1s44w64963kzf7";
+  };
+
+  patches = [ ./cargo-xbuild.patch ];
+
+  cargoSha256 = "1pj4x8y5vfpnn8vhxqqm3vicn29870r3jh0b17q3riq4vz1a2afp";
+
+  meta = with pkgs.stdenv.lib; {
+    description = "Automatically cross-compiles the sysroot crates core, compiler_builtins, and alloc";
+    homepage = "https://github.com/rust-osdev/cargo-xbuild";
+    license = with licenses; [ mit asl20 ];
+    maintainers = with maintainers; [ johntitor xrelkd ];
+  };
+}
--- a/cargo-xbuild.patch
+++ b/cargo-xbuild.patch
@ -0,0 +1,14 @@
+diff --git a/src/sysroot.rs b/src/sysroot.rs
+index 1f3c8d1..e5615ee 100644
+--- a/src/sysroot.rs
+++ b/src/sysroot.rs
+@@ -163,7 +163,8 @@ version = "0.0.0"
+ edition = "2018"
+ 
+ [dependencies.compiler_builtins]
+-version = "0.1.0"
+git = "https://github.com/pca006132/compiler-builtins.git"
+branch = "pr"
+ "#;
+ 
+     let mut stoml = TOML.to_owned();
--- a/channel-rust-nightly.toml
+++ b/channel-rust-nightly.toml
--- a/default.nix
+++ b/default.nix
@ -0,0 +1,132 @@
+{
+  mozillaOverlay ? import (builtins.fetchTarball https://github.com/mozilla/nixpkgs-mozilla/archive/master.tar.gz),
+}:
+
+let
+  pkgs = import <nixpkgs> { overlays = [ mozillaOverlay ]; };
+  rustPlatform = (import ./rustPlatform.nix { inherit pkgs; });
+  artiqpkgs = import <artiq-fast/default.nix> { inherit pkgs; };
+  vivado = import <artiq-fast/vivado.nix> { inherit pkgs; };
+  zc706-fsbl = import ./fsbl.nix { inherit pkgs; };
+  mkbootimage = (import ./mkbootimage.nix { inherit pkgs; });
+  build-zc706 = { variant }: let
+    firmware = rustPlatform.buildRustPackage rec {
+      name = "zc706-${variant}-firmware";
+      version = "0.1.0";
+
+      src = ./src;
+      cargoSha256 = "0fpnwiqwscd8v48hpjzy0ydmiv3kl68lbl9j06nkybs9flj1r08a";
+
+      nativeBuildInputs = [
+        pkgs.gnumake
+        (pkgs.python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq ])))
+        pkgs.cargo-xbuild
+        pkgs.llvmPackages_9.llvm
+        pkgs.llvmPackages_9.clang-unwrapped
+      ];
+      buildPhase = ''
+        export XARGO_RUST_SRC="${rustPlatform.rust.rustc.src}/src"
+        export CARGO_HOME=$(mktemp -d cargo-home.XXX)
+        make VARIANT=${variant}
+      '';
+
+      installPhase = ''
+        mkdir -p $out $out/nix-support
+        cp ../build/runtime.bin $out/runtime.bin
+        cp ../build/firmware/armv7-none-eabihf/release/runtime $out/runtime.elf
+        cp ../build/firmware/armv7-none-eabihf/debug/szl $out/szl.elf
+        echo file binary-dist $out/runtime.bin >> $out/nix-support/hydra-build-products
+        echo file binary-dist $out/runtime.elf >> $out/nix-support/hydra-build-products
+        echo file binary-dist $out/szl.elf >> $out/nix-support/hydra-build-products
+      '';
+
+      doCheck = false;
+      dontFixup = true;
+    };
+    gateware = pkgs.runCommand "zc706-${variant}-gateware"
+      {
+        nativeBuildInputs = [ 
+          (pkgs.python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq ])))
+          vivado
+        ];
+      }
+      ''
+        python ${./src/gateware}/zc706.py -g build -V ${variant}
+        mkdir -p $out $out/nix-support
+        cp build/top.bit $out
+        echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
+      '';
+
+    # SZL startup
+    jtag = pkgs.runCommand "zc706-${variant}-jtag" {}
+      ''
+        mkdir $out
+        ln -s ${firmware}/szl.elf $out
+        ln -s ${firmware}/runtime.bin $out
+        ln -s ${gateware}/top.bit $out
+      '';
+    sd = pkgs.runCommand "zc706-${variant}-sd"
+      {
+        buildInputs = [ mkbootimage ];
+      }
+      ''
+      # Do not use "long" paths in boot.bif, because embedded developers
+      # can't write software (mkbootimage will segfault).
+      bifdir=`mktemp -d`
+      cd $bifdir
+      ln -s ${firmware}/szl.elf szl.elf
+      ln -s ${firmware}/runtime.elf runtime.elf
+      ln -s ${gateware}/top.bit top.bit
+      cat > boot.bif << EOF
+      the_ROM_image:
+      {
+        [bootloader]szl.elf
+        top.bit
+        runtime.elf
+      }
+      EOF
+      mkdir $out $out/nix-support
+      mkbootimage boot.bif $out/boot.bin
+      echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
+      '';
+
+    # FSBL startup
+    fsbl-sd = pkgs.runCommand "zc706-${variant}-fsbl-sd"
+      {
+        buildInputs = [ mkbootimage ];
+      }
+      ''
+      bifdir=`mktemp -d`
+      cd $bifdir
+      ln -s ${zc706-fsbl}/fsbl.elf fsbl.elf
+      ln -s ${gateware}/top.bit top.bit
+      ln -s ${firmware}/runtime.elf runtime.elf
+      cat > boot.bif << EOF
+      the_ROM_image:
+      {
+        [bootloader]fsbl.elf
+        top.bit
+        runtime.elf
+      }
+      EOF
+      mkdir $out $out/nix-support
+      mkbootimage boot.bif $out/boot.bin
+      echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
+      '';
+  in {
+    "zc706-${variant}-firmware" = firmware;
+    "zc706-${variant}-gateware" = gateware;
+    "zc706-${variant}-jtag" = jtag;
+    "zc706-${variant}-sd" = sd;
+    "zc706-${variant}-fsbl-sd" = fsbl-sd;
+  };
+in
+  (
+    (build-zc706 { variant = "simple"; }) //
+    (build-zc706 { variant = "nist_clock"; }) //
+    (build-zc706 { variant = "nist_qc2"; }) //
+    (build-zc706 { variant = "acpki_simple"; }) //
+    (build-zc706 { variant = "acpki_nist_clock"; }) //
+    (build-zc706 { variant = "acpki_nist_qc2"; }) //
+    { inherit zc706-fsbl; }
+  )
--- a/demo.json
+++ b/demo.json
@ -1,60 +0,0 @@
-{
-    "target": "kasli_soc",
-    "variant": "demo",
-    "hw_rev": "v1.0",
-    "base": "standalone",
-    "peripherals": [
-        {
-            "type": "grabber",
-            "ports": [0]
-        },
-        {
-            "type": "dio",
-            "ports": [1],
-            "bank_direction_low": "input",
-            "bank_direction_high": "output"
-        },
-        {
-            "type": "dio",
-            "ports": [2],
-            "bank_direction_low": "output",
-            "bank_direction_high": "output"
-        },
-        {
-            "type": "urukul",
-            "dds": "ad9910",
-            "ports": [3, 4],
-            "clk_sel": 2
-        },
-        {
-            "type": "zotino",
-            "ports": [5]
-        },
-        {
-            "type": "sampler",
-            "ports": [6, 7]
-        },
-        {
-            "type": "mirny",
-            "ports": [8],
-            "clk_sel": 1,
-            "refclk": 125e6
-        },
-        {
-            "type": "fastino",
-            "ports": [9]
-        },
-        {
-            "type": "dio",
-            "ports": [10],
-            "bank_direction_low": "input",
-            "bank_direction_high": "input"
-        },
-        {
-            "type": "dio",
-            "ports": [11],
-            "bank_direction_low": "output",
-            "bank_direction_high": "input"
-        }
-    ]
-}
--- a/examples/device_db.py
+++ b/examples/device_db.py
@ -29,11 +29,30 @@ device_db = {
        "class": "PCA9548"
    },

+    # led? are common to all variants
    "led0": {
        "type": "local",
        "module": "artiq.coredevice.ttl",
        "class": "TTLOut",
-        "arguments": {"channel": 41},
+        "arguments": {"channel": 0},
+    },
+    "led1": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 1},
+    },
+    "led2": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 2}
+    },
+    "led3": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 3}
    },
 }

@ -43,22 +62,9 @@ for i in range(40):
        "type": "local",
        "module": "artiq.coredevice.ttl",
        "class": "TTLInOut",
-        "arguments": {"channel": i}
+        "arguments": {"channel": 4+i}
    }

-device_db["ad9914dds0"] = {
-    "type": "local",
-    "module": "artiq.coredevice.ad9914",
-    "class": "AD9914",
-    "arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 0},
-}
-device_db["ad9914dds1"] = {
-    "type": "local",
-    "module": "artiq.coredevice.ad9914",
-    "class": "AD9914",
-    "arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 1},
-}
-
 # for ARTIQ test suite
 device_db.update(
    loop_out="ttl0",
--- a/flake.lock
+++ b/flake.lock
@ -1,188 +0,0 @@
-{
-  "nodes": {
-    "artiq": {
-      "inputs": {
-        "mozilla-overlay": "mozilla-overlay",
-        "nixpkgs": "nixpkgs",
-        "src-migen": "src-migen",
-        "src-misoc": "src-misoc",
-        "src-pythonparser": "src-pythonparser",
-        "src-sipyco": "src-sipyco"
-      },
-      "locked": {
-        "lastModified": 1644375232,
-        "narHash": "sha256-jd8sAlAz6xGQoxiRUV5ChtEjdjh4pdIksUPsqftcK5s=",
-        "ref": "master",
-        "rev": "a0070d4396136b84e0a50a1c57ee72bcf4e7f6f9",
-        "revCount": 7961,
-        "type": "git",
-        "url": "https://github.com/m-labs/artiq.git"
-      },
-      "original": {
-        "type": "git",
-        "url": "https://github.com/m-labs/artiq.git"
-      }
-    },
-    "mozilla-overlay": {
-      "flake": false,
-      "locked": {
-        "lastModified": 1643634764,
-        "narHash": "sha256-EcFlgzZnZSHwZixELYV1pa267t+u5mCeLhSNBeAA/+c=",
-        "owner": "mozilla",
-        "repo": "nixpkgs-mozilla",
-        "rev": "f233fdc4ff6ba2ffeb1e3e3cd6d63bb1297d6996",
-        "type": "github"
-      },
-      "original": {
-        "owner": "mozilla",
-        "repo": "nixpkgs-mozilla",
-        "type": "github"
-      }
-    },
-    "mozilla-overlay_2": {
-      "flake": false,
-      "locked": {
-        "lastModified": 1643634764,
-        "narHash": "sha256-EcFlgzZnZSHwZixELYV1pa267t+u5mCeLhSNBeAA/+c=",
-        "owner": "mozilla",
-        "repo": "nixpkgs-mozilla",
-        "rev": "f233fdc4ff6ba2ffeb1e3e3cd6d63bb1297d6996",
-        "type": "github"
-      },
-      "original": {
-        "owner": "mozilla",
-        "repo": "nixpkgs-mozilla",
-        "type": "github"
-      }
-    },
-    "mozilla-overlay_3": {
-      "flake": false,
-      "locked": {
-        "lastModified": 1638887313,
-        "narHash": "sha256-FMYV6rVtvSIfthgC1sK1xugh3y7muoQcvduMdriz4ag=",
-        "owner": "mozilla",
-        "repo": "nixpkgs-mozilla",
-        "rev": "7c1e8b1dd6ed0043fb4ee0b12b815256b0b9de6f",
-        "type": "github"
-      },
-      "original": {
-        "owner": "mozilla",
-        "repo": "nixpkgs-mozilla",
-        "type": "github"
-      }
-    },
-    "nixpkgs": {
-      "locked": {
-        "lastModified": 1643503720,
-        "narHash": "sha256-tJic20ufuRnG8V+fTCd3YU6xl1ImxNspoEkXHct0AG4=",
-        "owner": "NixOS",
-        "repo": "nixpkgs",
-        "rev": "0f316e4d72daed659233817ffe52bf08e081b5de",
-        "type": "github"
-      },
-      "original": {
-        "owner": "NixOS",
-        "ref": "nixos-21.11",
-        "repo": "nixpkgs",
-        "type": "github"
-      }
-    },
-    "root": {
-      "inputs": {
-        "artiq": "artiq",
-        "mozilla-overlay": "mozilla-overlay_2",
-        "zynq-rs": "zynq-rs"
-      }
-    },
-    "src-migen": {
-      "flake": false,
-      "locked": {
-        "lastModified": 1639659493,
-        "narHash": "sha256-qpVj/yJf4hDDc99XXpVPH4EbLC8aCmEtACn5qNc3DGI=",
-        "owner": "m-labs",
-        "repo": "migen",
-        "rev": "ac703010eaa06ac9b6e32f97c6fa98b15de22b31",
-        "type": "github"
-      },
-      "original": {
-        "owner": "m-labs",
-        "repo": "migen",
-        "type": "github"
-      }
-    },
-    "src-misoc": {
-      "flake": false,
-      "locked": {
-        "lastModified": 1641889368,
-        "narHash": "sha256-0Ai25lry9ju1HxFmfMRNKG8mamBqvw+kvDfpuK8Dtjo=",
-        "ref": "master",
-        "rev": "7242dc5a41732135425acc4871487461dfae6c66",
-        "revCount": 2419,
-        "submodules": true,
-        "type": "git",
-        "url": "https://github.com/m-labs/misoc.git"
-      },
-      "original": {
-        "submodules": true,
-        "type": "git",
-        "url": "https://github.com/m-labs/misoc.git"
-      }
-    },
-    "src-pythonparser": {
-      "flake": false,
-      "locked": {
-        "lastModified": 1628745371,
-        "narHash": "sha256-p6TgeeaK4NEmbhimEXp31W8hVRo4DgWmcCoqZ+UdN60=",
-        "owner": "m-labs",
-        "repo": "pythonparser",
-        "rev": "5413ee5c9f8760e95c6acd5d6e88dabb831ad201",
-        "type": "github"
-      },
-      "original": {
-        "owner": "m-labs",
-        "repo": "pythonparser",
-        "type": "github"
-      }
-    },
-    "src-sipyco": {
-      "flake": false,
-      "locked": {
-        "lastModified": 1641866796,
-        "narHash": "sha256-TSH0IgNbi9IcMcBDb2nWRphKlxstbWeATjrGbi6K2m0=",
-        "owner": "m-labs",
-        "repo": "sipyco",
-        "rev": "b04234c49379cd446d4cb3346d4741868d86841a",
-        "type": "github"
-      },
-      "original": {
-        "owner": "m-labs",
-        "repo": "sipyco",
-        "type": "github"
-      }
-    },
-    "zynq-rs": {
-      "inputs": {
-        "mozilla-overlay": "mozilla-overlay_3",
-        "nixpkgs": [
-          "artiq",
-          "nixpkgs"
-        ]
-      },
-      "locked": {
-        "lastModified": 1644558411,
-        "narHash": "sha256-PC/gVlVLmtZCv1Tw8Xz5ZCTxqmS2osncg5hlt9BoJ/8=",
-        "ref": "master",
-        "rev": "3e95df1f640aa761740feaf9eec797acb58dd942",
-        "revCount": 604,
-        "type": "git",
-        "url": "https://git.m-labs.hk/m-labs/zynq-rs"
-      },
-      "original": {
-        "type": "git",
-        "url": "https://git.m-labs.hk/m-labs/zynq-rs"
-      }
-    }
-  },
-  "root": "root",
-  "version": 7
-}
--- a/flake.nix
+++ b/flake.nix
@ -1,298 +0,0 @@
-{
-  description = "ARTIQ port to the Zynq-7000 platform";
-
-  inputs.artiq.url = git+https://github.com/m-labs/artiq.git;
-  inputs.mozilla-overlay = { url = github:mozilla/nixpkgs-mozilla; flake = false; };
-  inputs.zynq-rs.url = git+https://git.m-labs.hk/m-labs/zynq-rs;
-  inputs.zynq-rs.inputs.nixpkgs.follows = "artiq/nixpkgs";
-
-  outputs = { self, mozilla-overlay, zynq-rs, artiq }:
-  let
-    pkgs = import artiq.inputs.nixpkgs { system = "x86_64-linux"; overlays = [ (import mozilla-overlay) ]; };
-    zynqpkgs = zynq-rs.packages.x86_64-linux;
-    artiqpkgs = artiq.packages.x86_64-linux;
-
-    rustPlatform = zynq-rs.rustPlatform;
-
-    fastnumbers = pkgs.python3Packages.buildPythonPackage rec {
-      pname = "fastnumbers";
-      version = "2.2.1";
-
-      src = pkgs.python3Packages.fetchPypi {
-        inherit pname version;
-        sha256 = "0j15i54p7nri6hkzn1wal9pxri4pgql01wgjccig6ar0v5jjbvsy";
-      };
-    };
-
-    artiq-netboot = pkgs.python3Packages.buildPythonPackage rec {
-      pname = "artiq-netboot";
-      version = "unstable-2020-10-15";
-
-      src = pkgs.fetchgit {
-        url = "https://git.m-labs.hk/m-labs/artiq-netboot.git";
-        rev = "04f69eb07df73abe4b89fde2c24084f7664f2104";
-        sha256 = "0ql4fr8m8gpb2yql8aqsdqsssxb8zqd6l65kl1f6s9845zy7shs9";
-      };
-    };
-
-    ramda = pkgs.python3Packages.buildPythonPackage {
-      pname = "ramda";
-      version = "unstable-2019-02-01";
-
-      src = pkgs.fetchFromGitHub {
-        owner = "peteut";
-        repo = "ramda.py";
-        rev = "bd58f8e69d0e9a713d9c1f286a1ac5e5603956b1";
-        sha256 = "0qzd5yp9lbaham8p1wiymdjapzbqsli7lvngv24c3z4ybd9jlq9g";
-      };
-
-      nativeBuildInputs = with pkgs.python3Packages; [ pbr ];
-      propagatedBuildInputs = with pkgs.python3Packages; [ future fastnumbers ];
-
-      checkInputs = with pkgs.python3Packages; [ pytest pytest-flake8 ];
-      checkPhase = "pytest";
-      doCheck = false;
-
-      preBuild = ''
-        export PBR_VERSION=0.0.1
-      '';
-    };
-
-    migen-axi = pkgs.python3Packages.buildPythonPackage {
-      pname = "migen-axi";
-      version = "unstable-2021-09-15";
-
-      src = pkgs.fetchFromGitHub {
-        owner = "peteut";
-        repo = "migen-axi";
-        rev = "9763505ee96acd7572280a2d1233721342dc7c3f";
-        sha256 = "15c7g05n183rka66fl1glzp6h7xjlpy1p6k8biry24dangsmxmvg";
-      };
-
-      nativeBuildInputs = with pkgs.python3Packages; [ pbr ];
-      propagatedBuildInputs = with pkgs.python3Packages; [ setuptools click numpy toolz jinja2 ramda artiqpkgs.migen artiqpkgs.misoc ];
-
-      postPatch = ''
-        substituteInPlace requirements.txt \
-          --replace "jinja2==2.11.3" "jinja2"
-        substituteInPlace requirements.txt \
-          --replace "future==0.18.2" "future"
-        substituteInPlace requirements.txt \
-          --replace "ramda==0.5.5" "ramda"
-        substituteInPlace requirements.txt \
-          --replace "colorama==0.4.3" "colorama"
-        substituteInPlace requirements.txt \
-          --replace "toolz==0.10.0" "toolz"
-        substituteInPlace requirements.txt \
-          --replace "pyserial==3.4" "pyserial"
-        substituteInPlace requirements.txt \
-          --replace "markupsafe==1.1.1" "markupsafe"
-      '';
-
-      checkInputs = with pkgs.python3Packages; [ pytest pytest-timeout pytest-flake8 ];
-      checkPhase = "pytest";
-
-      preBuild = ''
-        export PBR_VERSION=0.0.1
-      '';
-    };
-    binutils = { platform, target, zlib }: pkgs.stdenv.mkDerivation rec {
-      basename = "binutils";
-      version = "2.30";
-      name = "${basename}-${platform}-${version}";
-      src = pkgs.fetchurl {
-        url = "https://ftp.gnu.org/gnu/binutils/binutils-${version}.tar.bz2";
-        sha256 = "028cklfqaab24glva1ks2aqa1zxa6w6xmc8q34zs1sb7h22dxspg";
-      };
-      configureFlags =
-        [ "--enable-shared" "--enable-deterministic-archives" "--target=${target}"];
-      outputs = [ "out" "info" "man" ];
-      depsBuildBuild = [ pkgs.buildPackages.stdenv.cc ];
-      buildInputs = [ zlib ];
-      enableParallelBuilding = true;
-    };
-    binutils-arm = pkgs.callPackage binutils { platform = "arm"; target = "armv7-unknown-linux-gnueabihf"; };
-
-    # FSBL configuration supplied by Vivado 2020.1 for these boards:
-    fsblTargets = ["zc702" "zc706" "zed"];
-    sat_variants = [
-      # kasli-soc satellite variants
-      "satellite"
-      # zc706 satellite variants
-      "nist_clock_satellite" "nist_qc2_satellite" "acpki_nist_clock_satellite" "acpki_nist_qc2_satellite" 
-      "nist_clock_satellite_100mhz" "nist_qc2_satellite_100mhz" "acpki_nist_clock_satellite_100mhz" "acpki_nist_qc2_satellite_100mhz"
-    ];
-    build = { target, variant, json ? null }: let
-      szl = zynqpkgs."${target}-szl";
-      fsbl = zynqpkgs."${target}-fsbl";
-      fwtype = if builtins.elem variant sat_variants then "satman" else "runtime";
-
-      firmware = rustPlatform.buildRustPackage rec {
-
-        name = "firmware";
-        src = ./src;
-        cargoLock = { 
-          lockFile = src/Cargo.lock;
-          outputHashes = {
-            "libasync-0.0.0" = "sha256-PC/gVlVLmtZCv1Tw8Xz5ZCTxqmS2osncg5hlt9BoJ/8=";
-          };
-        };
-
-        nativeBuildInputs = [
-          pkgs.gnumake
-          (pkgs.python3.withPackages(ps: (with artiqpkgs; [ ps.jsonschema migen migen-axi misoc artiq ])))
-          artiqpkgs.artiq
-          zynqpkgs.cargo-xbuild
-          pkgs.llvmPackages_9.llvm
-          pkgs.llvmPackages_9.clang-unwrapped
-        ];
-        buildPhase = ''
-          export XARGO_RUST_SRC="${rustPlatform.rust.rustc}/lib/rustlib/src/rust/library"
-          export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_9.clang-unwrapped.lib}/lib/clang/9.0.1/include"
-          export CARGO_HOME=$(mktemp -d cargo-home.XXX)
-          make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype}
-        '';
-
-        installPhase = ''
-          mkdir -p $out $out/nix-support
-          cp ../build/${fwtype}.bin $out/${fwtype}.bin
-          cp ../build/firmware/armv7-none-eabihf/release/${fwtype} $out/${fwtype}.elf
-          echo file binary-dist $out/${fwtype}.bin >> $out/nix-support/hydra-build-products
-          echo file binary-dist $out/${fwtype}.elf >> $out/nix-support/hydra-build-products
-        '';
-
-        doCheck = false;
-        dontFixup = true;
-      };
-      gateware = pkgs.runCommand "${target}-${variant}-gateware"
-        {
-          nativeBuildInputs = [ 
-            (pkgs.python3.withPackages(ps: (with artiqpkgs; [ ps.jsonschema migen migen-axi misoc artiq ])))
-            artiqpkgs.artiq
-            artiqpkgs.vivado
-          ];
-        }
-        ''
-          python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json}
-          mkdir -p $out $out/nix-support
-          cp build/top.bit $out
-          echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
-        '';
-
-      # SZL startup
-      jtag = pkgs.runCommand "${target}-${variant}-jtag" {}
-        ''
-          mkdir $out
-          ln -s ${szl}/szl.elf $out
-          ln -s ${firmware}/${fwtype}.bin $out
-          ln -s ${gateware}/top.bit $out
-        '';
-      sd = pkgs.runCommand "${target}-${variant}-sd"
-        {
-          buildInputs = [ zynqpkgs.mkbootimage ];
-        }
-        ''
-          # Do not use "long" paths in boot.bif, because embedded developers
-          # can't write software (mkbootimage will segfault).
-          bifdir=`mktemp -d`
-          cd $bifdir
-          ln -s ${szl}/szl.elf szl.elf
-          ln -s ${firmware}/${fwtype}.elf ${fwtype}.elf
-          ln -s ${gateware}/top.bit top.bit
-          cat > boot.bif << EOF
-          the_ROM_image:
-          {
-            [bootloader]szl.elf
-            top.bit
-            ${fwtype}.elf
-          }
-          EOF
-          mkdir $out $out/nix-support
-          mkbootimage boot.bif $out/boot.bin
-          echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
-        '';
-
-      # FSBL startup
-      fsbl-sd = pkgs.runCommand "${target}-${variant}-fsbl-sd"
-        {
-          buildInputs = [ zynqpkgs.mkbootimage ];
-        }
-        ''
-          bifdir=`mktemp -d`
-          cd $bifdir
-          ln -s ${fsbl}/fsbl.elf fsbl.elf
-          ln -s ${gateware}/top.bit top.bit
-          ln -s ${firmware}/${fwtype}.elf ${fwtype}.elf
-          cat > boot.bif << EOF
-          the_ROM_image:
-          {
-            [bootloader]fsbl.elf
-            top.bit
-            ${fwtype}.elf
-          }
-          EOF
-          mkdir $out $out/nix-support
-          mkbootimage boot.bif $out/boot.bin
-          echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
-        '';
-    in {
-      "${target}-${variant}-firmware" = firmware;
-      "${target}-${variant}-gateware" = gateware;
-      "${target}-${variant}-jtag" = jtag;
-      "${target}-${variant}-sd" = sd;
-    } // (
-      if builtins.elem target fsblTargets
-      then {
-        "${target}-${variant}-fsbl-sd" = fsbl-sd;
-      }
-      else {}
-    );
-  in rec {
-    packages.x86_64-linux = (build { target = "zc706"; variant = "nist_clock"; }) //
-      (build { target = "zc706"; variant = "nist_clock_master"; }) //
-      (build { target = "zc706"; variant = "nist_clock_satellite"; }) //
-      (build { target = "zc706"; variant = "nist_clock_satellite_100mhz"; }) //
-      (build { target = "zc706"; variant = "nist_qc2"; }) //
-      (build { target = "zc706"; variant = "nist_qc2_master"; }) //
-      (build { target = "zc706"; variant = "nist_qc2_satellite"; }) //
-      (build { target = "zc706"; variant = "nist_qc2_satellite_100mhz"; }) //
-      (build { target = "zc706"; variant = "acpki_nist_clock"; }) //
-      (build { target = "zc706"; variant = "acpki_nist_clock_master"; }) //
-      (build { target = "zc706"; variant = "acpki_nist_clock_satellite"; }) //
-      (build { target = "zc706"; variant = "acpki_nist_clock_satellite_100mhz"; }) //
-      (build { target = "zc706"; variant = "acpki_nist_qc2"; }) //
-      (build { target = "zc706"; variant = "acpki_nist_qc2_master"; }) //
-      (build { target = "zc706"; variant = "acpki_nist_qc2_satellite"; }) //
-      (build { target = "zc706"; variant = "acpki_nist_qc2_satellite_100mhz"; }) //
-      (build { target = "kasli_soc"; variant = "demo"; json = ./demo.json; }) //
-      (build { target = "kasli_soc"; variant = "master"; json = ./kasli-soc-master.json; }) //
-      (build { target = "kasli_soc"; variant = "satellite"; json = ./kasli-soc-satellite.json; });
-
-    hydraJobs = packages.x86_64-linux;
-
-    devShell.x86_64-linux = pkgs.mkShell {
-      name = "artiq-zynq-dev-shell";
-      buildInputs = with pkgs; [
-        rustPlatform.rust.rustc
-        rustPlatform.rust.cargo
-        llvmPackages_9.llvm
-        llvmPackages_9.clang-unwrapped
-        gnumake
-        cacert
-        zynqpkgs.cargo-xbuild
-        zynqpkgs.mkbootimage
-        openocd  
-        openssh rsync
-        (python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq artiq-netboot ps.jsonschema ps.pyftdi ])))
-        artiqpkgs.artiq
-        artiqpkgs.vivado
-        binutils-arm
-      ];
-      XARGO_RUST_SRC = "${rustPlatform.rust.rustc}/lib/rustlib/src/rust/library";
-      CLANG_EXTRA_INCLUDE_DIR = "${pkgs.llvmPackages_9.clang-unwrapped.lib}/lib/clang/9.0.1/include";
-      OPENOCD_ZYNQ = "${zynq-rs}/openocd";
-      SZL = "${zynqpkgs.szl}";
-    };
-
-  };
-}
--- a/fsbl.nix
+++ b/fsbl.nix
@ -0,0 +1,37 @@
+{ pkgs, board ? "zc706" }:
+let
+  gnutoolchain = import ./gnutoolchain.nix { inherit pkgs; };
+in
+pkgs.stdenv.mkDerivation {
+  name = "${board}-fsbl";
+  src = pkgs.fetchFromGitHub {
+    owner = "Xilinx";
+    repo = "embeddedsw";
+    rev = "65c849ed46c88c67457e1fc742744f96db968ff1";
+    sha256 = "1rvl06ha40dzd6s9aa4sylmksh4xb9dqaxq462lffv1fdk342pda";
+  };
+  patches = [ ./fsbl.patch ];
+  nativeBuildInputs = [
+    pkgs.gnumake
+    gnutoolchain.binutils
+    gnutoolchain.gcc
+  ];
+  patchPhase =
+    ''
+    patch -p1 -i ${./fsbl.patch}
+    patchShebangs lib/sw_apps/zynq_fsbl/misc/copy_bsp.sh
+    echo 'SEARCH_DIR("${gnutoolchain.newlib}/arm-none-eabi/lib");' >> lib/sw_apps/zynq_fsbl/src/lscript.ld
+    '';
+  buildPhase =
+    ''
+    cd lib/sw_apps/zynq_fsbl/src
+    make BOARD=${board} "CFLAGS=-DFSBL_DEBUG_INFO -g"
+    '';
+  installPhase = 
+    ''
+    mkdir $out
+    cp fsbl.elf $out
+    '';
+  doCheck = false;
+  dontFixup = true;
+}
--- a/fsbl.patch
+++ b/fsbl.patch
@ -0,0 +1,31 @@
+diff --git a/lib/sw_apps/zynq_fsbl/src/Makefile b/lib/sw_apps/zynq_fsbl/src/Makefile
+index 0e3ccdf1c5..a5b02f386e 100644
+--- a/lib/sw_apps/zynq_fsbl/src/Makefile
+++ b/lib/sw_apps/zynq_fsbl/src/Makefile
+@@ -71,11 +71,14 @@ endif
+ all: $(EXEC)
+ 
+ $(EXEC): $(LIBS) $(OBJS) $(INCLUDES)
+-	cp $(BSP_DIR)/$(BOARD)/ps7_init.* .
+ 	$(LINKER) $(LD1FLAGS)  -o $@ $(OBJS) $(LDFLAGS)
+ 	rm -rf $(OBJS)
+-	
+-	
+
+.PHONY: ps7_init
+
+ps7_init:
+	cp $(BSP_DIR)/$(BOARD)/ps7_init.* .
+
+ $(LIBS): 
+ 	echo "Copying BSP files"
+ 	$(BSP_DIR)/copy_bsp.sh $(BOARD) $(CC)
+@@ -86,7 +89,7 @@ $(LIBS):
+         make -C $(BSP_DIR) -k all "CC=armcc" "AR=armar" "C_FLAGS= -O2 -c" "EC_FLAGS=--debug --wchar32"; \
+ 	fi;
+ 
+-%.o:%.c
+%.o:%.c ps7_init
+ 	$(CC) $(CC_FLAGS) $(CFLAGS) $(ECFLAGS) -c $< -o $@ $(INCLUDEPATH)
+ 
+ %.o:%.S
--- a/gnutoolchain.nix
+++ b/gnutoolchain.nix
@ -0,0 +1,134 @@
+{ pkgs ? import <nixpkgs> }:
+let 
+
+platform = "arm-none-eabi";
+
+binutils-pkg = { stdenv, buildPackages
+, fetchurl, zlib
+, extraConfigureFlags ? []
+}:
+
+stdenv.mkDerivation rec {
+  basename = "binutils";
+  version = "2.30";
+  name = "${basename}-${platform}-${version}";
+  src = fetchurl {
+    url = "https://ftp.gnu.org/gnu/binutils/binutils-${version}.tar.bz2";
+    sha256 = "028cklfqaab24glva1ks2aqa1zxa6w6xmc8q34zs1sb7h22dxspg";
+  };
+  configureFlags = [
+    "--enable-deterministic-archives"
+    "--target=${platform}"
+    "--with-cpu=cortex-a9"
+    "--with-fpu=vfpv3"
+    "--with-float=hard"
+    "--with-mode=thumb"
+  ] ++ extraConfigureFlags;
+  outputs = [ "out" "info" "man" ];
+  depsBuildBuild = [ buildPackages.stdenv.cc ];
+  buildInputs = [ zlib ];
+  enableParallelBuilding = true;
+  meta = {
+    description = "Tools for manipulating binaries (linker, assembler, etc.)";
+    longDescription = ''
+      The GNU Binutils are a collection of binary tools.  The main
+      ones are `ld' (the GNU linker) and `as' (the GNU assembler).
+      They also include the BFD (Binary File Descriptor) library,
+      `gprof', `nm', `strip', etc.
+    '';
+    homepage = http://www.gnu.org/software/binutils/;
+    license = stdenv.lib.licenses.gpl3Plus;
+    /* Give binutils a lower priority than gcc-wrapper to prevent a
+       collision due to the ld/as wrappers/symlinks in the latter. */
+    priority = "10";
+  };
+};
+
+
+gcc-pkg = { stdenv, buildPackages
+, fetchurl, gmp, mpfr, libmpc, platform-binutils
+, extraConfigureFlags ? []
+}:
+
+stdenv.mkDerivation rec {
+  basename = "gcc";
+  version = "9.1.0";
+  name = "${basename}-${platform}-${version}";
+  src = fetchurl {
+    url = "https://ftp.gnu.org/gnu/gcc/gcc-${version}/gcc-${version}.tar.xz";
+    sha256 = "1817nc2bqdc251k0lpc51cimna7v68xjrnvqzvc50q3ax4s6i9kr";
+  };
+  preConfigure =
+    ''
+    mkdir build
+    cd build
+    '';
+  configureScript = "../configure";
+  configureFlags =
+    [ "--target=${platform}"
+      "--with-arch=armv7-a"
+      "--with-tune=cortex-a9"
+      "--with-fpu=vfpv3"
+      "--with-float=hard"
+      "--disable-libssp"
+      "--enable-languages=c"
+      "--with-as=${platform-binutils}/bin/${platform}-as"
+      "--with-ld=${platform-binutils}/bin/${platform}-ld" ] ++ extraConfigureFlags;
+  outputs = [ "out" "info" "man" ];
+  hardeningDisable = [ "format" "pie" ];
+  propagatedBuildInputs = [ gmp mpfr libmpc platform-binutils ];
+  enableParallelBuilding = true;
+  dontFixup = true;
+};
+
+
+newlib-pkg = { stdenv, fetchurl, buildPackages, platform-binutils, platform-gcc }:
+
+stdenv.mkDerivation rec {
+  pname = "newlib";
+  version = "3.1.0";
+  src = fetchurl {
+    url = "ftp://sourceware.org/pub/newlib/newlib-${version}.tar.gz";
+    sha256 = "0ahh3n079zjp7d9wynggwrnrs27440aac04340chf1p9476a2kzv";
+  };
+
+  nativeBuildInputs = [ platform-binutils platform-gcc ];
+
+  configureFlags = [
+    "--target=${platform}"
+
+    "--with-cpu=cortex-a9"
+    "--with-fpu=vfpv3"
+    "--with-float=hard"
+    "--with-mode=thumb"
+    "--enable-interwork"
+    "--disable-multilib"
+
+    "--disable-newlib-supplied-syscalls"
+    "--with-gnu-ld"
+    "--with-gnu-as"
+    "--disable-newlib-io-float"
+    "--disable-werror"
+  ];
+  dontFixup = true;
+};
+
+
+in rec {
+  binutils-bootstrap = pkgs.callPackage binutils-pkg { };
+  gcc-bootstrap = pkgs.callPackage gcc-pkg {
+    platform-binutils = binutils-bootstrap;
+    extraConfigureFlags = [ "--disable-libgcc" ];
+  };
+  newlib = pkgs.callPackage newlib-pkg {
+    platform-binutils = binutils-bootstrap;
+    platform-gcc = gcc-bootstrap;
+  };
+  binutils = pkgs.callPackage binutils-pkg {
+    extraConfigureFlags = [ "--with-lib-path=${newlib}/arm-none-eabi/lib" ];
+  };
+  gcc = pkgs.callPackage gcc-pkg {
+    platform-binutils = binutils;
+    extraConfigureFlags = [ "--enable-newlib" "--with-headers=${newlib}/arm-none-eabi/include" ];
+  };
+}
--- a/kasli-soc-master.json
+++ b/kasli-soc-master.json
@ -1,60 +0,0 @@
-{
-    "target": "kasli_soc",
-    "variant": "master",
-    "hw_rev": "v1.0",
-    "base": "master",
-    "peripherals": [
-        {
-            "type": "grabber",
-            "ports": [0]
-        },
-        {
-            "type": "dio",
-            "ports": [1],
-            "bank_direction_low": "input",
-            "bank_direction_high": "output"
-        },
-        {
-            "type": "dio",
-            "ports": [2],
-            "bank_direction_low": "output",
-            "bank_direction_high": "output"
-        },
-        {
-            "type": "urukul",
-            "dds": "ad9910",
-            "ports": [3, 4],
-            "clk_sel": 2
-        },
-        {
-            "type": "zotino",
-            "ports": [5]
-        },
-        {
-            "type": "sampler",
-            "ports": [6, 7]
-        },
-        {
-            "type": "mirny",
-            "ports": [8],
-            "clk_sel": 1,
-            "refclk": 125e6
-        },
-        {
-            "type": "fastino",
-            "ports": [9]
-        },
-        {
-            "type": "dio",
-            "ports": [10],
-            "bank_direction_low": "input",
-            "bank_direction_high": "input"
-        },
-        {
-            "type": "dio",
-            "ports": [11],
-            "bank_direction_low": "output",
-            "bank_direction_high": "input"
-        }
-    ]
-}
--- a/kasli-soc-satellite.json
+++ b/kasli-soc-satellite.json
@ -1,60 +0,0 @@
-{
-    "target": "kasli_soc",
-    "variant": "satellite",
-    "hw_rev": "v1.0",
-    "base": "satellite",
-    "peripherals": [
-        {
-            "type": "grabber",
-            "ports": [0]
-        },
-        {
-            "type": "dio",
-            "ports": [1],
-            "bank_direction_low": "input",
-            "bank_direction_high": "output"
-        },
-        {
-            "type": "dio",
-            "ports": [2],
-            "bank_direction_low": "output",
-            "bank_direction_high": "output"
-        },
-        {
-            "type": "urukul",
-            "dds": "ad9910",
-            "ports": [3, 4],
-            "clk_sel": 2
-        },
-        {
-            "type": "zotino",
-            "ports": [5]
-        },
-        {
-            "type": "sampler",
-            "ports": [6, 7]
-        },
-        {
-            "type": "mirny",
-            "ports": [8],
-            "clk_sel": 1,
-            "refclk": 125e6
-        },
-        {
-            "type": "fastino",
-            "ports": [9]
-        },
-        {
-            "type": "dio",
-            "ports": [10],
-            "bank_direction_low": "input",
-            "bank_direction_high": "input"
-        },
-        {
-            "type": "dio",
-            "ports": [11],
-            "bank_direction_low": "output",
-            "bank_direction_high": "input"
-        }
-    ]
-}
--- a/local_run.sh
+++ b/local_run.sh
@ -2,21 +2,11 @@

 set -e

-if [ -z "$OPENOCD_ZYNQ" ]; then
-    echo "OPENOCD_ZYNQ environment variable must be set"
-    exit 1
-fi
-if [ -z "$SZL" ]; then
-    echo "SZL environment variable must be set"
-    exit 1
-fi
-
 impure=0
 load_bitstream=1
-board_type="kasli_soc"
-fw_type="runtime"
+board_host="192.168.1.52"

-while getopts "ilb:t:f:" opt; do
+while getopts "ilb:" opt; do
    case "$opt" in
    \?) exit 1
        ;;
@ -26,36 +16,24 @@ while getopts "ilb:t:f:" opt; do
        ;;
    b)  board_host=$OPTARG
        ;;
-    t)  board_type=$OPTARG
-        ;;
-    f)  fw_type=$OPTARG
-        ;;
    esac
 done

-if [ -z "$board_host" ]; then
-    case $board_type in
-    kasli_soc) board_host="192.168.1.56";;
-    zc706) board_host="192.168.1.52";;
-    *) echo "Unknown board type"; exit 1;;
-    esac
-fi
-
 load_bitstream_cmd=""

-build_dir=`pwd`/build
-result_dir=`pwd`/result
-cd $OPENOCD_ZYNQ
-openocd -f $board_type.cfg -c "load_image $SZL/szl-$board_type.elf; resume 0; exit"
-sleep 5
+cd openocd
 if [ $impure -eq 1 ]; then
    if [ $load_bitstream -eq 1 ]; then
-        load_bitstream_cmd="-g $build_dir/gateware/top.bit"
+        load_bitstream_cmd="-g ../build/gateware/top.bit"
    fi
-    artiq_netboot $load_bitstream_cmd -f $build_dir/$fw_type.bin -b $board_host
+    openocd -f zc706.cfg -c "load_image ../build/firmware/armv7-none-eabihf/debug/szl; resume 0; exit"
+    sleep 5
+    artiq_netboot $load_bitstream_cmd -f ../build/runtime.bin -b $board_host
 else
    if [ $load_bitstream -eq 1 ]; then
-        load_bitstream_cmd="-g $result_dir/top.bit"
+        load_bitstream_cmd="-g ../result/top.bit"
    fi
-    artiq_netboot $load_bitstream_cmd -f $result_dir/$fw_type.bin -b $board_host
-fi
+    openocd -f zc706.cfg -c "load_image ../result/szl.elf; resume 0; exit"
+    sleep 5
+    artiq_netboot $load_bitstream_cmd -f ../result/runtime.bin -b $board_host
+fi
--- a/mkbootimage.nix
+++ b/mkbootimage.nix
@ -0,0 +1,24 @@
+{ pkgs }:
+
+pkgs.stdenv.mkDerivation {
+  pname = "mkbootimage";
+  version = "2.2";
+
+  src = pkgs.fetchFromGitHub {
+    owner = "antmicro";
+    repo = "zynq-mkbootimage";
+    rev = "4ee42d782a9ba65725ed165a4916853224a8edf7";
+    sha256 = "1k1mbsngqadqihzjgvwvsrkvryxy5ladpxd9yh9iqn2s7fxqwqa9";
+  };
+
+  propagatedBuildInputs = [ pkgs.libelf pkgs.pcre ];
+  patchPhase =
+    ''
+    substituteInPlace Makefile --replace "git rev-parse --short HEAD" "echo nix"
+    '';
+  installPhase =
+    ''
+    mkdir -p $out/bin
+    cp mkbootimage $out/bin
+    '';
+}
--- a/openocd/digilent_jtag_smt2_nc.cfg
+++ b/openocd/digilent_jtag_smt2_nc.cfg
@ -0,0 +1,18 @@
+#
+# Digilent JTAG-SMT2-NC
+#
+# http://store.digilentinc.com/jtag-smt2-nc-surface-mount-programming-module/
+# https://reference.digilentinc.com/_media/jtag_smt2nc/jtag-smt2-nc_rm.pdf
+#
+# Based on reference sheet (above) and Xilinx KCU105 schematics
+# https://www.xilinx.com/products/boards-and-kits/kcu105.html#documentation
+#
+# Note that the digilent_jtag_smt2 layout does not work and hangs while
+# the ftdi_device_desc from digilent_hs2 is wrong.
+
+interface ftdi
+ftdi_device_desc "Digilent USB Device"
+ftdi_vid_pid 0x0403 0x6014
+ftdi_channel 0
+ftdi_layout_init 0x00e8 0x60eb
+ftdi_layout_signal nSRST -data 0x2000
--- a/openocd/zc706.cfg
+++ b/openocd/zc706.cfg
@ -0,0 +1,40 @@
+source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+adapter_khz 1000
+
+set PL_TAPID 0x23731093
+set SMP 1
+
+source ./zynq-7000.cfg
+
+reset_config srst_only srst_open_drain
+adapter_nsrst_assert_width 250
+adapter_nsrst_delay 400
+
+set XC7_JSHUTDOWN 0x0d
+set XC7_JPROGRAM 0x0b
+set XC7_JSTART 0x0c
+set XC7_BYPASS 0x3f
+
+proc xc7_program {tap} {
+    global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
+    irscan $tap $XC7_JSHUTDOWN
+    irscan $tap $XC7_JPROGRAM
+    runtest 60000
+    #JSTART prevents this from working...
+    #irscan $tap $XC7_JSTART
+    runtest 2000
+    irscan $tap $XC7_BYPASS
+    runtest 2000
+}
+
+pld device virtex2 zynq.tap 1
+init
+xc7_program zynq.tap
+
+reset halt
+
+# Disable MMU
+targets $_TARGETNAME_1
+arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]
+targets $_TARGETNAME_0
+arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]
--- a/openocd/zynq-7000.cfg
+++ b/openocd/zynq-7000.cfg
@ -0,0 +1,95 @@
+#
+# Xilinx Zynq 7000 SoC
+#
+#  Chris Johns <chrisj@rtems.org>
+#
+# Setup
+# -----
+#
+# Create a user configuration following the "Configuration Basics" in the user
+# documentation. In the file have:
+#
+#    source [find interface/ftdi/flyswatter2.cfg]
+#    source [find board/zynq-zc706-eval.cfg]
+#    adapter_khz 2000
+#    init
+#
+
+if { [info exists CHIPNAME] } {
+    global _CHIPNAME
+    set _CHIPNAME $CHIPNAME
+} else {
+    global _CHIPNAME
+    set _CHIPNAME zynq
+}
+
+if { [info exists ENDIAN] } {
+    set _ENDIAN $ENDIAN
+} else {
+    # this defaults to a bigendian
+    set _ENDIAN little
+}
+
+if { [info exists SMP] } {
+    global _SMP
+    set _SMP 1
+} else {
+    global _SMP
+    set _SMP 0
+}
+
+#
+# PL Tap.
+#
+# See ug585 ZYNQ-7000 TRM PSS_IDCODE for how this number is constructed.
+#   0x03731093 - ZC706 Eval board 1.1
+#   0x23731093 - ??
+#   0x23727093 - Zedboard Rev. C and D
+#
+# Set in your configuration file or board specific file.
+#
+if { [info exists PL_TAPID] } {
+    set _PL_TAPID $PL_TAPID
+} else {
+    set _PL_TAPID 0x03731093
+}
+
+jtag newtap $_CHIPNAME tap -irlen 6 -ircapture 0x001 -irmask 0x003 \
+    -expected-id $_PL_TAPID
+
+#
+# CoreSight Debug Access Port
+#
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x03 \
+    -expected-id $_DAP_TAPID
+
+#
+# GDB target: Cortex-A9, using DAP, configuring only one core
+# Base addresses of cores:
+# core 0  -  0xF8890000
+# core 1  -  0xF8892000
+#
+# Read from the ROM table with the patch to read the nested table.
+#
+
+set _TARGETNAME_0 $_CHIPNAME.cpu.0
+set _TARGETNAME_1 $_CHIPNAME.cpu.1
+
+target create $_TARGETNAME_0 cortex_a -coreid 0 \
+    -endian $_ENDIAN \
+    -chain-position $_CHIPNAME.dap \
+    -dbgbase 0x80090000
+if { $_SMP } {
+    echo "Zynq CPU1."
+    target create $_TARGETNAME_1 cortex_a -coreid 1 \
+        -endian $_ENDIAN \
+        -chain-position $_CHIPNAME.dap \
+        -dbgbase 0x80092000
+    target smp $_TARGETNAME_0 $_TARGETNAME_1
+}
--- a/remote_run.sh
+++ b/remote_run.sh
@ -1,18 +1,7 @@
 #!/usr/bin/env bash

-# Only ZC706 supported for now.
-
 set -e

-if [ -z "$OPENOCD_ZYNQ" ]; then
-    echo "OPENOCD_ZYNQ environment variable must be set"
-    exit 1
-fi
-if [ -z "$SZL" ]; then
-    echo "SZL environment variable must be set"
-    exit 1
-fi
-
 target_host="rpi-4.m-labs.hk"
 impure=0
 pure_dir="result"
@ -20,9 +9,8 @@ impure_dir="build"
 sshopts=""
 load_bitstream=1
 board_host="192.168.1.52"
-fw_type="runtime"

-while getopts "h:id:o:lt:" opt; do
+while getopts "h:id:o:l" opt; do
    case "$opt" in
    \?) exit 1
        ;;
@ -39,8 +27,6 @@ while getopts "h:id:o:lt:" opt; do
        ;;
    b)  board_host=$OPTARG
        ;;
-    t)  fw_type=$OPTARG
-        ;;
    esac
 done

@ -50,18 +36,19 @@ load_bitstream_cmd=""
 echo "Creating $target_folder..."
 ssh $sshopts $target_host "mkdir -p $target_folder"
 echo "Copying files..."
-rsync -e "ssh $sshopts" -Lc $OPENOCD_ZYNQ/* $target_host:$target_folder
-rsync -e "ssh $sshopts" -Lc $SZL/szl-zc706.elf $target_host:$target_folder/szl.elf
+rsync -e "ssh $sshopts" openocd/* $target_host:$target_folder
 if [ $impure -eq 1 ]; then
    if [ $load_bitstream -eq 1 ]; then
        load_bitstream_cmd="-g build/gateware/top.bit"
    fi
-    firmware="build/$fw_type.bin"
+    firmware="build/runtime.bin"
+    rsync -e "ssh $sshopts" $impure_dir/firmware/armv7-none-eabihf/debug/szl $target_host:$target_folder/szl.elf
 else
    if [ $load_bitstream -eq 1 ]; then
        load_bitstream_cmd="-g $pure_dir/top.bit"
    fi
-    firmware="$pure_dir/$fw_type.bin"    
+    firmware="$pure_dir/runtime.bin"
+    rsync -e "ssh $sshopts" -Lc $pure_dir/szl.elf $target_host:$target_folder
 fi
 echo "Programming board..."
 ssh $sshopts $target_host "cd $target_folder; openocd -f zc706.cfg -c'load_image szl.elf; resume 0; exit'"
--- a/rustPlatform.nix
+++ b/rustPlatform.nix
@ -0,0 +1,24 @@
+{ pkgs }:
+
+let
+  rustcSrc = pkgs.fetchgit {
+    url = "https://github.com/rust-lang/rust.git";
+    # sync with git_commit_hash from pkg.rust in channel-rust-nightly.toml
+    rev = "5ef299eb9805b4c86b227b718b39084e8bf24454";
+    sha256 = "0gc9hmb1sfkaf3ba8fsynl1n6bs8nk65hbhhx7ss89dfkrsxrn0x";
+    fetchSubmodules = true;
+  };
+  rustManifest = ./channel-rust-nightly.toml;
+
+  targets = [];
+  rustChannelOfTargets = _channel: _date: targets:
+    (pkgs.lib.rustLib.fromManifestFile rustManifest {
+      inherit (pkgs) stdenv fetchurl patchelf;
+    }).rust.override { inherit targets; };
+  rust =
+    rustChannelOfTargets "nightly" null targets;
+in
+  pkgs.recurseIntoAttrs (pkgs.makeRustPlatform {
+    rustc = rust // { src = rustcSrc; };
+    cargo = rust;
+  })
--- a/shell.nix
+++ b/shell.nix
@ -0,0 +1,32 @@
+let
+  mozillaOverlay = import (builtins.fetchTarball "https://github.com/mozilla/nixpkgs-mozilla/archive/master.tar.gz");
+  pkgs = import <nixpkgs> { overlays = [ mozillaOverlay ]; };
+  artiq-fast = <artiq-fast>;
+  rustPlatform = (import ./rustPlatform.nix { inherit pkgs; });
+  artiqpkgs = import "${artiq-fast}/default.nix" { inherit pkgs; };
+  vivado = import "${artiq-fast}/vivado.nix" { inherit pkgs; };
+  cargo-xbuild = import ./cargo-xbuild.nix { inherit pkgs; };
+in
+  pkgs.stdenv.mkDerivation {
+    name = "artiq-zynq-env";
+    buildInputs = [
+      pkgs.gnumake
+      rustPlatform.rust.rustc
+      rustPlatform.rust.cargo
+      pkgs.llvmPackages_9.llvm
+      pkgs.llvmPackages_9.clang-unwrapped
+      pkgs.cacert
+      cargo-xbuild
+
+      pkgs.openocd
+      pkgs.openssh pkgs.rsync
+
+      (pkgs.python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq ])))
+      vivado
+      artiqpkgs.binutils-arm
+
+      (import ./mkbootimage.nix { inherit pkgs; })
+    ];
+
+    XARGO_RUST_SRC = "${rustPlatform.rust.rustc.src}/src";
+  }
--- a/src/Cargo.lock
+++ b/src/Cargo.lock
@ -2,9 +2,9 @@
 # It is not intended for manual editing.
 [[package]]
 name = "async-recursion"
-version = "0.3.2"
+version = "0.3.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d7d78656ba01f1b93024b7c3a0467f1608e4be67d725749fdcd7d2c7678fd7a2"
+checksum = "e5444eec77a9ec2bfe4524139e09195862e981400c4358d3b760cae634e4c4ee"
 dependencies = [
 "proc-macro2",
 "quote",
@ -13,15 +13,15 @@ dependencies = [

 [[package]]
 name = "autocfg"
-version = "1.0.1"
+version = "1.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "cdb031dd78e28731d87d56cc8ffef4a8f36ca26c38fe2de700543e627f8a464a"
+checksum = "f8aac770f1885fd7e387acedd76065302551364496e46b3dd00860b2f8359b9d"

 [[package]]
 name = "bit_field"
-version = "0.10.1"
+version = "0.10.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "dcb6dd1c2376d2e096796e234a70e17e94cc2d5d54ff8ce42b28cef1d0d359a4"
+checksum = "a165d606cf084741d4ac3a28fb6e9b1eb0bd31f6cd999098cfddb0b2ab381dc0"

 [[package]]
 name = "bitflags"
@ -29,27 +29,17 @@ version = "1.2.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "cf1de2fe8c75bc145a2f577add951f8134889b4795d47466a54a5c846d691693"

-[[package]]
-name = "build_const"
-version = "0.2.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b4ae4235e6dac0694637c763029ecea1a2ec9e4e06ec2729bd21ba4d9c863eb7"
-
-[[package]]
-name = "build_zynq"
-version = "0.0.0"
-
 [[package]]
 name = "byteorder"
-version = "1.4.3"
+version = "1.3.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "14c189c53d098945499cdfa7ecc63567cf3886b3332b312a5b4585d8d3a6a610"
+checksum = "08c48aae112d48ed9f069b33538ea9e3e90aa263cfa3d1c24309612b1f7472de"

 [[package]]
 name = "cc"
-version = "1.0.69"
+version = "1.0.58"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e70cc2f62c6ce1868963827bd677764c62d07c3d9a3e1fb1177ee1a9ab199eb2"
+checksum = "f9a06fb2e53271d7c279ec1efea6ab691c35a2ae67ec0d91d7acec0caf13b518"

 [[package]]
 name = "cfg-if"
@ -57,34 +47,16 @@ version = "0.1.10"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "4785bdd1c96b2a846b2bd7cc02e86b6b3dbf14e7e53446c4f54c92a361040822"

-[[package]]
-name = "cfg-if"
-version = "1.0.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
-
 [[package]]
 name = "compiler_builtins"
-version = "0.1.39"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3748f82c7d366a0b4950257d19db685d4958d2fa27c6d164a3f069fec42b748b"
+version = "0.1.36"
+source = "git+https://github.com/pca006132/compiler-builtins.git?branch=pr#b18c32c55484e593eb3d38bbf4ca5132be1202eb"

 [[package]]
 name = "core_io"
-version = "0.1.20210325"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "97f8932064288cc79feb4d343a399d353a6f6f001e586ece47fe518a9e8507df"
+version = "0.1.20200410"
 dependencies = [
- "rustc_version",
-]
-
-[[package]]
-name = "crc"
-version = "1.8.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d663548de7f5cca343f1e0a48d14dcfb0e9eb4e079ec58883b7251539fa10aeb"
-dependencies = [
- "build_const",
+ "memchr",
 ]

 [[package]]
@ -97,9 +69,8 @@ checksum = "0f8cb7306107e4b10e64994de6d3274bd08996a7c1322a27b86482392f96be0a"
 name = "dwarf"
 version = "0.0.0"
 dependencies = [
- "cfg-if 0.1.10",
+ "cfg-if",
 "compiler_builtins",
- "cslice",
 "libc",
 "unwind",
 ]
@ -114,9 +85,9 @@ dependencies = [

 [[package]]
 name = "embedded-hal"
-version = "0.2.6"
+version = "0.2.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e36cfb62ff156596c892272f3015ef952fe1525e85261fa3a7f327bd6b384ab9"
+checksum = "fa998ce59ec9765d15216393af37a58961ddcefb14c753b4816ba2191d865fcb"
 dependencies = [
 "nb 0.1.3",
 "void",
@ -124,9 +95,9 @@ dependencies = [

 [[package]]
 name = "fatfs"
-version = "0.3.5"
+version = "0.3.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e18f80a87439240dac45d927fd8f8081b6f1e34c03e97271189fa8a8c2e96c8f"
+checksum = "93079df23039e52059e1f03b4c29fb0c72da2c792aad91bb2236c9fb81d3592e"
 dependencies = [
 "bitflags",
 "byteorder",
@ -136,9 +107,9 @@ dependencies = [

 [[package]]
 name = "futures"
-version = "0.3.16"
+version = "0.3.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1adc00f486adfc9ce99f77d717836f0c5aa84965eb0b4f051f4e83f7cab53f8b"
+checksum = "1e05b85ec287aac0dc34db7d4a569323df697f9c55b99b15d6b4ef8cde49f613"
 dependencies = [
 "futures-channel",
 "futures-core",
@ -150,9 +121,9 @@ dependencies = [

 [[package]]
 name = "futures-channel"
-version = "0.3.16"
+version = "0.3.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "74ed2411805f6e4e3d9bc904c95d5d423b89b3b25dc0250aa74729de20629ff9"
+checksum = "f366ad74c28cca6ba456d95e6422883cfb4b252a83bed929c83abfdbbf2967d5"
 dependencies = [
 "futures-core",
 "futures-sink",
@ -160,23 +131,22 @@ dependencies = [

 [[package]]
 name = "futures-core"
-version = "0.3.16"
+version = "0.3.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "af51b1b4a7fdff033703db39de8802c673eb91855f2e0d47dcf3bf2c0ef01f99"
+checksum = "59f5fff90fd5d971f936ad674802482ba441b6f09ba5e15fd8b39145582ca399"

 [[package]]
 name = "futures-io"
-version = "0.3.16"
+version = "0.3.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0b0e06c393068f3a6ef246c75cdca793d6a46347e75286933e5e75fd2fd11582"
+checksum = "de27142b013a8e869c14957e6d2edeef89e97c289e69d042ee3a49acd8b51789"

 [[package]]
 name = "futures-macro"
-version = "0.3.16"
+version = "0.3.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c54913bae956fb8df7f4dc6fc90362aa72e69148e3f39041fbe8742d21e0ac57"
+checksum = "d0b5a30a4328ab5473878237c447333c093297bded83a4983d10f4deea240d39"
 dependencies = [
- "autocfg",
 "proc-macro-hack",
 "proc-macro2",
 "quote",
@ -185,82 +155,51 @@ dependencies = [

 [[package]]
 name = "futures-sink"
-version = "0.3.16"
+version = "0.3.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c0f30aaa67363d119812743aa5f33c201a7a66329f97d1a887022971feea4b53"
+checksum = "3f2032893cb734c7a05d85ce0cc8b8c4075278e93b24b66f9de99d6eb0fa8acc"

 [[package]]
 name = "futures-task"
-version = "0.3.16"
+version = "0.3.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "bbe54a98670017f3be909561f6ad13e810d9a51f3f061b902062ca3da80799f2"
+checksum = "bdb66b5f09e22019b1ab0830f7785bcea8e7a42148683f99214f73f8ec21a626"

 [[package]]
 name = "futures-util"
-version = "0.3.16"
+version = "0.3.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "67eb846bfd58e44a8481a00049e82c43e0ccb5d61f8dc071057cb19249dd4d78"
+checksum = "8764574ff08b701a084482c3c7031349104b07ac897393010494beaa18ce32c6"
 dependencies = [
- "autocfg",
 "futures-core",
 "futures-macro",
 "futures-sink",
 "futures-task",
- "pin-project-lite",
+ "pin-project",
 "pin-utils",
 "proc-macro-hack",
 "proc-macro-nested",
 ]

-[[package]]
-name = "io"
-version = "0.0.0"
-dependencies = [
- "byteorder",
- "core_io",
- "libsupport_zynq",
-]
-
 [[package]]
 name = "libasync"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#3e95df1f640aa761740feaf9eec797acb58dd942"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#4fef8a71929b989e1189736628ab9c186f23f3a5"
 dependencies = [
 "embedded-hal",
 "libcortex_a9",
- "nb 1.0.0",
+ "nb 0.1.3",
 "pin-utils",
 "smoltcp",
 ]

-[[package]]
-name = "libboard_artiq"
-version = "0.0.0"
-dependencies = [
- "build_zynq",
- "core_io",
- "crc",
- "embedded-hal",
- "io",
- "libasync",
- "libboard_zynq",
- "libconfig",
- "libcortex_a9",
- "libregister",
- "log",
- "log_buffer",
- "nb 1.0.0",
- "void",
-]
-
 [[package]]
 name = "libboard_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#3e95df1f640aa761740feaf9eec797acb58dd942"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#4fef8a71929b989e1189736628ab9c186f23f3a5"
 dependencies = [
 "bit_field",
 "embedded-hal",
- "libasync",
 "libcortex_a9",
 "libregister",
 "log",
@ -281,7 +220,6 @@ dependencies = [
 [[package]]
 name = "libconfig"
 version = "0.1.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#3e95df1f640aa761740feaf9eec797acb58dd942"
 dependencies = [
 "core_io",
 "fatfs",
@ -292,7 +230,7 @@ dependencies = [
 [[package]]
 name = "libcortex_a9"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#3e95df1f640aa761740feaf9eec797acb58dd942"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#4fef8a71929b989e1189736628ab9c186f23f3a5"
 dependencies = [
 "bit_field",
 "libregister",
@ -308,7 +246,7 @@ checksum = "c7d73b3f436185384286bd8098d17ec07c9a7d2388a6599f824d8502b529702a"
 [[package]]
 name = "libregister"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#3e95df1f640aa761740feaf9eec797acb58dd942"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#4fef8a71929b989e1189736628ab9c186f23f3a5"
 dependencies = [
 "bit_field",
 "vcell",
@ -318,9 +256,8 @@ dependencies = [
 [[package]]
 name = "libsupport_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#3e95df1f640aa761740feaf9eec797acb58dd942"
+source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#4fef8a71929b989e1189736628ab9c186f23f3a5"
 dependencies = [
- "cc",
 "compiler_builtins",
 "libboard_zynq",
 "libcortex_a9",
@ -331,17 +268,17 @@ dependencies = [

 [[package]]
 name = "linked_list_allocator"
-version = "0.8.11"
+version = "0.8.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "822add9edb1860698b79522510da17bef885171f75aa395cff099d770c609c24"
+checksum = "660b26e6156a7d00eefb19052fe1943cf5ab2f353a723a577fad6ba2f99d1f90"

 [[package]]
 name = "log"
-version = "0.4.14"
+version = "0.4.11"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "51b9bbe6c47d51fc3e1a9b945965946b4c44142ab8792c50835a980d362c2710"
+checksum = "4fabed175da42fed1fa0746b0ea71f412aa9d35e76e95e59b192c64b9dc2bf8b"
 dependencies = [
- "cfg-if 1.0.0",
+ "cfg-if",
 ]

 [[package]]
@ -356,6 +293,12 @@ version = "0.7.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "c75de51135344a4f8ed3cfe2720dc27736f7711989703a0b43aadf3753c55577"

+[[package]]
+name = "memchr"
+version = "2.3.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3728d817d99e5ac407411fa471ff9800a778d88a24685968b36824eaf4bee400"
+
 [[package]]
 name = "nb"
 version = "0.1.3"
@ -373,9 +316,9 @@ checksum = "546c37ac5d9e56f55e73b677106873d9d9f5190605e41a856503623648488cae"

 [[package]]
 name = "num-derive"
-version = "0.3.3"
+version = "0.3.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "876a53fff98e03a936a674b29568b0e605f06b29372c2489ff4de23f1949743d"
+checksum = "e0396233fb2d5b0ae3f05ff6aba9a09185f7f6e70f87fb01147d545f85364665"
 dependencies = [
 "proc-macro2",
 "quote",
@ -384,18 +327,32 @@ dependencies = [

 [[package]]
 name = "num-traits"
-version = "0.2.14"
+version = "0.2.12"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9a64b1ec5cda2586e284722486d802acf1f7dbdc623e2bfc57e65ca1cd099290"
+checksum = "ac267bcc07f48ee5f8935ab0d24f316fb722d7a1292e2913f0cc196b29ffd611"
 dependencies = [
 "autocfg",
 ]

 [[package]]
-name = "pin-project-lite"
-version = "0.2.7"
+name = "pin-project"
+version = "0.4.23"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8d31d11c69a6b52a174b42bdc0c30e5e11670f90788b2c471c31c1d17d449443"
+checksum = "ca4433fff2ae79342e497d9f8ee990d174071408f28f726d6d83af93e58e48aa"
+dependencies = [
+ "pin-project-internal",
+]
+
+[[package]]
+name = "pin-project-internal"
+version = "0.4.23"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2c0e815c3ee9a031fdf5af21c10aa17c573c9c6a566328d99e3936c34e36461f"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]

 [[package]]
 name = "pin-utils"
@ -405,30 +362,30 @@ checksum = "8b870d8c151b6f2fb93e84a13146138f05d02ed11c7e7c54f8826aaaf7c9f184"

 [[package]]
 name = "proc-macro-hack"
-version = "0.5.19"
+version = "0.5.18"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "dbf0c48bc1d91375ae5c3cd81e3722dff1abcf81a30960240640d223f59fe0e5"
+checksum = "99c605b9a0adc77b7211c6b1f722dcb613d68d66859a44f3d485a6da332b0598"

 [[package]]
 name = "proc-macro-nested"
-version = "0.1.7"
+version = "0.1.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "bc881b2c22681370c6a780e47af9840ef841837bc98118431d4e1868bd0c1086"
+checksum = "eba180dafb9038b050a4c280019bbedf9f2467b61e5d892dcad585bb57aadc5a"

 [[package]]
 name = "proc-macro2"
-version = "1.0.28"
+version = "1.0.19"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5c7ed8b8c7b886ea3ed7dde405212185f423ab44682667c8c6dd14aa1d9f6612"
+checksum = "04f5f085b5d71e2188cb8271e5da0161ad52c3f227a661a3c135fdf28e258b12"
 dependencies = [
 "unicode-xid",
 ]

 [[package]]
 name = "quote"
-version = "1.0.9"
+version = "1.0.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c3d0b9745dc2debf507c8422de05d7226cc1f0644216dfdfead988f9b1ab32a7"
+checksum = "aa563d17ecb180e500da1cfd2b028310ac758de548efdd203e18f283af693f37"
 dependencies = [
 "proc-macro2",
 ]
@ -444,7 +401,6 @@ name = "runtime"
 version = "0.1.0"
 dependencies = [
 "async-recursion",
- "build_zynq",
 "byteorder",
 "core_io",
 "cslice",
@ -452,9 +408,7 @@ dependencies = [
 "dyld",
 "embedded-hal",
 "futures",
- "io",
 "libasync",
- "libboard_artiq",
 "libboard_zynq",
 "libc",
 "libconfig",
@ -472,44 +426,11 @@ dependencies = [
 "void",
 ]

-[[package]]
-name = "rustc_version"
-version = "0.1.7"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c5f5376ea5e30ce23c03eb77cbe4962b988deead10910c372b226388b594c084"
-dependencies = [
- "semver",
-]
-
-[[package]]
-name = "satman"
-version = "0.0.0"
-dependencies = [
- "build_zynq",
- "embedded-hal",
- "libasync",
- "libboard_artiq",
- "libboard_zynq",
- "libc",
- "libconfig",
- "libcortex_a9",
- "libregister",
- "libsupport_zynq",
- "log",
- "unwind",
-]
-
-[[package]]
-name = "semver"
-version = "0.1.20"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d4f410fedcf71af0345d7607d246e7ad15faaadd49d240ee3b24e5dc21a820ac"
-
 [[package]]
 name = "smoltcp"
-version = "0.7.5"
+version = "0.6.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3e4a069bef843d170df47e7c0a8bf8d037f217d9f5b325865acc3e466ffe40d3"
+checksum = "0fe46639fd2ec79eadf8fe719f237a7a0bd4dac5d957f1ca5bbdbc1c3c39e53a"
 dependencies = [
 "bitflags",
 "byteorder",
@ -518,36 +439,50 @@ dependencies = [

 [[package]]
 name = "syn"
-version = "1.0.74"
+version = "1.0.38"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1873d832550d4588c3dbc20f01361ab00bfe741048f71e3fecf145a7cc18b29c"
+checksum = "e69abc24912995b3038597a7a593be5053eb0fb44f3cc5beec0deb421790c1f4"
 dependencies = [
 "proc-macro2",
 "quote",
 "unicode-xid",
 ]

+[[package]]
+name = "szl"
+version = "0.1.0"
+dependencies = [
+ "byteorder",
+ "core_io",
+ "libboard_zynq",
+ "libconfig",
+ "libcortex_a9",
+ "libregister",
+ "libsupport_zynq",
+ "log",
+]
+
 [[package]]
 name = "unicode-xid"
-version = "0.2.2"
+version = "0.2.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8ccb82d61f80a663efe1f787a51b16b5a51e3314d6ac365b08639f52387b33f3"
+checksum = "f7fe0bb3479651439c9112f72b6c505038574c9fbb575ed1bf3b797fa39dd564"

 [[package]]
 name = "unwind"
 version = "0.0.0"
 dependencies = [
 "cc",
- "cfg-if 0.1.10",
+ "cfg-if",
 "compiler_builtins",
 "libc",
 ]

 [[package]]
 name = "vcell"
-version = "0.1.3"
+version = "0.1.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "77439c1b53d2303b20d9459b1ade71a83c716e3f9c34f3228c00e6f185d6c002"
+checksum = "876e32dcadfe563a4289e994f7cb391197f362b6315dc45e8ba4aa6f564a4b3c"

 [[package]]
 name = "void"
--- a/src/Cargo.toml
+++ b/src/Cargo.toml
@ -2,16 +2,32 @@
 members = [
  "libc",
  "libdyld",
+  "libconfig",
+  "libcoreio",
  "libdwarf",
-  "libio",
  "libunwind",
  "runtime",
-  "satman"
+  "szl"
 ]

+# Note: we are using dev profile for szl to override the opt-level only
+[profile.dev]
+panic = "abort"
+debug = true
+codegen-units = 1
+opt-level = 'z'
+lto = true
+debug-assertions = false
+overflow-checks = false
+
 [profile.release]
 panic = "abort"
 debug = true
 codegen-units = 1
 opt-level = 2
 lto = true
+
+[patch.crates-io]
+core_io = { path = "./libcoreio" }
+compiler_builtins = { git = "https://github.com/pca006132/compiler-builtins.git", branch = "pr" }
+
--- a/src/Makefile
+++ b/src/Makefile
@ -1,34 +1,17 @@
-TARGET := zc706
-GWARGS := -V nist_clock
+VARIANT := simple

-all: runtime
+all: ../build/firmware/armv7-none-eabihf/debug/szl ../build/firmware/armv7-none-eabihf/release/runtime

-runtime: ../build/runtime.bin
+.PHONY: all

-satman: ../build/satman.bin

-.PHONY: all runtime_target satman_target
-
-../build/pl.rs ../build/rustc-cfg ../build/mem.rs: gateware/* 
+../build/pl.rs ../build/rustc-cfg: gateware/*
 	mkdir -p ../build
-	python gateware/$(TARGET).py -r ../build/pl.rs -c ../build/rustc-cfg -m ../build/mem.rs $(GWARGS)
+	python gateware/zc706.py -r ../build/pl.rs -c ../build/rustc-cfg -V $(VARIANT)

-../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(shell find . -type f -print)
-	cd runtime && \
-	XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \
-	cargo xbuild --release \
-		--target-dir ../../build/firmware \
-		--no-default-features --features=target_$(TARGET)
-
-../build/runtime.bin: ../build/firmware/armv7-none-eabihf/release/runtime
+../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg $(shell find . -path ./szl -prune -o -print)
+	XBUILD_SYSROOT_PATH=`pwd`/../build/sysroot cargo xbuild --release -p runtime --target-dir ../build/firmware
 	llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin

-../build/firmware/armv7-none-eabihf/release/satman: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(shell find . -type f -print)
-	cd satman && \
-	XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \
-	cargo xbuild --release \
-		--target-dir ../../build/firmware \
-		--no-default-features --features=target_$(TARGET)
-
-../build/satman.bin: ../build/firmware/armv7-none-eabihf/release/satman
-	llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/satman ../build/satman.bin
+../build/firmware/armv7-none-eabihf/debug/szl: .cargo/* armv7-none-eabihf.json Cargo.lock Cargo.toml szl/* szl/src/*
+	XBUILD_SYSROOT_PATH=`pwd`/../build/sysroot cargo xbuild -p szl --target-dir ../build/firmware
--- a/src/gateware/acpki.py
+++ b/src/gateware/acpki.py
@ -7,7 +7,8 @@ from misoc.interconnect.csr import *

 from artiq.gateware import rtio

-OUT_BURST_LEN = 10
+
+OUT_BURST_LEN = 4
 IN_BURST_LEN = 4


@ -97,7 +98,7 @@ class Engine(Module, AutoCSR):
        ### Write
        self.comb += [
            w.data.eq(self.din),
-            aw.addr.eq(self.addr_base.storage+96),
+            aw.addr.eq(self.addr_base.storage+32), # Write to next cache line
            w.strb.eq(0xff),
            aw.burst.eq(axi.Burst.incr.value),
            aw.len.eq(IN_BURST_LEN-1), # Number of transfers in burst minus 1
@ -190,31 +191,22 @@ class KernelInitiator(Module, AutoCSR):
            cmd_read.eq(cmd == 1)
        ]

-        out_len = Signal(8)
        dout_cases = {}
        dout_cases[0] = [
            cmd.eq(self.engine.dout[:8]),
-            out_len.eq(self.engine.dout[8:16]),
            cri.chan_sel.eq(self.engine.dout[40:]),
            cri.o_address.eq(self.engine.dout[32:40])
        ]
-        for i in range(8):
-            target = cri.o_data[i*64:(i+1)*64]
-            dout_cases[0] += [If(i >= self.engine.dout[8:16], target.eq(0))]
-
        dout_cases[1] = [
-            cri.o_timestamp.eq(self.engine.dout),
-            cri.i_timeout.eq(self.engine.dout)
+            cri.o_timestamp.eq(self.engine.dout)
        ]
-        for i in range(8):
-            target = cri.o_data[i*64:(i+1)*64]
-            dout_cases[i+2] = [target.eq(self.engine.dout)]
+        dout_cases[2] = [cri.o_data.eq(self.engine.dout)] # only lowest 64 bits

        self.sync += [
            cri.cmd.eq(rtio.cri.commands["nop"]),
            If(self.engine.dout_stb,
                Case(self.engine.dout_index, dout_cases),
-                If(self.engine.dout_index == out_len + 2,
+                If(self.engine.dout_index == 2,
                    If(cmd_write, cri.cmd.eq(rtio.cri.commands["write"])),
                    If(cmd_read, cri.cmd.eq(rtio.cri.commands["read"]))
                )
@ -234,11 +226,7 @@ class KernelInitiator(Module, AutoCSR):
        )
        fsm.act("WAIT_OUT_CYCLE",
            self.engine.din_ready.eq(0),
-            If(self.engine.dout_stb & cmd_write & (self.engine.dout_index == out_len + 2),
-               NextState("WAIT_READY")
-            ),
-            # for some reason read requires some delay until the next state
-            If(self.engine.dout_stb & cmd_read & (self.engine.dout_index == out_len + 3),
+            If(self.engine.dout_stb & (self.engine.dout_index == 3),
                NextState("WAIT_READY")
            )
        )
--- a/src/gateware/drtio_aux_controller.py
+++ b/src/gateware/drtio_aux_controller.py
@ -1,85 +0,0 @@
-"""Auxiliary controller, common to satellite and master"""
-
-from artiq.gateware.drtio.aux_controller import Transmitter, Receiver
-from migen.fhdl.simplify import FullMemoryWE
-from misoc.interconnect.csr import *
-from migen_axi.interconnect.sram import SRAM
-from migen_axi.interconnect import axi
-
-max_packet = 1024
-
-class _DRTIOAuxControllerBase(Module):
-    def __init__(self, link_layer):
-        self.bus = axi.Interface()
-        self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
-        self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data))
-
-    def get_csrs(self):
-        return self.transmitter.get_csrs() + self.receiver.get_csrs()
-
-
-# TODO: FullMemoryWE should be applied by migen.build
-@FullMemoryWE()
-class DRTIOAuxControllerAxi(_DRTIOAuxControllerBase):
-    def __init__(self, link_layer):
-        _DRTIOAuxControllerBase.__init__(self, link_layer)
-
-        tx_sdram_if = SRAM(self.transmitter.mem, read_only=False)
-        rx_sdram_if = SRAM(self.receiver.mem, read_only=True)
-        aw_decoder = axi.AddressDecoder(self.bus.aw,
-            [(lambda a: a[log2_int(max_packet)] == 0, tx_sdram_if.bus.aw),
-             (lambda a: a[log2_int(max_packet)] == 1, rx_sdram_if.bus.aw)],
-            register=True)
-        ar_decoder = axi.AddressDecoder(self.bus.ar,
-            [(lambda a: a[log2_int(max_packet)] == 0, tx_sdram_if.bus.ar),
-             (lambda a: a[log2_int(max_packet)] == 1, rx_sdram_if.bus.ar)],
-            register=True)
-        # unlike wb, axi address decoder only connects ar/aw lanes,
-        # the rest must also be connected!
-        # not quite unlike an address decoder itself.
-
-        # connect bus.b with tx.b
-        self.comb += [tx_sdram_if.bus.b.ready.eq(self.bus.b.ready),
-                      self.bus.b.id.eq(tx_sdram_if.bus.b.id),
-                      self.bus.b.resp.eq(tx_sdram_if.bus.b.resp),
-                      self.bus.b.valid.eq(tx_sdram_if.bus.b.valid)]
-        # connect bus.w with tx.w
-        # no worries about w.valid and slave sel here, only tx will be written to
-        self.comb += [tx_sdram_if.bus.w.id.eq(self.bus.w.id),
-                      tx_sdram_if.bus.w.data.eq(self.bus.w.data),
-                      tx_sdram_if.bus.w.strb.eq(self.bus.w.strb),
-                      tx_sdram_if.bus.w.last.eq(self.bus.w.last),
-                      tx_sdram_if.bus.w.valid.eq(self.bus.w.valid),
-                      self.bus.w.ready.eq(tx_sdram_if.bus.w.ready)]
-        # connect bus.r with rx.r and tx.r w/o data
-        self.comb += [self.bus.r.id.eq(rx_sdram_if.bus.r.id | tx_sdram_if.bus.r.id),
-                #self.bus.r.data.eq(rx_sdram_if.bus.r.data | tx_sdram_if.bus.r.data),
-                self.bus.r.resp.eq(rx_sdram_if.bus.r.resp | tx_sdram_if.bus.r.resp),
-                self.bus.r.last.eq(rx_sdram_if.bus.r.last | tx_sdram_if.bus.r.last),
-                self.bus.r.valid.eq(rx_sdram_if.bus.r.valid | tx_sdram_if.bus.r.valid),
-                rx_sdram_if.bus.r.ready.eq(self.bus.r.ready),
-                tx_sdram_if.bus.r.ready.eq(self.bus.r.ready)]
-        # connect read data after being masked
-        masked = [Replicate(rx_sdram_if.bus.r.valid,
-                            len(self.bus.r.data)
-                            ) & rx_sdram_if.bus.r.data,
-                 Replicate(tx_sdram_if.bus.r.valid,
-                            len(self.bus.r.data)
-                            ) & tx_sdram_if.bus.r.data]
-        self.comb += self.bus.r.data.eq(reduce(or_, masked))
-
-        self.submodules += tx_sdram_if, rx_sdram_if, aw_decoder, ar_decoder
-
-
-@FullMemoryWE()
-class DRTIOAuxControllerBare(_DRTIOAuxControllerBase):
-    # Barebones version of the AuxController. No SRAM, no decoders.
-    # add memories manually from tx and rx in target code.
-    def get_tx_port(self):
-        return self.transmitter.mem.get_port(write_capable=True)
-
-    def get_rx_port(self):
-        return self.receiver.mem.get_port(write_capable=False)
-
-    def get_mem_size(self):
-        return max_packet
--- a/src/gateware/kasli_soc.py
+++ b/src/gateware/kasli_soc.py
@ -1,526 +0,0 @@
-#!/usr/bin/env python
-
-import argparse
-from operator import itemgetter
-
-from migen import *
-from migen.build.generic_platform import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.genlib.cdc import MultiReg
-from migen_axi.integration.soc_core import SoCCore
-from migen_axi.platforms import kasli_soc
-from misoc.interconnect.csr import *
-from misoc.integration import cpu_interface
-
-from artiq.coredevice import jsondesc
-from artiq.gateware import rtio, eem_7series
-from artiq.gateware.rtio.phy import ttl_simple
-from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier
-from artiq.gateware.drtio.transceiver import gtx_7series
-from artiq.gateware.drtio.siphaser import SiPhaser7Series
-from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
-from artiq.gateware.drtio import *
-
-import dma
-import analyzer
-import acpki
-import drtio_aux_controller
-
-class RTIOCRG(Module, AutoCSR):
-    def __init__(self, platform):
-        self.pll_reset = CSRStorage(reset=1)
-        self.pll_locked = CSRStatus()
-        self.clock_domains.cd_rtio = ClockDomain()
-        self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
-
-        clk_synth = platform.request("cdr_clk_clean_fabric")
-        clk_synth_se = Signal()
-        platform.add_period_constraint(clk_synth.p, 8.0)
-        self.specials += [
-            Instance("IBUFGDS",
-                p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
-                i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
-        ]
-
-        pll_locked = Signal()
-        rtio_clk = Signal()
-        rtiox4_clk = Signal()
-        fb_clk = Signal()
-        self.specials += [
-            Instance("PLLE2_ADV",
-                     p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
-                     p_BANDWIDTH="HIGH",
-                     p_REF_JITTER1=0.001,
-                     p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
-                     i_CLKIN2=clk_synth_se,
-                     # Warning: CLKINSEL=0 means CLKIN2 is selected
-                     i_CLKINSEL=0,
-
-                     # VCO @ 1.5GHz when using 125MHz input
-                     p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
-                     i_CLKFBIN=fb_clk,
-                     i_RST=self.pll_reset.storage,
-
-                     o_CLKFBOUT=fb_clk,
-
-                     p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0,
-                     o_CLKOUT0=rtiox4_clk,
-
-                     p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0,
-                     o_CLKOUT1=rtio_clk),
-            Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
-            Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
-
-            AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
-            MultiReg(pll_locked, self.pll_locked.status)
-        ]
-
-        
-eem_iostandard_dict = {
-     0: "LVDS_25",
-     1: "LVDS_25",
-     2: "LVDS",
-     3: "LVDS",
-     4: "LVDS",
-     5: "LVDS",
-     6: "LVDS",
-     7: "LVDS",
-     8: "LVDS_25",
-     9: "LVDS_25",
-    10: "LVDS",
-    11: "LVDS",
-}
-
-
-def eem_iostandard(eem):
-    return IOStandard(eem_iostandard_dict[eem])
-
-
-class GenericStandalone(SoCCore):
-    def __init__(self, description, acpki=False):
-        self.acpki = acpki
-        self.rustc_cfg = dict()
-
-        platform = kasli_soc.Platform()
-        platform.toolchain.bitstream_commands.extend([
-            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
-        ])
-        ident = self.__class__.__name__
-        if self.acpki:
-            ident = "acpki_" + ident
-        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
-
-        platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
-        platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
-
-        self.rustc_cfg["has_si5324"] = None
-        self.rustc_cfg["si5324_soft_reset"] = None
-
-        self.crg = self.ps7 # HACK for eem_7series to find the clock
-        self.submodules.rtio_crg = RTIOCRG(self.platform)
-        self.csr_devices.append("rtio_crg")
-        self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
-        self.platform.add_false_path_constraints(
-            self.ps7.cd_sys.clk,
-            self.rtio_crg.cd_rtio.clk)
-
-        self.rtio_channels = []
-        has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
-        if has_grabber:
-            self.grabber_csr_group = []
-        eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
-        for i in (0, 1):
-            print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
-            user_led = self.platform.request("user_led", i)
-            phy = ttl_simple.Output(user_led)
-            self.submodules += phy
-            self.rtio_channels.append(rtio.Channel.from_phy(phy))
-        self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
-        self.rtio_channels.append(rtio.LogChannel())
-
-        self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
-        self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
-        self.csr_devices.append("rtio_core")
-
-        if self.acpki:
-            self.rustc_cfg["ki_impl"] = "acp"
-            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
-                                                         bus=self.ps7.s_axi_acp,
-                                                         user=self.ps7.s_axi_acp_user,
-                                                         evento=self.ps7.event.o)
-            self.csr_devices.append("rtio")
-        else:
-            self.rustc_cfg["ki_impl"] = "csr"
-            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
-            self.csr_devices.append("rtio")
-
-        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
-        self.csr_devices.append("rtio_dma")
-
-        self.submodules.cri_con = rtio.CRIInterconnectShared(
-            [self.rtio.cri, self.rtio_dma.cri],
-            [self.rtio_core.cri])
-        self.csr_devices.append("cri_con")
-
-        self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
-        self.csr_devices.append("rtio_moninj")
-
-        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
-                                                          self.ps7.s_axi_hp1)
-        self.csr_devices.append("rtio_analyzer")
-
-        if has_grabber:
-            self.rustc_cfg["has_grabber"] = None
-            self.add_csr_group("grabber", self.grabber_csr_group)
-            for grabber in self.grabber_csr_group:
-                self.platform.add_false_path_constraints(
-                    self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk)
-
-
-class GenericMaster(SoCCore):
-    def __init__(self, description, acpki=False):
-        sys_clk_freq = 125e6
-        rtio_clk_freq = description["rtio_frequency"]
-
-        self.acpki = acpki
-        self.rustc_cfg = dict()
-
-        platform = kasli_soc.Platform()
-        platform.toolchain.bitstream_commands.extend([
-            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
-        ])
-        ident = self.__class__.__name__
-        if self.acpki:
-            ident = "acpki_" + ident
-        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
-
-        platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
-        platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
-
-        data_pads = [platform.request("sfp", i) for i in range(4)]
-
-        self.submodules.drtio_transceiver = gtx_7series.GTX(
-            clock_pads=platform.request("clk125_gtp"),
-            pads=data_pads,
-            sys_clk_freq=sys_clk_freq)
-        self.csr_devices.append("drtio_transceiver")
-
-        self.crg = self.ps7 # HACK for eem_7series to find the clock
-        self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
-        self.csr_devices.append("rtio_crg")
-
-        self.rtio_channels = []
-        has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
-        if has_grabber:
-            self.grabber_csr_group = []
-        eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
-        for i in (0, 1):
-            print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
-            user_led = self.platform.request("user_led", i)
-            phy = ttl_simple.Output(user_led)
-            self.submodules += phy
-            self.rtio_channels.append(rtio.Channel.from_phy(phy))
-        self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
-        self.rtio_channels.append(rtio.LogChannel())
-
-        self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
-
-        drtio_csr_group = []
-        drtioaux_csr_group = []
-        drtioaux_memory_group = []
-        self.drtio_cri = []
-        for i in range(len(self.drtio_transceiver.channels)):
-            core_name = "drtio" + str(i)
-            coreaux_name = "drtioaux" + str(i)
-            memory_name = "drtioaux" + str(i) + "_mem"
-            drtio_csr_group.append(core_name)
-            drtioaux_csr_group.append(coreaux_name)
-            drtioaux_memory_group.append(memory_name)
-
-            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
-
-            core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
-            setattr(self.submodules, core_name, core)
-            self.drtio_cri.append(core.cri)
-            self.csr_devices.append(core_name)
-
-            coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
-            setattr(self.submodules, coreaux_name, coreaux)
-            self.csr_devices.append(coreaux_name)
-
-            size = coreaux.get_mem_size()
-            memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
-            self.axi2csr.register_port(coreaux.get_rx_port(), size)
-            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
-        self.rustc_cfg["has_drtio"] = None
-        self.rustc_cfg["has_drtio_routing"] = None
-        self.add_csr_group("drtio", drtio_csr_group)
-        self.add_csr_group("drtioaux", drtioaux_csr_group)
-        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
-
-        self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
-        self.csr_devices.append("rtio_core")
-
-        if self.acpki:
-            self.rustc_cfg["ki_impl"] = "acp"
-            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
-                                                         bus=self.ps7.s_axi_acp,
-                                                         user=self.ps7.s_axi_acp_user,
-                                                         evento=self.ps7.event.o)
-            self.csr_devices.append("rtio")
-        else:
-            self.rustc_cfg["ki_impl"] = "csr"
-            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
-            self.csr_devices.append("rtio")
-
-        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
-        self.csr_devices.append("rtio_dma")
-
-        self.submodules.cri_con = rtio.CRIInterconnectShared(
-            [self.rtio.cri, self.rtio_dma.cri],
-            [self.rtio_core.cri] + self.drtio_cri,
-            enable_routing=True)
-        self.csr_devices.append("cri_con")
-
-        self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
-        self.csr_devices.append("rtio_moninj")
-
-        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
-        self.csr_devices.append("routing_table")
-
-        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
-                                                          self.ps7.s_axi_hp1)
-        self.csr_devices.append("rtio_analyzer")
-
-        if has_grabber:
-            self.rustc_cfg["has_grabber"] = None
-            self.add_csr_group("grabber", self.grabber_csr_group)
-
-
-class GenericSatellite(SoCCore):
-    def __init__(self, description, acpki=False):
-        sys_clk_freq = 125e6  
-        rtio_clk_freq = description["rtio_frequency"]
-
-        self.acpki = acpki
-        self.rustc_cfg = dict()
-
-        platform = kasli_soc.Platform()
-        platform.toolchain.bitstream_commands.extend([
-            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
-        ])
-        ident = self.__class__.__name__
-        if self.acpki:
-            ident = "acpki_" + ident
-        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
-
-        platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
-        platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
-
-        self.crg = self.ps7 # HACK for eem_7series to find the clock
-        self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
-        self.csr_devices.append("rtio_crg")
-        
-        data_pads = [platform.request("sfp", i) for i in range(4)]
-        
-        self.submodules.drtio_transceiver = gtx_7series.GTX(
-            clock_pads=platform.request("clk125_gtp"),  
-            pads=data_pads,
-            sys_clk_freq=sys_clk_freq)
-        self.csr_devices.append("drtio_transceiver")
-
-        self.rtio_channels = []
-        has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
-        if has_grabber:
-            self.grabber_csr_group = []
-        eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
-        for i in (0, 1):
-            print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
-            user_led = self.platform.request("user_led", i)
-            phy = ttl_simple.Output(user_led)
-            self.submodules += phy
-            self.rtio_channels.append(rtio.Channel.from_phy(phy))
-        self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
-        self.rtio_channels.append(rtio.LogChannel())
-
-        self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
-
-        drtioaux_csr_group = []
-        drtioaux_memory_group = []
-        drtiorep_csr_group = []
-        self.drtio_cri = []
-        for i in range(len(self.drtio_transceiver.channels)):
-            coreaux_name = "drtioaux" + str(i)
-            memory_name = "drtioaux" + str(i) + "_mem"
-            drtioaux_csr_group.append(coreaux_name)
-            drtioaux_memory_group.append(memory_name)
-
-            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
-
-            if i == 0:
-                self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
-                core = cdr(DRTIOSatellite(
-                    self.rtio_tsc, self.drtio_transceiver.channels[i],
-                    self.rx_synchronizer))
-                self.submodules.drtiosat = core
-                self.csr_devices.append("drtiosat")
-            else:
-                corerep_name = "drtiorep" + str(i-1)
-                drtiorep_csr_group.append(corerep_name)
-
-                core = cdr(DRTIORepeater(
-                    self.rtio_tsc, self.drtio_transceiver.channels[i]))
-                setattr(self.submodules, corerep_name, core)
-                self.drtio_cri.append(core.cri)
-                self.csr_devices.append(corerep_name)
-
-            coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
-            setattr(self.submodules, coreaux_name, coreaux)
-            self.csr_devices.append(coreaux_name)
-
-            mem_size = coreaux.get_mem_size()
-            tx_port = coreaux.get_tx_port()
-            rx_port = coreaux.get_rx_port()
-            memory_address = self.axi2csr.register_port(tx_port, mem_size)
-            # rcv in upper half of the memory, thus added second
-            self.axi2csr.register_port(rx_port, mem_size)
-            # and registered in PS interface
-            # manually, because software refers to rx/tx by halves of entire memory block, not names
-            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
-        self.rustc_cfg["has_drtio"] = None
-        self.rustc_cfg["has_drtio_routing"] = None
-        self.add_csr_group("drtioaux", drtioaux_csr_group)
-        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
-        self.add_csr_group("drtiorep", drtiorep_csr_group)
-
-        self.rustc_cfg["has_si5324"] = None
-        self.rustc_cfg["si5324_soft_reset"] = None
-
-        if self.acpki:
-            self.rustc_cfg["ki_impl"] = "acp"
-            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
-                                                         bus=self.ps7.s_axi_acp,
-                                                         user=self.ps7.s_axi_acp_user,
-                                                         evento=self.ps7.event.o)
-            self.csr_devices.append("rtio")
-        else:
-            self.rustc_cfg["ki_impl"] = "csr"
-            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
-            self.csr_devices.append("rtio")
-
-        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
-        self.csr_devices.append("rtio_dma")
-
-        self.submodules.local_io = SyncRTIO(self.rtio_tsc, self.rtio_channels)
-        self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
-
-        self.submodules.cri_con = rtio.CRIInterconnectShared(
-            [self.drtiosat.cri],
-            [self.local_io.cri] + self.drtio_cri,
-            mode="sync", enable_routing=True)
-        self.csr_devices.append("cri_con")
-
-        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
-        self.csr_devices.append("routing_table")     
-
-        self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
-        self.csr_devices.append("rtio_moninj")
-
-        rtio_clk_period = 1e9/rtio_clk_freq
-        self.rustc_cfg["rtio_frequency"] = str(rtio_clk_freq/1e6)
-
-        self.submodules.siphaser = SiPhaser7Series(
-            si5324_clkin=platform.request("cdr_clk"),
-            rx_synchronizer=self.rx_synchronizer,
-            ultrascale=False,
-            rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
-        platform.add_false_path_constraints(
-            self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
-        self.csr_devices.append("siphaser")
-        self.rustc_cfg["has_si5324"] = None
-        self.rustc_cfg["has_siphaser"] = None
-        self.rustc_cfg["si5324_soft_reset"] = None
-
-        gtx0 = self.drtio_transceiver.gtxs[0]
-        platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
-        platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
-        platform.add_false_path_constraints(
-            self.crg.cd_sys.clk,
-            gtx0.txoutclk, gtx0.rxoutclk)
-        for gtx in self.drtio_transceiver.gtxs[1:]:
-            platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
-            platform.add_false_path_constraints(
-                self.crg.cd_sys.clk, gtx.rxoutclk)
-
-        if has_grabber:
-            self.rustc_cfg["has_grabber"] = None
-            self.add_csr_group("grabber", self.grabber_csr_group)
-            # no RTIO CRG here
-     
-
-def write_mem_file(soc, filename):
-    with open(filename, "w") as f:
-        f.write(cpu_interface.get_mem_rust(
-            soc.get_memory_regions(), soc.get_memory_groups(), None))
-
-
-def write_csr_file(soc, filename):
-    with open(filename, "w") as f:
-        f.write(cpu_interface.get_csr_rust(
-            soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
-
-
-def write_rustc_cfg_file(soc, filename):
-    with open(filename, "w") as f:
-        for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
-            if v is None:
-                f.write("{}\n".format(k))
-            else:
-                f.write("{}=\"{}\"\n".format(k, v))
-
-
-def main():
-    parser = argparse.ArgumentParser(
-        description="ARTIQ device binary builder for generic Kasli-SoC systems")
-    parser.add_argument("-r", default=None,
-        help="build Rust interface into the specified file")
-    parser.add_argument("-c", default=None,
-        help="build Rust compiler configuration into the specified file")
-    parser.add_argument("-m", default=None,
-        help="build Rust memory interface into the specified file")
-    parser.add_argument("-g", default=None,
-        help="build gateware into the specified directory")
-    parser.add_argument("--acpki", default=False, action="store_true",
-        help="enable ACPKI")
-    parser.add_argument("description", metavar="DESCRIPTION",
-                        help="JSON system description file")
-    args = parser.parse_args()
-    description = jsondesc.load(args.description)
-
-    if description["target"] != "kasli_soc":
-        raise ValueError("Description is for a different target")
-
-    if description["base"] == "standalone":
-        cls = GenericStandalone
-    elif description["base"] == "master":
-        cls = GenericMaster
-    elif description["base"] == "satellite":
-        cls = GenericSatellite
-    else:
-        raise ValueError("Invalid base")
-
-    soc = cls(description, acpki=args.acpki)
-    soc.finalize()
-
-    if args.r is not None:
-        write_csr_file(soc, args.r)
-    if args.m is not None:
-        write_mem_file(soc, args.m)
-    if args.c is not None:
-        write_rustc_cfg_file(soc, args.c)
-    if args.g is not None:
-        soc.build(build_dir=args.g)
-
-
-if __name__ == "__main__":
-    main()
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@ -11,20 +11,13 @@ from migen_axi.integration.soc_core import SoCCore
 from migen_axi.platforms import zc706
 from misoc.interconnect.csr import *
 from misoc.integration import cpu_interface
-from misoc.cores import gpio

 from artiq.gateware import rtio, nist_clock, nist_qc2
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
-from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier, fix_serdes_timing_path
-from artiq.gateware.drtio.transceiver import gtx_7series
-from artiq.gateware.drtio.siphaser import SiPhaser7Series
-from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
-from artiq.gateware.drtio import *

 import dma
 import analyzer
 import acpki
-import drtio_aux_controller


 class RTIOCRG(Module, AutoCSR):
@ -71,77 +64,25 @@ class RTIOCRG(Module, AutoCSR):
        ]


-# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
-# This also changes the I/O standard for some on-board LEDs.
-leds_fmc33 = [
-    ("user_led_33", 0, Pins("Y21"), IOStandard("LVCMOS33")),
-    ("user_led_33", 1, Pins("G2"), IOStandard("LVCMOS15")),
-    ("user_led_33", 2, Pins("W21"), IOStandard("LVCMOS33")),
-    ("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")),
-]
-
-# same deal as with LEDs - changed I/O standard.
-si5324_fmc33 = [
-    ("si5324_33", 0,
-        Subsignal("rst_n", Pins("W23"), IOStandard("LVCMOS33")),
-        Subsignal("int", Pins("AJ25"), IOStandard("LVCMOS33"))
-    ),
-]
-
-pmod1_33 = [
-    ("pmod1_33", 0, Pins("AJ21"), IOStandard("LVCMOS33")),
-    ("pmod1_33", 1, Pins("AK21"), IOStandard("LVCMOS33")),
-    ("pmod1_33", 2, Pins("AB21"), IOStandard("LVCMOS33")),
-    ("pmod1_33", 3, Pins("AB16"), IOStandard("LVCMOS33")),
-    # rest removed for use with dummy spi
-]
-
-_ams101_dac = [
-    ("ams101_dac", 0,
-        Subsignal("ldac", Pins("XADC:GPIO0")),
-        Subsignal("clk", Pins("XADC:GPIO1")),
-        Subsignal("mosi", Pins("XADC:GPIO2")),
-        Subsignal("cs_n", Pins("XADC:GPIO3")),
-        IOStandard("LVCMOS15")
-     )
-]
-
-_pmod_spi = [ 
-    ("pmod_spi", 0,
-        # PMOD_1 4-7 pins, same bank as sfp_tx_disable or user_sma_clock
-        Subsignal("miso", Pins("Y20"), IOStandard("LVCMOS25")),
-        Subsignal("clk", Pins("AA20"), IOStandard("LVCMOS25")),
-        Subsignal("mosi", Pins("AC18"), IOStandard("LVCMOS25")),
-        Subsignal("cs_n", Pins("AC19"), IOStandard("LVCMOS25")),
-        IOStandard("LVCMOS25")
-    )
-]
-
-
-def prepare_zc706_platform(platform):
-    platform.toolchain.bitstream_commands.extend([
-        "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
-    ])
-    platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
-    platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
-
-
 class ZC706(SoCCore):
    def __init__(self, acpki=False):
        self.acpki = acpki
        self.rustc_cfg = dict()

        platform = zc706.Platform()
-        prepare_zc706_platform(platform)
-
+        platform.toolchain.bitstream_commands.extend([
+            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+        ])
        ident = self.__class__.__name__
        if self.acpki:
            ident = "acpki_" + ident
        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)

+        platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
+        platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
+
        self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
        self.csr_devices.append("rtio_crg")
-        self.rustc_cfg["has_rtio_crg_clock_sel"] = None
        self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
        self.platform.add_false_path_constraints(
            self.ps7.cd_sys.clk,
@ -180,301 +121,52 @@ class ZC706(SoCCore):
        self.csr_devices.append("rtio_analyzer")


-class _MasterBase(SoCCore):
-    def __init__(self, acpki=False, drtio100mhz=False):
-        self.acpki = acpki
-        self.rustc_cfg = dict()
-
-        platform = zc706.Platform()
-        prepare_zc706_platform(platform)
-        ident = self.__class__.__name__
-        if self.acpki:
-            ident = "acpki_" + ident
-        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
-
-        platform.add_extension(si5324_fmc33)
-
-        self.sys_clk_freq = 125e6
-        rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq
+class Simple(ZC706):
+    def __init__(self, **kwargs):
+        ZC706.__init__(self, **kwargs)

        platform = self.platform

-        self.comb += platform.request("sfp_tx_disable_n").eq(1)
-        data_pads = [
-            platform.request("sfp"),
-            platform.request("user_sma_mgt")
-        ]
+        rtio_channels = []
+        for i in range(4):
+            phy = ttl_simple.Output(platform.request("user_led", i))
+            self.submodules += phy
+            rtio_channels.append(rtio.Channel.from_phy(phy))

-        # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
-        self.submodules.drtio_transceiver = gtx_7series.GTX(
-            clock_pads=platform.request("si5324_clkout"),
-            pads=data_pads,
-            sys_clk_freq=self.sys_clk_freq,
-            rtio_clk_freq=rtio_clk_freq)
-        self.csr_devices.append("drtio_transceiver")
+        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
+        rtio_channels.append(rtio.LogChannel())

-        self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
-
-        drtio_csr_group = []
-        drtioaux_csr_group = []
-        drtioaux_memory_group = []
-        self.drtio_cri = []
-        for i in range(len(self.drtio_transceiver.channels)):
-            core_name = "drtio" + str(i)
-            coreaux_name = "drtioaux" + str(i)
-            memory_name = "drtioaux" + str(i) + "_mem"
-            drtio_csr_group.append(core_name)
-            drtioaux_csr_group.append(coreaux_name)
-            drtioaux_memory_group.append(memory_name)
-
-            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
-
-            core = cdr(DRTIOMaster(
-                self.rtio_tsc, self.drtio_transceiver.channels[i]))
-            setattr(self.submodules, core_name, core)
-            self.drtio_cri.append(core.cri)
-            self.csr_devices.append(core_name)
-
-            coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
-            setattr(self.submodules, coreaux_name, coreaux)
-            self.csr_devices.append(coreaux_name)
-
-            mem_size = coreaux.get_mem_size()
-            memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), mem_size)
-            self.axi2csr.register_port(coreaux.get_rx_port(), mem_size)
-            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
-        self.rustc_cfg["has_drtio"] = None
-        self.rustc_cfg["has_drtio_routing"] = None
-        self.add_csr_group("drtio", drtio_csr_group)
-        self.add_csr_group("drtioaux", drtioaux_csr_group)
-        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
-
-        self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
-
-        self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
-        self.csr_devices.append("si5324_rst_n")
-        self.rustc_cfg["has_si5324"] = None
-        self.rustc_cfg["si5324_as_synthesizer"] = None
-
-        rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
-        # Constrain TX & RX timing for the first transceiver channel
-        # (First channel acts as master for phase alignment for all channels' TX)
-        gtx0 = self.drtio_transceiver.gtxs[0]
-        platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
-        platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
-        platform.add_false_path_constraints(
-            self.ps7.cd_sys.clk,
-            gtx0.txoutclk, gtx0.rxoutclk)
-        # Constrain RX timing for the each transceiver channel
-        # (Each channel performs single-lane phase alignment for RX)
-        for gtx in self.drtio_transceiver.gtxs[1:]:
-            platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
-            platform.add_false_path_constraints(
-                self.ps7.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk)
-
-        self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq)
-        self.csr_devices.append("rtio_crg")
-        fix_serdes_timing_path(self.platform)
-
-    def add_rtio(self, rtio_channels):
-        self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
-        self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
-        self.csr_devices.append("rtio_core")
-
-        if self.acpki:
-            self.rustc_cfg["ki_impl"] = "acp"
-            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
-                                                         bus=self.ps7.s_axi_acp,
-                                                         user=self.ps7.s_axi_acp_user,
-                                                         evento=self.ps7.event.o)
-            self.csr_devices.append("rtio")
-        else:
-            self.rustc_cfg["ki_impl"] = "csr"
-            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
-            self.csr_devices.append("rtio")
-
-        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
-        self.csr_devices.append("rtio_dma")
-
-        self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
-        self.submodules.cri_con = rtio.CRIInterconnectShared(
-            [self.rtio.cri, self.rtio_dma.cri],
-            [self.local_io.cri] + self.drtio_cri,
-            mode="sync", enable_routing=True)
-        self.csr_devices.append("cri_con")
-
-        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
-        self.csr_devices.append("rtio_moninj")
-
-        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
-                                                          self.ps7.s_axi_hp1)
-        self.csr_devices.append("rtio_analyzer")
-
-        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
-        self.csr_devices.append("routing_table")
+        self.add_rtio(rtio_channels)


-class _SatelliteBase(SoCCore):
-    def __init__(self, acpki=False, drtio100mhz=False):
-        self.acpki = acpki
-        self.rustc_cfg = dict()
-
-        platform = zc706.Platform()
-        prepare_zc706_platform(platform)
-        ident = self.__class__.__name__
-        if self.acpki:
-            ident = "acpki_" + ident
-        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
-
-        platform.add_extension(si5324_fmc33)
-
-        self.sys_clk_freq = 125e6
-        rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq
-        platform = self.platform
-
-        # SFP
-        self.comb += platform.request("sfp_tx_disable_n").eq(0)
-        data_pads = [
-            platform.request("sfp"),
-            platform.request("user_sma_mgt")
-        ]
-
-        self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
-
-        # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
-        self.submodules.drtio_transceiver = gtx_7series.GTX(
-            clock_pads=platform.request("si5324_clkout"),
-            pads=data_pads,
-            sys_clk_freq=self.sys_clk_freq,
-            rtio_clk_freq=rtio_clk_freq)
-        self.csr_devices.append("drtio_transceiver")
-
-        drtioaux_csr_group = []
-        drtioaux_memory_group = []
-        drtiorep_csr_group = []
-        self.drtio_cri = []
-        for i in range(len(self.drtio_transceiver.channels)):
-            coreaux_name = "drtioaux" + str(i)
-            memory_name = "drtioaux" + str(i) + "_mem"
-            drtioaux_csr_group.append(coreaux_name)
-            drtioaux_memory_group.append(memory_name)
-
-            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
-
-            # Satellite
-            if i == 0:
-                self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
-                core = cdr(DRTIOSatellite(
-                    self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer))
-                self.submodules.drtiosat = core
-                self.csr_devices.append("drtiosat")
-            # Repeaters
-            else:
-                corerep_name = "drtiorep" + str(i-1)
-                drtiorep_csr_group.append(corerep_name)
-                core = cdr(DRTIORepeater(
-                    self.rtio_tsc, self.drtio_transceiver.channels[i]))
-                setattr(self.submodules, corerep_name, core)
-                self.drtio_cri.append(core.cri)
-                self.csr_devices.append(corerep_name)
-
-            coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
-            setattr(self.submodules, coreaux_name, coreaux)
-            self.csr_devices.append(coreaux_name)
-
-            mem_size = coreaux.get_mem_size()
-            tx_port = coreaux.get_tx_port()
-            rx_port = coreaux.get_rx_port()
-            memory_address = self.axi2csr.register_port(tx_port, mem_size)
-            # rcv in upper half of the memory, thus added second
-            self.axi2csr.register_port(rx_port, mem_size)
-            # and registered in PS interface
-            # manually, because software refers to rx/tx by halves of entire memory block, not names
-            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
-        self.rustc_cfg["has_drtio"] = None
-        self.rustc_cfg["has_drtio_routing"] = None
-        self.add_csr_group("drtioaux", drtioaux_csr_group)
-        self.add_csr_group("drtiorep", drtiorep_csr_group)
-        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
-
-        self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
-
-        # Si5324 Phaser
-        self.submodules.siphaser = SiPhaser7Series(
-            si5324_clkin=platform.request("si5324_clkin"),
-            rx_synchronizer=self.rx_synchronizer,
-            ultrascale=False,
-            rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
-        platform.add_false_path_constraints(
-            self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output)
-        self.csr_devices.append("siphaser")
-        self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
-        self.csr_devices.append("si5324_rst_n")
-        self.rustc_cfg["has_si5324"] = None
-        self.rustc_cfg["has_siphaser"] = None
-
-        rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
-        # Constrain TX & RX timing for the first transceiver channel
-        # (First channel acts as master for phase alignment for all channels' TX)
-        gtx0 = self.drtio_transceiver.gtxs[0]
-        platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
-        platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
-        platform.add_false_path_constraints(
-            self.ps7.cd_sys.clk,
-            gtx0.txoutclk, gtx0.rxoutclk)
-        # Constrain RX timing for the each transceiver channel
-        # (Each channel performs single-lane phase alignment for RX)
-        for gtx in self.drtio_transceiver.gtxs[1:]:
-            platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
-            platform.add_false_path_constraints(
-                self.ps7.cd_sys.clk, gtx.rxoutclk)
-
-        self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq)
-        self.csr_devices.append("rtio_crg")
-        fix_serdes_timing_path(self.platform)
-
-    def add_rtio(self, rtio_channels):
-        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
-        self.csr_devices.append("rtio_moninj")
-
-        if self.acpki:
-            self.rustc_cfg["ki_impl"] = "acp"
-            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
-                                                         bus=self.ps7.s_axi_acp,
-                                                         user=self.ps7.s_axi_acp_user,
-                                                         evento=self.ps7.event.o)
-            self.csr_devices.append("rtio")
-        else:
-            self.rustc_cfg["ki_impl"] = "csr"
-            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
-            self.csr_devices.append("rtio")
-
-        self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
-        self.submodules.cri_con = rtio.CRIInterconnectShared(
-            [self.drtiosat.cri],
-            [self.local_io.cri] + self.drtio_cri,
-            mode="sync", enable_routing=True)
-        self.csr_devices.append("cri_con")
-
-        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
-        self.csr_devices.append("routing_table")
+# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
+# This also changes the I/O standard for some on-board LEDs.
+leds_fmc33 = [
+    ("user_led_33", 0, Pins("Y21"), IOStandard("LVCMOS33")),
+    ("user_led_33", 1, Pins("G2"), IOStandard("LVCMOS15")),
+    ("user_led_33", 2, Pins("W21"), IOStandard("LVCMOS33")),
+    ("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")),
+]


-
-class _NIST_CLOCK_RTIO:
+class NIST_CLOCK(ZC706):
    """
    NIST clock hardware, with old backplane and 11 DDS channels
    """
-    def __init__(self):
+    def __init__(self, **kwargs):
+        ZC706.__init__(self, **kwargs)
+
        platform = self.platform
        platform.add_extension(nist_clock.fmc_adapter_io)
        platform.add_extension(leds_fmc33)
-        platform.add_extension(pmod1_33)
-        platform.add_extension(_ams101_dac)
-        platform.add_extension(_pmod_spi)

        rtio_channels = []

+        for i in range(4):
+            phy = ttl_simple.Output(platform.request("user_led_33", i))
+            self.submodules += phy
+            rtio_channels.append(rtio.Channel.from_phy(phy))
+
        for i in range(16):
            if i % 4 == 3:
                phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
@ -490,40 +182,16 @@ class _NIST_CLOCK_RTIO:
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))

-        # no SMA GPIO, replaced with PMOD1_0
-        phy = ttl_serdes_7series.InOut_8X(platform.request("pmod1_33", 0))
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
-
-        phy = ttl_simple.Output(platform.request("user_led_33", 0))
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy))
-
-        ams101_dac = self.platform.request("ams101_dac", 0)
-        phy = ttl_simple.Output(ams101_dac.ldac)
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy))
-
        phy = ttl_simple.ClockGen(platform.request("la32_p"))
        self.submodules += phy
        rtio_channels.append(rtio.Channel.from_phy(phy))

-        phy = spi2.SPIMaster(ams101_dac)
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(
-            phy, ififo_depth=4))
-
        for i in range(3):
            phy = spi2.SPIMaster(self.platform.request("spi", i))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(
                phy, ififo_depth=128))

-        # no SDIO on PL side, dummy SPI placeholder instead
-        phy = spi2.SPIMaster(platform.request("pmod_spi"))
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
-
        phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
        self.submodules += phy
        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
@ -534,51 +202,37 @@ class _NIST_CLOCK_RTIO:
        self.add_rtio(rtio_channels)


-class _NIST_QC2_RTIO:
+class NIST_QC2(ZC706):
    """
    NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
    and 24 DDS channels.  Two backplanes are used.
    """
-    def __init__(self):
+    def __init__(self, **kwargs):
+        ZC706.__init__(self, **kwargs)
+
        platform = self.platform
        platform.add_extension(nist_qc2.fmc_adapter_io)
        platform.add_extension(leds_fmc33)
-        platform.add_extension(_ams101_dac)
-        platform.add_extension(pmod1_33)

        rtio_channels = []

+        for i in range(4):
+            phy = ttl_simple.Output(platform.request("user_led_33", i))
+            self.submodules += phy
+            rtio_channels.append(rtio.Channel.from_phy(phy))
+
        # All TTL channels are In+Out capable
        for i in range(40):
            phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))

-        # no SMA GPIO, replaced with PMOD1_0
-        phy = ttl_serdes_7series.InOut_8X(platform.request("pmod1_33", 0))
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
-
-        phy = ttl_simple.Output(platform.request("user_led_33", 0))
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy))
-
-        ams101_dac = self.platform.request("ams101_dac", 0)
-        phy = ttl_simple.Output(ams101_dac.ldac)
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy))
-
        # CLK0, CLK1 are for clock generators, on backplane SMP connectors
        for i in range(2):
            phy = ttl_simple.ClockGen(
                platform.request("clkout", i))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy))
-        
-        phy = spi2.SPIMaster(ams101_dac)
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(
-            phy, ififo_depth=4))

        for i in range(4):
            phy = spi2.SPIMaster(self.platform.request("spi", i))
@ -598,38 +252,7 @@ class _NIST_QC2_RTIO:
        self.add_rtio(rtio_channels)


-class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
-    def __init__(self, acpki, drtio100mhz):
-        ZC706.__init__(self, acpki)
-        _NIST_CLOCK_RTIO.__init__(self)
-
-class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO):
-    def __init__(self, acpki, drtio100mhz):
-        _MasterBase.__init__(self, acpki, drtio100mhz)
-        _NIST_CLOCK_RTIO.__init__(self)
-
-class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO):
-    def __init__(self, acpki, drtio100mhz):
-        _SatelliteBase.__init__(self, acpki, drtio100mhz)
-        _NIST_CLOCK_RTIO.__init__(self)
-
-class NIST_QC2(ZC706, _NIST_QC2_RTIO):
-    def __init__(self, acpki, drtio100mhz):
-        ZC706.__init__(self, acpki)
-        _NIST_QC2_RTIO.__init__(self)
-
-class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO):
-    def __init__(self, acpki, drtio100mhz):
-        _MasterBase.__init__(self, acpki, drtio100mhz)
-        _NIST_QC2_RTIO.__init__(self)
-
-class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
-    def __init__(self, acpki, drtio100mhz):
-        _SatelliteBase.__init__(self, acpki, drtio100mhz)
-        _NIST_QC2_RTIO.__init__(self)
-
-VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
-                                                  NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
+VARIANTS = {cls.__name__.lower(): cls for cls in [Simple, NIST_CLOCK, NIST_QC2]}


 def write_csr_file(soc, filename):
@ -637,11 +260,6 @@ def write_csr_file(soc, filename):
        f.write(cpu_interface.get_csr_rust(
            soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))

-def write_mem_file(soc, filename):
-    with open(filename, "w") as f:
-        f.write(cpu_interface.get_mem_rust(
-            soc.get_memory_regions(), soc.get_memory_groups(), None))
-

 def write_rustc_cfg_file(soc, filename):
    with open(filename, "w") as f:
@ -657,15 +275,13 @@ def main():
        description="ARTIQ port to the ZC706 Zynq development kit")
    parser.add_argument("-r", default=None,
        help="build Rust interface into the specified file")
-    parser.add_argument("-m", default=None,
-        help="build Rust memory interface into the specified file")
    parser.add_argument("-c", default=None,
        help="build Rust compiler configuration into the specified file")
    parser.add_argument("-g", default=None,
        help="build gateware into the specified directory")
-    parser.add_argument("-V", "--variant", default="nist_clock",
+    parser.add_argument("-V", "--variant", default="simple",
                        help="variant: "
-                             "[acpki_]nist_clock/nist_qc2[_master/_satellite][_100mhz]"
+                             "[acpki_]simple/nist_clock/nist_qc2 "
                             "(default: %(default)s)")
    args = parser.parse_args()

@ -673,25 +289,21 @@ def main():
    acpki = variant.startswith("acpki_")
    if acpki:
        variant = variant[6:]
-    drtio100mhz = variant.endswith("_100mhz")
-    if drtio100mhz:
-        variant = variant[:-7]
    try:
        cls = VARIANTS[variant]
    except KeyError:
        raise SystemExit("Invalid variant (-V/--variant)")

-    soc = cls(acpki=acpki, drtio100mhz=drtio100mhz)
+    soc = cls(acpki=acpki)
    soc.finalize()

    if args.r is not None:
        write_csr_file(soc, args.r)
-    if args.m is not None:
-        write_mem_file(soc, args.m)
    if args.c is not None:
        write_rustc_cfg_file(soc, args.c)
    if args.g is not None:
        soc.build(build_dir=args.g)

+
 if __name__ == "__main__":
    main()
--- a/src/libboard_artiq/Cargo.toml
+++ b/src/libboard_artiq/Cargo.toml
@ -1,31 +0,0 @@
-[package]
-name = "libboard_artiq"
-version = "0.0.0"
-authors = ["M-Labs"]
-edition = "2018"
-
-[lib]
-name = "libboard_artiq"
-
-[features]
-target_zc706 = ["libboard_zynq/target_zc706", "libconfig/target_zc706"]
-target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
-
-[build-dependencies]
-build_zynq = { path = "../libbuild_zynq" }
-
-[dependencies]
-log = "0.4"
-log_buffer = { version = "1.2" }
-crc = { version = "1.7", default-features = false }
-core_io = { version = "0.1", features = ["collections"] }
-embedded-hal = "0.2"
-nb = "1.0"
-void = { version = "1", default-features = false }
-
-io = { path = "../libio", features = ["byteorder"] }
-libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git"}
-libregister = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
-libconfig = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git"}
-libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
-libasync = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
--- a/src/libboard_artiq/build.rs
+++ b/src/libboard_artiq/build.rs
@ -1,5 +0,0 @@
-extern crate build_zynq;
-
-fn main() {
-    build_zynq::cfg();
-}
--- a/src/libboard_artiq/src/drtio_routing.rs
+++ b/src/libboard_artiq/src/drtio_routing.rs
@ -1,109 +0,0 @@
-use libconfig::Config;
-#[cfg(has_drtio_routing)]
-use crate::pl::csr;
-use core::fmt;
-
-use log::{warn, info};
-
-#[cfg(has_drtio_routing)]
-pub const DEST_COUNT: usize = 256;
-#[cfg(not(has_drtio_routing))]
-pub const DEST_COUNT: usize = 0;
-pub const MAX_HOPS: usize = 32;
-pub const INVALID_HOP: u8 = 0xff;
-
-pub struct RoutingTable(pub [[u8; MAX_HOPS]; DEST_COUNT]);
-
-impl RoutingTable {
-    // default routing table is for star topology with no repeaters
-    pub fn default_master(default_n_links: usize) -> RoutingTable {
-        let mut ret = RoutingTable([[INVALID_HOP; MAX_HOPS]; DEST_COUNT]);
-        let n_entries = default_n_links + 1;  // include local RTIO
-        for i in 0..n_entries {
-            ret.0[i][0] = i as u8;
-        }
-        for i in 1..n_entries {
-            ret.0[i][1] = 0x00;
-        }
-        ret
-    }
-
-    // use this by default on satellite, as they receive
-    // the routing table from the master
-    pub fn default_empty() -> RoutingTable {
-        RoutingTable([[INVALID_HOP; MAX_HOPS]; DEST_COUNT])
-    }
-}
-
-impl fmt::Display for RoutingTable {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        write!(f, "RoutingTable {{")?;
-        for i in 0..DEST_COUNT {
-            if self.0[i][0] != INVALID_HOP {
-                write!(f, " {}:", i)?;
-                for j in 0..MAX_HOPS {
-                    if self.0[i][j] == INVALID_HOP {
-                        break;
-                    }
-                    write!(f, " {}", self.0[i][j])?;
-                }
-                write!(f, ";")?;
-            }
-        }
-        write!(f, " }}")?;
-        Ok(())
-    }
-}
-
-pub fn config_routing_table(default_n_links: usize, cfg: &Config) -> RoutingTable {
-    let mut ret = RoutingTable::default_master(default_n_links);
-    if let Ok(data) = cfg.read("routing_table") {
-        if data.len() == DEST_COUNT*MAX_HOPS
-        {
-            for i in 0..DEST_COUNT {
-                for j in 0..MAX_HOPS {
-                    ret.0[i][j] = data[i*MAX_HOPS+j];
-                }
-            }
-        }
-        else {
-            warn!("length of the routing table is incorrect, using default");
-        }
-    }
-    else {
-        warn!("could not read routing table from configuration, using default");
-    }
-    info!("routing table: {}", ret);
-    ret
-}
-
-#[cfg(has_drtio_routing)]
-pub fn interconnect_enable(routing_table: &RoutingTable, rank: u8, destination: u8) {
-    let hop = routing_table.0[destination as usize][rank as usize];
-    unsafe {
-        csr::routing_table::destination_write(destination);
-        csr::routing_table::hop_write(hop);
-    }
-}
-
-#[cfg(has_drtio_routing)]
-pub fn interconnect_disable(destination: u8) {
-    unsafe {
-        csr::routing_table::destination_write(destination);
-        csr::routing_table::hop_write(INVALID_HOP);
-    }
-}
-
-#[cfg(has_drtio_routing)]
-pub fn interconnect_enable_all(routing_table: &RoutingTable, rank: u8) {
-    for i in 0..DEST_COUNT {
-        interconnect_enable(routing_table, rank, i as u8);
-    }
-}
-
-#[cfg(has_drtio_routing)]
-pub fn interconnect_disable_all() {
-    for i in 0..DEST_COUNT {
-        interconnect_disable(i as u8);
-    }
-}
--- a/src/libboard_artiq/src/drtioaux.rs
+++ b/src/libboard_artiq/src/drtioaux.rs
@ -1,166 +0,0 @@
-use crc;
-
-use core_io::{ErrorKind as IoErrorKind, Error as IoError};
-use io::{proto::ProtoRead, proto::ProtoWrite, Cursor};
-use libboard_zynq::{timer::GlobalTimer, time::Milliseconds};
-use crate::mem::mem::DRTIOAUX_MEM;
-use crate::pl::csr::DRTIOAUX;
-use crate::drtioaux_proto::Error as ProtocolError;
-
-pub use crate::drtioaux_proto::Packet;
-
-#[derive(Debug)]
-pub enum Error {
-    GatewareError,
-    CorruptedPacket,
-
-    LinkDown,
-    TimedOut,
-    UnexpectedReply,
-
-    RoutingError,
-
-    Protocol(ProtocolError)
-}
-
-impl From<ProtocolError> for Error {
-    fn from(value: ProtocolError) -> Error {
-        Error::Protocol(value)
-    }
-}
-
-impl From<IoError> for Error {
-    fn from(value: IoError) -> Error {
-        Error::Protocol(ProtocolError::Io(value))
-    }
-}
-
-pub fn reset(linkno: u8) {
-    let linkno = linkno as usize;
-    unsafe {
-        // clear buffer first to limit race window with buffer overflow
-        // error. We assume the CPU is fast enough so that no two packets
-        // will be received between the buffer and the error flag are cleared.
-        (DRTIOAUX[linkno].aux_rx_present_write)(1);
-        (DRTIOAUX[linkno].aux_rx_error_write)(1);
-    }
-}
-
-pub fn has_rx_error(linkno: u8) -> bool {
-    let linkno = linkno as usize;
-    unsafe {
-        let error = (DRTIOAUX[linkno].aux_rx_error_read)() != 0;
-        if error {
-            (DRTIOAUX[linkno].aux_rx_error_write)(1)
-        }
-        error
-    }
-}
-
-pub fn copy_work_buffer(src: *mut u16, dst: *mut u16, len: isize) {
-    // AXI writes must be 4-byte aligned (drtio proto doesn't care for that),
-    // and AXI burst reads/writes are not implemented yet in gateware
-    // thus the need for a work buffer for transmitting and copying it over
-    unsafe {
-        for i in (0..(len/2)).step_by(2) {
-            *dst.offset(i) = *src.offset(i);
-            *dst.offset(i+1) = *src.offset(i+1);
-        }
-    }
-}
-
-fn receive<F, T>(linkno: u8, f: F) -> Result<Option<T>, Error>
-    where F: FnOnce(&[u8]) -> Result<T, Error>
-{
-    let linkidx = linkno as usize;
-    unsafe {
-        if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
-            let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2) as *mut u16;
-            let len = (DRTIOAUX[linkidx].aux_rx_length_read)() as usize;
-            // work buffer to accomodate axi burst reads
-            let mut buf: [u8; 1024] = [0; 1024];
-            copy_work_buffer(ptr, buf.as_mut_ptr() as *mut u16, len as isize);
-            let result = f(&buf[0..len]);
-            (DRTIOAUX[linkidx].aux_rx_present_write)(1);
-            Ok(Some(result?))
-        } else {
-            Ok(None)
-        }
-    }
-}
-
-pub fn recv(linkno: u8) -> Result<Option<Packet>, Error> {
-    if has_rx_error(linkno) {
-        return Err(Error::GatewareError)
-    }
-
-    receive(linkno, |buffer| {
-        if buffer.len() < 8 {
-            return Err(IoError::new(IoErrorKind::UnexpectedEof, "Unexpected end").into())
-        }
-
-        let mut reader = Cursor::new(buffer);
-
-        let checksum_at = buffer.len() - 4;
-        let checksum = crc::crc32::checksum_ieee(&reader.get_ref()[0..checksum_at]);
-        reader.set_position(checksum_at);
-        if reader.read_u32()? != checksum {
-            return Err(Error::CorruptedPacket)
-        }
-        reader.set_position(0);
-
-        Ok(Packet::read_from(&mut reader)?)
-    })
-}
-
-pub fn recv_timeout(linkno: u8, timeout_ms: Option<u64>,
-    timer: GlobalTimer) -> Result<Packet, Error> 
-{
-    let timeout_ms = Milliseconds(timeout_ms.unwrap_or(10));
-    let limit = timer.get_time() + timeout_ms;
-    while timer.get_time() < limit {
-        match recv(linkno)? {
-            None => (),
-            Some(packet) => return Ok(packet),
-        }
-    }
-    Err(Error::TimedOut)
-}
-
-fn transmit<F>(linkno: u8, f: F) -> Result<(), Error>
-    where F: FnOnce(&mut [u8]) -> Result<usize, Error>
-{
-    let linkno = linkno as usize;
-    unsafe {
-        while (DRTIOAUX[linkno].aux_tx_read)() != 0 {}
-        let ptr = DRTIOAUX_MEM[linkno].base as *mut u16;
-        let len = DRTIOAUX_MEM[linkno].size / 2;
-        // work buffer, works with unaligned mem access
-        let mut buf: [u8; 1024] = [0; 1024]; 
-        let len = f(&mut buf[0..len])?;
-        copy_work_buffer(buf.as_mut_ptr() as *mut u16, ptr, len as isize);
-        (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
-        (DRTIOAUX[linkno].aux_tx_write)(1);
-        Ok(())
-    }
-}
-
-pub fn send(linkno: u8, packet: &Packet) -> Result<(), Error> {
-    transmit(linkno, |buffer| {
-        let mut writer = Cursor::new(buffer);
-
-        packet.write_to(&mut writer)?;
-        
-        let padding = 4 - (writer.position() % 4);
-        if padding != 4 {
-            for _ in 0..padding {
-                writer.write_u8(0)?;
-            }
-        }
-
-        let checksum = crc::crc32::checksum_ieee(&writer.get_ref()[0..writer.position()]);
-        writer.write_u32(checksum)?;
-
-        Ok(writer.position())
-    })
-}
--- a/src/libboard_artiq/src/drtioaux_async.rs
+++ b/src/libboard_artiq/src/drtioaux_async.rs
@ -1,139 +0,0 @@
-use crc;
-
-use core_io::{ErrorKind as IoErrorKind, Error as IoError};
-use void::Void;
-use nb;
-
-use libboard_zynq::{timer::GlobalTimer, time::Milliseconds};
-use libasync::{task, block_async};
-
-use io::{proto::ProtoRead, proto::ProtoWrite, Cursor};
-use crate::mem::mem::DRTIOAUX_MEM;
-use crate::pl::csr::DRTIOAUX;
-use crate::drtioaux::{Error, has_rx_error, copy_work_buffer};
-
-pub use crate::drtioaux_proto::Packet;
-
-pub async fn reset(linkno: u8) {
-    let linkno = linkno as usize;
-    unsafe {
-        // clear buffer first to limit race window with buffer overflow
-        // error. We assume the CPU is fast enough so that no two packets
-        // will be received between the buffer and the error flag are cleared.
-        (DRTIOAUX[linkno].aux_rx_present_write)(1);
-        (DRTIOAUX[linkno].aux_rx_error_write)(1);
-    }
-}
-
-fn tx_ready(linkno: usize) -> nb::Result<(), Void> {
-    unsafe {
-        if (DRTIOAUX[linkno].aux_tx_read)() != 0 {
-            Err(nb::Error::WouldBlock)
-        }
-        else {
-            Ok(())
-        }
-    }
-}
-
-async fn receive<F, T>(linkno: u8, f: F) -> Result<Option<T>, Error>
-    where F: FnOnce(&[u8]) -> Result<T, Error>
-{
-    let linkidx = linkno as usize;
-    unsafe {
-        if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
-            let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2) as *mut u16;
-            let len = (DRTIOAUX[linkidx].aux_rx_length_read)() as usize;
-            // work buffer to accomodate axi burst reads
-            let mut buf: [u8; 1024] = [0; 1024];
-            copy_work_buffer(ptr, buf.as_mut_ptr() as *mut u16, len as isize);
-            let result = f(&buf[0..len]);
-            (DRTIOAUX[linkidx].aux_rx_present_write)(1);
-            Ok(Some(result?))
-        } else {
-            Ok(None)
-        }
-    }
-}
-
-pub async fn recv(linkno: u8) -> Result<Option<Packet>, Error> {
-    if has_rx_error(linkno) {
-        return Err(Error::GatewareError)
-    }
-
-    receive(linkno, |buffer| {
-        if buffer.len() < 8 {
-            return Err(IoError::new(IoErrorKind::UnexpectedEof, "Unexpected end").into())
-        }
-
-        let mut reader = Cursor::new(buffer);
-
-        let checksum_at = buffer.len() - 4;
-        let checksum = crc::crc32::checksum_ieee(&reader.get_ref()[0..checksum_at]);
-        reader.set_position(checksum_at);
-        if reader.read_u32()? != checksum {
-            return Err(Error::CorruptedPacket)
-        }
-        reader.set_position(0);
-
-        Ok(Packet::read_from(&mut reader)?)
-    }).await
-}
-
-pub async fn recv_timeout(linkno: u8, timeout_ms: Option<u64>,
-    timer: GlobalTimer) -> Result<Packet, Error> 
-{
-    let timeout_ms = Milliseconds(timeout_ms.unwrap_or(10));
-    let limit = timer.get_time() + timeout_ms;
-    let mut would_block = false;
-    while timer.get_time() < limit {
-        // to ensure one last time recv would run one last time
-        // in case async would return after timeout
-        if would_block {
-            task::r#yield().await;
-        }
-        match recv(linkno).await? {
-            None => { would_block = true; },
-            Some(packet) => return Ok(packet),
-        }
-    }
-    Err(Error::TimedOut)
-}
-
-async fn transmit<F>(linkno: u8, f: F) -> Result<(), Error>
-    where F: FnOnce(&mut [u8]) -> Result<usize, Error>
-{
-    let linkno = linkno as usize;
-    unsafe {
-        let _ = block_async!(tx_ready(linkno)).await;
-        let ptr = DRTIOAUX_MEM[linkno].base as *mut u16;
-        let len = DRTIOAUX_MEM[linkno].size / 2;
-        // work buffer, works with unaligned mem access
-        let mut buf: [u8; 1024] = [0; 1024]; 
-        let len = f(&mut buf[0..len])?;
-        copy_work_buffer(buf.as_mut_ptr() as *mut u16, ptr, len as isize);
-        (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
-        (DRTIOAUX[linkno].aux_tx_write)(1);
-        Ok(())
-    }
-}
-
-pub async fn send(linkno: u8, packet: &Packet) -> Result<(), Error> {
-    transmit(linkno, |buffer| {
-        let mut writer = Cursor::new(buffer);
-
-        packet.write_to(&mut writer)?;
-        
-        let padding = 4 - (writer.position() % 4);
-        if padding != 4 {
-            for _ in 0..padding {
-                writer.write_u8(0)?;
-            }
-        }
-
-        let checksum = crc::crc32::checksum_ieee(&writer.get_ref()[0..writer.position()]);
-        writer.write_u32(checksum)?;
-
-        Ok(writer.position())
-    }).await
-}
--- a/src/libboard_artiq/src/drtioaux_proto.rs
+++ b/src/libboard_artiq/src/drtioaux_proto.rs
@ -1,339 +0,0 @@
-use core_io::{Write, Read, Error as IoError};
-
-use io::proto::{ProtoWrite, ProtoRead};
-
-#[derive(Debug)]
-pub enum Error {
-    UnknownPacket(u8),
-    Io(IoError)
-}
-
-impl From<IoError> for Error {
-    fn from(value: IoError) -> Error {
-        Error::Io(value)
-    }
-}
-
-#[derive(PartialEq, Debug)]
-pub enum Packet {
-    EchoRequest,
-    EchoReply,
-    ResetRequest,
-    ResetAck,
-    TSCAck,
-
-    DestinationStatusRequest { destination: u8 },
-    DestinationDownReply,
-    DestinationOkReply,
-    DestinationSequenceErrorReply { channel: u16 },
-    DestinationCollisionReply { channel: u16 },
-    DestinationBusyReply { channel: u16 },
-
-    RoutingSetPath { destination: u8, hops: [u8; 32] },
-    RoutingSetRank { rank: u8 },
-    RoutingAck,
-
-    MonitorRequest { destination: u8, channel: u16, probe: u8 },
-    MonitorReply { value: u32 },
-    InjectionRequest { destination: u8, channel: u16, overrd: u8, value: u8 },
-    InjectionStatusRequest { destination: u8, channel: u16, overrd: u8 },
-    InjectionStatusReply { value: u8 },
-
-    I2cStartRequest { destination: u8, busno: u8 },
-    I2cRestartRequest { destination: u8, busno: u8 },
-    I2cStopRequest { destination: u8, busno: u8 },
-    I2cWriteRequest { destination: u8, busno: u8, data: u8 },
-    I2cWriteReply { succeeded: bool, ack: bool },
-    I2cReadRequest { destination: u8, busno: u8, ack: bool },
-    I2cReadReply { succeeded: bool, data: u8 },
-    I2cBasicReply { succeeded: bool },
-
-    SpiSetConfigRequest { destination: u8, busno: u8, flags: u8, length: u8, div: u8, cs: u8 },
-    SpiWriteRequest { destination: u8, busno: u8, data: u32 },
-    SpiReadRequest { destination: u8, busno: u8 },
-    SpiReadReply { succeeded: bool, data: u32 },
-    SpiBasicReply { succeeded: bool },
-
-}
-
-impl Packet {
-    pub fn read_from<R>(reader: &mut R) -> Result<Self, Error>
-        where R: Read + ?Sized
-    {
-        Ok(match reader.read_u8()? {
-            0x00 => Packet::EchoRequest,
-            0x01 => Packet::EchoReply,
-            0x02 => Packet::ResetRequest,
-            0x03 => Packet::ResetAck,
-            0x04 => Packet::TSCAck,
-
-            0x20 => Packet::DestinationStatusRequest {
-                destination: reader.read_u8()?
-            },
-            0x21 => Packet::DestinationDownReply,
-            0x22 => Packet::DestinationOkReply,
-            0x23 => Packet::DestinationSequenceErrorReply {
-                channel: reader.read_u16()?
-            },
-            0x24 => Packet::DestinationCollisionReply {
-                channel: reader.read_u16()?
-            },
-            0x25 => Packet::DestinationBusyReply {
-                channel: reader.read_u16()?
-            },
-
-            0x30 => {
-                let destination = reader.read_u8()?;
-                let mut hops = [0; 32];
-                reader.read_exact(&mut hops)?;
-                Packet::RoutingSetPath {
-                    destination: destination,
-                    hops: hops
-                }
-            },
-            0x31 => Packet::RoutingSetRank {
-                rank: reader.read_u8()?
-            },
-            0x32 => Packet::RoutingAck,
-
-            0x40 => Packet::MonitorRequest {
-                destination: reader.read_u8()?,
-                channel: reader.read_u16()?,
-                probe: reader.read_u8()?
-            },
-            0x41 => Packet::MonitorReply {
-                value: reader.read_u32()?
-            },
-            0x50 => Packet::InjectionRequest {
-                destination: reader.read_u8()?,
-                channel: reader.read_u16()?,
-                overrd: reader.read_u8()?,
-                value: reader.read_u8()?
-            },
-            0x51 => Packet::InjectionStatusRequest {
-                destination: reader.read_u8()?,
-                channel: reader.read_u16()?,
-                overrd: reader.read_u8()?
-            },
-            0x52 => Packet::InjectionStatusReply {
-                value: reader.read_u8()?
-            },
-
-            0x80 => Packet::I2cStartRequest {
-                destination: reader.read_u8()?,
-                busno: reader.read_u8()?
-            },
-            0x81 => Packet::I2cRestartRequest {
-                destination: reader.read_u8()?,
-                busno: reader.read_u8()?
-            },
-            0x82 => Packet::I2cStopRequest {
-                destination: reader.read_u8()?,
-                busno: reader.read_u8()?
-            },
-            0x83 => Packet::I2cWriteRequest {
-                destination: reader.read_u8()?,
-                busno: reader.read_u8()?,
-                data: reader.read_u8()?
-            },
-            0x84 => Packet::I2cWriteReply {
-                succeeded: reader.read_bool()?,
-                ack: reader.read_bool()?
-            },
-            0x85 => Packet::I2cReadRequest {
-                destination: reader.read_u8()?,
-                busno: reader.read_u8()?,
-                ack: reader.read_bool()?
-            },
-            0x86 => Packet::I2cReadReply {
-                succeeded: reader.read_bool()?,
-                data: reader.read_u8()?
-            },
-            0x87 => Packet::I2cBasicReply {
-                succeeded: reader.read_bool()?
-            },
-
-            0x90 => Packet::SpiSetConfigRequest {
-                destination: reader.read_u8()?,
-                busno: reader.read_u8()?,
-                flags: reader.read_u8()?,
-                length: reader.read_u8()?,
-                div: reader.read_u8()?,
-                cs: reader.read_u8()?
-            },
-            /* 0x91: was Packet::SpiSetXferRequest */
-            0x92 => Packet::SpiWriteRequest {
-                destination: reader.read_u8()?,
-                busno: reader.read_u8()?,
-                data: reader.read_u32()?
-            },
-            0x93 => Packet::SpiReadRequest {
-                destination: reader.read_u8()?,
-                busno: reader.read_u8()?
-            },
-            0x94 => Packet::SpiReadReply {
-                succeeded: reader.read_bool()?,
-                data: reader.read_u32()?
-            },
-            0x95 => Packet::SpiBasicReply {
-                succeeded: reader.read_bool()?
-            },
-
-            ty => return Err(Error::UnknownPacket(ty))
-        })
-    }
-
-    pub fn write_to<W>(&self, writer: &mut W) -> Result<(), IoError>
-        where W: Write + ?Sized
-    {
-
-        match *self {
-            Packet::EchoRequest =>
-                writer.write_u8(0x00)?,
-            Packet::EchoReply =>
-                writer.write_u8(0x01)?,
-            Packet::ResetRequest =>
-                writer.write_u8(0x02)?,
-            Packet::ResetAck =>
-                writer.write_u8(0x03)?,
-            Packet::TSCAck =>
-                writer.write_u8(0x04)?,
-
-            Packet::DestinationStatusRequest { destination } => {
-                writer.write_u8(0x20)?;
-                writer.write_u8(destination)?;
-            },
-            Packet::DestinationDownReply =>
-                writer.write_u8(0x21)?,
-            Packet::DestinationOkReply =>
-                writer.write_u8(0x22)?,
-            Packet::DestinationSequenceErrorReply { channel } => {
-                writer.write_u8(0x23)?;
-                writer.write_u16(channel)?;
-            },
-            Packet::DestinationCollisionReply { channel } => {
-                writer.write_u8(0x24)?;
-                writer.write_u16(channel)?;
-            },
-            Packet::DestinationBusyReply { channel } => {
-                writer.write_u8(0x25)?;
-                writer.write_u16(channel)?;
-            },
-
-            Packet::RoutingSetPath { destination, hops } => {
-                writer.write_u8(0x30)?;
-                writer.write_u8(destination)?;
-                writer.write_all(&hops)?;
-            },
-            Packet::RoutingSetRank { rank } => {
-                writer.write_u8(0x31)?;
-                writer.write_u8(rank)?;
-            },
-            Packet::RoutingAck =>
-                writer.write_u8(0x32)?,
-
-            Packet::MonitorRequest { destination, channel, probe } => {
-                writer.write_u8(0x40)?;
-                writer.write_u8(destination)?;
-                writer.write_u16(channel)?;
-                writer.write_u8(probe)?;
-            },
-            Packet::MonitorReply { value } => {
-                writer.write_u8(0x41)?;
-                writer.write_u32(value)?;
-            },
-            Packet::InjectionRequest { destination, channel, overrd, value } => {
-                writer.write_u8(0x50)?;
-                writer.write_u8(destination)?;
-                writer.write_u16(channel)?;
-                writer.write_u8(overrd)?;
-                writer.write_u8(value)?;
-            },
-            Packet::InjectionStatusRequest { destination, channel, overrd } => {
-                writer.write_u8(0x51)?;
-                writer.write_u8(destination)?;
-                writer.write_u16(channel)?;
-                writer.write_u8(overrd)?;
-            },
-            Packet::InjectionStatusReply { value } => {
-                writer.write_u8(0x52)?;
-                writer.write_u8(value)?;
-            },
-
-            Packet::I2cStartRequest { destination, busno } => {
-                writer.write_u8(0x80)?;
-                writer.write_u8(destination)?;
-                writer.write_u8(busno)?;
-            },
-            Packet::I2cRestartRequest { destination, busno } => {
-                writer.write_u8(0x81)?;
-                writer.write_u8(destination)?;
-                writer.write_u8(busno)?;
-            },
-            Packet::I2cStopRequest { destination, busno } => {
-                writer.write_u8(0x82)?;
-                writer.write_u8(destination)?;
-                writer.write_u8(busno)?;
-            },
-            Packet::I2cWriteRequest { destination, busno, data } => {
-                writer.write_u8(0x83)?;
-                writer.write_u8(destination)?;
-                writer.write_u8(busno)?;
-                writer.write_u8(data)?;
-            },
-            Packet::I2cWriteReply { succeeded, ack } => {
-                writer.write_u8(0x84)?;
-                writer.write_bool(succeeded)?;
-                writer.write_bool(ack)?;
-            },
-            Packet::I2cReadRequest { destination, busno, ack } => {
-                writer.write_u8(0x85)?;
-                writer.write_u8(destination)?;
-                writer.write_u8(busno)?;
-                writer.write_bool(ack)?;
-            },
-            Packet::I2cReadReply { succeeded, data } => {
-                writer.write_u8(0x86)?;
-                writer.write_bool(succeeded)?;
-                writer.write_u8(data)?;
-            },
-            Packet::I2cBasicReply { succeeded } => {
-                writer.write_u8(0x87)?;
-                writer.write_bool(succeeded)?;
-            },
-
-            Packet::SpiSetConfigRequest { destination, busno, flags, length, div, cs } => {
-                writer.write_u8(0x90)?;
-                writer.write_u8(destination)?;
-                writer.write_u8(busno)?;
-                writer.write_u8(flags)?;
-                writer.write_u8(length)?;
-                writer.write_u8(div)?;
-                writer.write_u8(cs)?;
-            },
-            Packet::SpiWriteRequest { destination, busno, data } => {
-                writer.write_u8(0x92)?;
-                writer.write_u8(destination)?;
-                writer.write_u8(busno)?;
-                writer.write_u32(data)?;
-            },
-            Packet::SpiReadRequest { destination, busno } => {
-                writer.write_u8(0x93)?;
-                writer.write_u8(destination)?;
-                writer.write_u8(busno)?;
-            },
-            Packet::SpiReadReply { succeeded, data } => {
-                writer.write_u8(0x94)?;
-                writer.write_bool(succeeded)?;
-                writer.write_u32(data)?;
-            },
-            Packet::SpiBasicReply { succeeded } => {
-                writer.write_u8(0x95)?;
-                writer.write_bool(succeeded)?;
-            },
-
-        }
-        Ok(())
-    }
-    
-}
--- a/src/libboard_artiq/src/lib.rs
+++ b/src/libboard_artiq/src/lib.rs
@ -1,69 +0,0 @@
-#![no_std]
-#![feature(never_type)]
-
-extern crate log;
-extern crate crc;
-extern crate embedded_hal;
-extern crate core_io;
-extern crate io;
-extern crate libboard_zynq;
-extern crate libregister;
-extern crate libconfig;
-extern crate libcortex_a9;
-extern crate libasync;
-extern crate log_buffer;
-
-#[path = "../../../build/pl.rs"]
-pub mod pl;
-pub mod drtioaux_proto;
-pub mod drtio_routing;
-pub mod logger;
-#[cfg(has_si5324)]
-pub mod si5324;
-#[cfg(has_drtio)]
-pub mod drtioaux;
-#[cfg(has_drtio)]
-pub mod drtioaux_async;
-#[cfg(has_drtio)]
-#[path = "../../../build/mem.rs"]
-pub mod mem;
-
-use core::{cmp, str};
-use libboard_zynq::slcr;
-use libregister::RegisterW;
-
-pub fn identifier_read(buf: &mut [u8]) -> &str {
-    unsafe {
-        pl::csr::identifier::address_write(0);
-        let len = pl::csr::identifier::data_read();
-        let len = cmp::min(len, buf.len() as u8);
-        for i in 0..len {
-            pl::csr::identifier::address_write(1 + i);
-            buf[i as usize] = pl::csr::identifier::data_read();
-        }
-        str::from_utf8_unchecked(&buf[..len as usize])
-    }
-}
-
-pub fn init_gateware() {
-    // Set up PS->PL clocks
-    slcr::RegisterBlock::unlocked(|slcr| {
-        // As we are touching the mux, the clock may glitch, so reset the PL.
-        slcr.fpga_rst_ctrl.write(
-            slcr::FpgaRstCtrl::zeroed()
-                .fpga0_out_rst(true)
-                .fpga1_out_rst(true)
-                .fpga2_out_rst(true)
-                .fpga3_out_rst(true)
-        );
-        slcr.fpga0_clk_ctrl.write(
-            slcr::Fpga0ClkCtrl::zeroed()
-                .src_sel(slcr::PllSource::IoPll)
-                .divisor0(8)
-                .divisor1(1)
-        );
-        slcr.fpga_rst_ctrl.write(
-            slcr::FpgaRstCtrl::zeroed()
-        );
-    });
-}
--- a/src/libboard_artiq/src/si5324.rs
+++ b/src/libboard_artiq/src/si5324.rs
@ -1,353 +0,0 @@
-use core::result;
-use log::info;
-use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds};
-use embedded_hal::blocking::delay::DelayUs;
-#[cfg(not(si5324_soft_reset))]
-use crate::pl::csr;
-
-type Result<T> = result::Result<T, &'static str>;
-
-const ADDRESS: u8 = 0x68;
-
-#[cfg(not(si5324_soft_reset))]
-fn hard_reset(timer: &mut GlobalTimer) {
-    unsafe { csr::si5324_rst_n::out_write(0); }
-    timer.delay_us(1_000);
-    unsafe { csr::si5324_rst_n::out_write(1); }
-    timer.delay_us(10_000);
-}
-
-// NOTE: the logical parameters DO NOT MAP to physical values written
-// into registers. They have to be mapped; see the datasheet.
-// DSPLLsim reports the logical parameters in the design summary, not
-// the physical register values.
-pub struct FrequencySettings {
-    pub n1_hs: u8,
-    pub nc1_ls: u32,
-    pub n2_hs: u8,
-    pub n2_ls: u32,
-    pub n31: u32,
-    pub n32: u32,
-    pub bwsel: u8,
-    pub crystal_ref: bool
-}
-
-pub enum Input {
-    Ckin1,
-    Ckin2,
-}
-
-fn map_frequency_settings(settings: &FrequencySettings) -> Result<FrequencySettings> {
-    if settings.nc1_ls != 0 && (settings.nc1_ls % 2) == 1 {
-        return Err("NC1_LS must be 0 or even")
-    }
-    if settings.nc1_ls > (1 << 20) {
-        return Err("NC1_LS is too high")
-    }
-    if (settings.n2_ls % 2) == 1 {
-        return Err("N2_LS must be even")
-    }
-    if settings.n2_ls > (1 << 20) {
-        return Err("N2_LS is too high")
-    }
-    if settings.n31 > (1 << 19) {
-        return Err("N31 is too high")
-    }
-    if settings.n32 > (1 << 19) {
-        return Err("N32 is too high")
-    }
-    let r = FrequencySettings {
-        n1_hs: match settings.n1_hs {
-            4  => 0b000,
-            5  => 0b001,
-            6  => 0b010,
-            7  => 0b011,
-            8  => 0b100,
-            9  => 0b101,
-            10 => 0b110,
-            11 => 0b111,
-            _  => return Err("N1_HS has an invalid value")
-        },
-        nc1_ls: settings.nc1_ls - 1,
-        n2_hs: match settings.n2_hs {
-            4  => 0b000,
-            5  => 0b001,
-            6  => 0b010,
-            7  => 0b011,
-            8  => 0b100,
-            9  => 0b101,
-            10 => 0b110,
-            11 => 0b111,
-            _  => return Err("N2_HS has an invalid value")
-        },
-        n2_ls: settings.n2_ls - 1,
-        n31: settings.n31 - 1,
-        n32: settings.n32 - 1,
-        bwsel: settings.bwsel,
-        crystal_ref: settings.crystal_ref
-    };
-    Ok(r)
-}
-
-fn write(i2c: &mut I2c, reg: u8, val: u8) -> Result<()> {
-    i2c.start().unwrap();
-    if !i2c.write(ADDRESS << 1).unwrap() {
-        return Err("Si5324 failed to ack write address")
-    }
-    if !i2c.write(reg).unwrap() {
-        return Err("Si5324 failed to ack register")
-    }
-    if !i2c.write(val).unwrap() {
-        return Err("Si5324 failed to ack value")
-    }
-    i2c.stop().unwrap();
-    Ok(())
-}
-
-#[allow(dead_code)]
-fn write_no_ack_value(i2c: &mut I2c, reg: u8, val: u8) -> Result<()> {
-    i2c.start().unwrap();
-    if !i2c.write(ADDRESS << 1).unwrap() {
-        return Err("Si5324 failed to ack write address")
-    }
-    if !i2c.write(reg).unwrap() {
-        return Err("Si5324 failed to ack register")
-    }
-    i2c.write(val).unwrap();
-    i2c.stop().unwrap();
-    Ok(())
-}
-
-fn read(i2c: &mut I2c, reg: u8) -> Result<u8> {
-    i2c.start().unwrap();
-    if !i2c.write(ADDRESS << 1).unwrap() {
-        return Err("Si5324 failed to ack write address")
-    }
-    if !i2c.write(reg).unwrap() {
-        return Err("Si5324 failed to ack register")
-    }
-    i2c.restart().unwrap();
-    if !i2c.write((ADDRESS << 1) | 1).unwrap() {
-        return Err("Si5324 failed to ack read address")
-    }
-    let val = i2c.read(false).unwrap();
-    i2c.stop().unwrap();
-    Ok(val)
-}
-
-fn rmw<F>(i2c: &mut I2c, reg: u8, f: F) -> Result<()> where
-        F: Fn(u8) -> u8 {
-    let value = read(i2c, reg)?;
-    write(i2c, reg, f(value))?;
-    Ok(())
-}
-
-fn ident(i2c: &mut I2c) -> Result<u16> {
-    Ok(((read(i2c, 134)? as u16) << 8) | (read(i2c, 135)? as u16))
-}
-
-#[cfg(si5324_soft_reset)]
-fn soft_reset(i2c: &mut I2c, timer: &mut GlobalTimer) -> Result<()> {
-    let val = read(i2c, 136)?;
-    write_no_ack_value(i2c, 136, val | 0x80)?;
-    timer.delay_us(10_000);
-    Ok(())
-}
-
-fn has_xtal(i2c: &mut I2c) -> Result<bool> {
-    Ok((read(i2c, 129)? & 0x01) == 0)  // LOSX_INT=0
-}
-
-fn has_ckin(i2c: &mut I2c, input: Input) -> Result<bool> {
-    match input {
-        Input::Ckin1 => Ok((read(i2c, 129)? & 0x02) == 0),  // LOS1_INT=0
-        Input::Ckin2 => Ok((read(i2c, 129)? & 0x04) == 0),  // LOS2_INT=0
-    }
-}
-
-fn locked(i2c: &mut I2c) -> Result<bool> {
-    Ok((read(i2c, 130)? & 0x01) == 0)  // LOL_INT=0
-}
-
-fn monitor_lock(i2c: &mut I2c, timer: &mut GlobalTimer) -> Result<()> {
-    info!("waiting for Si5324 lock...");
-    let timeout = timer.get_time() + Milliseconds(20_000);
-    while !locked(i2c)? {
-        // Yes, lock can be really slow.
-        if timer.get_time() > timeout {
-            return Err("Si5324 lock timeout");
-        }
-    }
-    info!("  ...locked");
-    Ok(())
-}
-
-fn init(i2c: &mut I2c, timer: &mut GlobalTimer) -> Result<()> {
-    #[cfg(not(si5324_soft_reset))]
-    hard_reset(timer);
-
-    #[cfg(feature = "target_kasli_soc")]
-    {
-        i2c.pca954x_select(0x70, None)?;
-        i2c.pca954x_select(0x71, Some(3))?;
-    }
-    #[cfg(feature = "target_zc706")]
-    {
-        i2c.pca954x_select(0x74, Some(4))?;
-    }
-
-    if ident(i2c)? != 0x0182 {
-        return Err("Si5324 does not have expected product number");
-    }
-
-    #[cfg(si5324_soft_reset)]
-    soft_reset(i2c, timer)?;
-    Ok(())
-}
-
-pub fn bypass(i2c: &mut I2c, input: Input, timer: &mut GlobalTimer) -> Result<()> {
-    let cksel_reg = match input {
-        Input::Ckin1 => 0b00,
-        Input::Ckin2 => 0b01,
-    };
-    init(i2c, timer)?;
-    rmw(i2c, 21,  |v| v & 0xfe)?;                        // CKSEL_PIN=0
-    rmw(i2c, 3,   |v| (v & 0x3f) | (cksel_reg << 6))?;   // CKSEL_REG
-    rmw(i2c, 4,   |v| (v & 0x3f) | (0b00 << 6))?;        // AUTOSEL_REG=b00
-    rmw(i2c, 6,   |v| (v & 0xc0) | 0b111111)?;           // SFOUT2_REG=b111 SFOUT1_REG=b111
-    rmw(i2c, 0,   |v| (v & 0xfd) | 0x02)?;               // BYPASS_REG=1
-    Ok(())
-}
-
-pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, input: Input, timer: &mut GlobalTimer) -> Result<()> {
-    let s = map_frequency_settings(settings)?;
-    let cksel_reg = match input {
-        Input::Ckin1 => 0b00,
-        Input::Ckin2 => 0b01,
-    };
-
-    init(i2c, timer)?;
-    if settings.crystal_ref {
-        rmw(i2c, 0,   |v| v | 0x40)?;                     // FREE_RUN=1
-    }
-    rmw(i2c, 2,   |v| (v & 0x0f) | (s.bwsel << 4))?;
-    rmw(i2c, 21,  |v| v & 0xfe)?;                        // CKSEL_PIN=0
-    rmw(i2c, 3,   |v| (v & 0x2f) | (cksel_reg << 6) | 0x10)?;  // CKSEL_REG, SQ_ICAL=1
-    rmw(i2c, 4,   |v| (v & 0x3f) | (0b00 << 6))?;        // AUTOSEL_REG=b00
-    rmw(i2c, 6,   |v| (v & 0xc0) | 0b111111)?;           // SFOUT2_REG=b111 SFOUT1_REG=b111
-    write(i2c, 25,  (s.n1_hs  << 5 ) as u8)?;
-    write(i2c, 31,  (s.nc1_ls >> 16) as u8)?;
-    write(i2c, 32,  (s.nc1_ls >> 8 ) as u8)?;
-    write(i2c, 33,  (s.nc1_ls)       as u8)?;
-    write(i2c, 34,  (s.nc1_ls >> 16) as u8)?;            // write to NC2_LS as well
-    write(i2c, 35,  (s.nc1_ls >> 8 ) as u8)?;
-    write(i2c, 36,  (s.nc1_ls)       as u8)?;
-    write(i2c, 40,  (s.n2_hs  << 5 ) as u8 | (s.n2_ls  >> 16) as u8)?;
-    write(i2c, 41,  (s.n2_ls  >> 8 ) as u8)?;
-    write(i2c, 42,  (s.n2_ls)        as u8)?;
-    write(i2c, 43,  (s.n31    >> 16) as u8)?;
-    write(i2c, 44,  (s.n31    >> 8)  as u8)?;
-    write(i2c, 45,  (s.n31)          as u8)?;
-    write(i2c, 46,  (s.n32    >> 16) as u8)?;
-    write(i2c, 47,  (s.n32    >> 8)  as u8)?;
-    write(i2c, 48,  (s.n32)          as u8)?;
-    rmw(i2c, 137, |v| v | 0x01)?;                       // FASTLOCK=1
-    rmw(i2c, 136, |v| v | 0x40)?;                       // ICAL=1
-
-    if !has_xtal(i2c)? {
-        return Err("Si5324 misses XA/XB signal");
-    }
-    if !has_ckin(i2c, input)? {
-        return Err("Si5324 misses clock input signal");
-    }
-
-    monitor_lock(i2c, timer)?;
-    Ok(())
-}
-
-pub fn select_input(i2c: &mut I2c, input: Input, timer: &mut GlobalTimer) -> Result<()> {
-    let cksel_reg = match input {
-        Input::Ckin1 => 0b00,
-        Input::Ckin2 => 0b01,
-    };
-    rmw(i2c, 3,   |v| (v & 0x3f) | (cksel_reg << 6))?;
-    if !has_ckin(i2c, input)? {
-        return Err("Si5324 misses clock input signal");
-    }
-    monitor_lock(i2c, timer)?;
-    Ok(())
-}
-
-#[cfg(has_siphaser)]
-pub mod siphaser {
-    use super::*;
-    use crate::pl::csr;
-
-    pub fn select_recovered_clock(i2c: &mut I2c, rc: bool, timer: &mut GlobalTimer) -> Result<()> {
-        let val = read(i2c, 3)?;
-        write(i2c, 3,   (val & 0xdf) | (1 << 5))?;  // DHOLD=1
-        unsafe {
-            csr::siphaser::switch_clocks_write(if rc { 1 } else { 0 });
-        }
-        let val = read(i2c, 3)?;
-        write(i2c, 3,   (val & 0xdf) | (0 << 5))?;  // DHOLD=0
-        monitor_lock(i2c, timer)?;
-        Ok(())
-    }
-
-    fn phase_shift(direction: u8, timer: &mut GlobalTimer) {
-        unsafe {
-            csr::siphaser::phase_shift_write(direction);
-            while csr::siphaser::phase_shift_done_read() == 0 {}
-        }
-        // wait for the Si5324 loop to stabilize
-        timer.delay_us(500);
-    }
-
-    fn has_error(timer: &mut GlobalTimer) -> bool {
-        unsafe {
-            csr::siphaser::error_write(1);
-        }
-        timer.delay_us(5_000);
-        unsafe {
-            csr::siphaser::error_read() != 0
-        }
-    }
-
-    fn find_edge(target: bool, timer: &mut GlobalTimer) -> Result<u32> {
-        let mut nshifts = 0;
-
-        let mut previous = has_error(timer);
-        loop {
-            phase_shift(1, timer);
-            nshifts += 1;
-            let current = has_error(timer);
-            if previous != target && current == target {
-                return Ok(nshifts);
-            }
-            if nshifts > 5000 {
-                return Err("failed to find timing error edge");
-            }
-            previous = current;
-        }
-    }
-
-    pub fn calibrate_skew(timer: &mut GlobalTimer) -> Result<()> {
-        let jitter_margin = 32;
-        let lead = find_edge(false, timer)?;
-        for _ in 0..jitter_margin {
-            phase_shift(1, timer);
-        }
-        let width = find_edge(true, timer)? + jitter_margin;
-        // width is 360 degrees (one full rotation of the phase between s/h limits) minus jitter
-        info!("calibration successful, lead: {}, width: {} ({}deg)", lead, width, width*360/(56*8));
-
-        // Apply reverse phase shift for half the width to get into the
-        // middle of the working region.
-        for _ in 0..width/2 {
-            phase_shift(0, timer);
-        }
-
-        Ok(())
-    }
-}
--- a/src/libbuild_zynq/Cargo.toml
+++ b/src/libbuild_zynq/Cargo.toml
@ -1,8 +0,0 @@
-[package]
-authors = ["M-Labs"]
-name = "build_zynq"
-version = "0.0.0"
-
-[lib]
-name = "build_zynq"
-path = "lib.rs"
--- a/src/libbuild_zynq/lib.rs
+++ b/src/libbuild_zynq/lib.rs
@ -1,30 +0,0 @@
-use std::env;
-use std::fs::File;
-use std::io::{BufRead, BufReader, Write};
-use std::path::PathBuf;
-
-
-pub fn add_linker_script() {
-    // Put the linker script somewhere the linker can find it
-    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
-    File::create(out.join("link.x"))
-        .unwrap()
-        .write_all(include_bytes!("link.x"))
-        .unwrap();
-    println!("cargo:rustc-link-search={}", out.display());
-
-    // Only re-run the build script when link.x is changed,
-    // instead of when any part of the source code changes.
-    println!("cargo:rerun-if-changed=link.x");
-}
-
-pub fn cfg() {
-    // Handle rustc-cfg file
-    let cfg_path = "../../build/rustc-cfg";
-    println!("cargo:rerun-if-changed={}", cfg_path);
-
-    let f = BufReader::new(File::open(cfg_path).unwrap());
-    for line in f.lines() {
-        println!("cargo:rustc-cfg={}", line.unwrap());
-    }
-}
--- a/src/libc/build.rs
+++ b/src/libc/build.rs
@ -5,8 +5,6 @@ fn main() {

 mod libc {
    use std::path::Path;
-    use std::env;
-
    pub fn compile() {
        let cfg = &mut cc::Build::new();
        cfg.no_default_flags(true);
@ -18,9 +16,6 @@ mod libc {
        cfg.flag("-ffreestanding");
        cfg.flag("-fno-PIC");
        cfg.flag("-isystem../include");
-        if let Ok(extra_include) = env::var("CLANG_EXTRA_INCLUDE_DIR") {
-            cfg.flag(&("-isystem".to_owned() + &extra_include));
-        }
        cfg.flag("-fno-stack-protector");
        cfg.flag("--target=armv7-none-eabihf");
        cfg.flag("-O2");
@ -33,7 +28,9 @@ mod libc {
        cfg.define("_FORTIFY_SOURCE", Some("0"));

        let sources = vec![
-            "printf.c"
+            "printf.c",
+            "memcpy.c",
+            "fast_memcpy.S"
        ];

        let root = Path::new("./");
--- a/src/libc/src/fast_memcpy.S
+++ b/src/libc/src/fast_memcpy.S
@ -0,0 +1,620 @@
+/* Copyright (c) 2013, Linaro Limited
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+      * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+      * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+
+      * Neither the name of Linaro Limited nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+   This memcpy routine is optimised for Cortex-A15 cores and takes advantage
+   of VFP or NEON when built with the appropriate flags.
+
+   Assumptions:
+
+    ARMv6 (ARMv7-a if using Neon)
+    ARM state
+    Unaligned accesses
+    LDRD/STRD support unaligned word accesses
+
+   If compiled with GCC, this file should be enclosed within following
+   pre-processing check:
+   if defined (__ARM_ARCH_7A__) && defined (__ARM_FEATURE_UNALIGNED)
+
+ */
+	.syntax unified
+	/* This implementation requires ARM state.  */
+	.arm
+
+#ifdef __ARM_NEON__
+
+	.fpu	neon
+	.arch	armv7-a
+# define FRAME_SIZE	4
+# define USE_VFP
+# define USE_NEON
+
+#elif !defined (__SOFTFP__)
+
+	.arch	armv6
+	.fpu	vfpv2
+# define FRAME_SIZE	32
+# define USE_VFP
+
+#else
+	.arch	armv6
+# define FRAME_SIZE    32
+
+#endif
+
+/* Old versions of GAS incorrectly implement the NEON align semantics.  */
+#ifdef BROKEN_ASM_NEON_ALIGN
+#define ALIGN(addr, align) addr,:align
+#else
+#define ALIGN(addr, align) addr:align
+#endif
+
+#define PC_OFFSET	8	/* PC pipeline compensation.  */
+#define INSN_SIZE	4
+
+/* Call parameters.  */
+#define dstin	r0
+#define src	r1
+#define count	r2
+
+/* Locals.  */
+#define tmp1	r3
+#define dst	ip
+#define tmp2	r10
+
+#ifndef USE_NEON
+/* For bulk copies using GP registers.  */
+#define	A_l	r2		/* Call-clobbered.  */
+#define	A_h	r3		/* Call-clobbered.  */
+#define	B_l	r4
+#define	B_h	r5
+#define	C_l	r6
+#define	C_h	r7
+#define	D_l	r8
+#define	D_h	r9
+#endif
+
+/* Number of lines ahead to pre-fetch data.  If you change this the code
+   below will need adjustment to compensate.  */
+
+#define prefetch_lines	5
+
+#ifdef USE_VFP
+	.macro	cpy_line_vfp vreg, base
+	vstr	\vreg, [dst, #\base]
+	vldr	\vreg, [src, #\base]
+	vstr	d0, [dst, #\base + 8]
+	vldr	d0, [src, #\base + 8]
+	vstr	d1, [dst, #\base + 16]
+	vldr	d1, [src, #\base + 16]
+	vstr	d2, [dst, #\base + 24]
+	vldr	d2, [src, #\base + 24]
+	vstr	\vreg, [dst, #\base + 32]
+	vldr	\vreg, [src, #\base + prefetch_lines * 64 - 32]
+	vstr	d0, [dst, #\base + 40]
+	vldr	d0, [src, #\base + 40]
+	vstr	d1, [dst, #\base + 48]
+	vldr	d1, [src, #\base + 48]
+	vstr	d2, [dst, #\base + 56]
+	vldr	d2, [src, #\base + 56]
+	.endm
+
+	.macro	cpy_tail_vfp vreg, base
+	vstr	\vreg, [dst, #\base]
+	vldr	\vreg, [src, #\base]
+	vstr	d0, [dst, #\base + 8]
+	vldr	d0, [src, #\base + 8]
+	vstr	d1, [dst, #\base + 16]
+	vldr	d1, [src, #\base + 16]
+	vstr	d2, [dst, #\base + 24]
+	vldr	d2, [src, #\base + 24]
+	vstr	\vreg, [dst, #\base + 32]
+	vstr	d0, [dst, #\base + 40]
+	vldr	d0, [src, #\base + 40]
+	vstr	d1, [dst, #\base + 48]
+	vldr	d1, [src, #\base + 48]
+	vstr	d2, [dst, #\base + 56]
+	vldr	d2, [src, #\base + 56]
+	.endm
+#endif
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+def_fn fast_memcpy p2align=6
+
+	mov	dst, dstin	/* Preserve dstin, we need to return it.  */
+	cmp	count, #64
+	bge	.Lcpy_not_short
+	/* Deal with small copies quickly by dropping straight into the
+	   exit block.  */
+
+.Ltail63unaligned:
+#ifdef USE_NEON
+	and	tmp1, count, #0x38
+	rsb	tmp1, tmp1, #(56 - PC_OFFSET + INSN_SIZE)
+	add	pc, pc, tmp1
+	vld1.8	{d0}, [src]!	/* 14 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 12 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 10 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 8 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 6 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 4 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 2 words to go.  */
+	vst1.8	{d0}, [dst]!
+
+	tst	count, #4
+	ldrne	tmp1, [src], #4
+	strne	tmp1, [dst], #4
+#else
+	/* Copy up to 15 full words of data.  May not be aligned.  */
+	/* Cannot use VFP for unaligned data.  */
+	and	tmp1, count, #0x3c
+	add	dst, dst, tmp1
+	add	src, src, tmp1
+	rsb	tmp1, tmp1, #(60 - PC_OFFSET/2 + INSN_SIZE/2)
+	/* Jump directly into the sequence below at the correct offset.  */
+	add	pc, pc, tmp1, lsl #1
+
+	ldr	tmp1, [src, #-60]	/* 15 words to go.  */
+	str	tmp1, [dst, #-60]
+
+	ldr	tmp1, [src, #-56]	/* 14 words to go.  */
+	str	tmp1, [dst, #-56]
+	ldr	tmp1, [src, #-52]
+	str	tmp1, [dst, #-52]
+
+	ldr	tmp1, [src, #-48]	/* 12 words to go.  */
+	str	tmp1, [dst, #-48]
+	ldr	tmp1, [src, #-44]
+	str	tmp1, [dst, #-44]
+
+	ldr	tmp1, [src, #-40]	/* 10 words to go.  */
+	str	tmp1, [dst, #-40]
+	ldr	tmp1, [src, #-36]
+	str	tmp1, [dst, #-36]
+
+	ldr	tmp1, [src, #-32]	/* 8 words to go.  */
+	str	tmp1, [dst, #-32]
+	ldr	tmp1, [src, #-28]
+	str	tmp1, [dst, #-28]
+
+	ldr	tmp1, [src, #-24]	/* 6 words to go.  */
+	str	tmp1, [dst, #-24]
+	ldr	tmp1, [src, #-20]
+	str	tmp1, [dst, #-20]
+
+	ldr	tmp1, [src, #-16]	/* 4 words to go.  */
+	str	tmp1, [dst, #-16]
+	ldr	tmp1, [src, #-12]
+	str	tmp1, [dst, #-12]
+
+	ldr	tmp1, [src, #-8]	/* 2 words to go.  */
+	str	tmp1, [dst, #-8]
+	ldr	tmp1, [src, #-4]
+	str	tmp1, [dst, #-4]
+#endif
+
+	lsls	count, count, #31
+	ldrhcs	tmp1, [src], #2
+	ldrbne	src, [src]		/* Src is dead, use as a scratch.  */
+	strhcs	tmp1, [dst], #2
+	strbne	src, [dst]
+	bx	lr
+
+.Lcpy_not_short:
+	/* At least 64 bytes to copy, but don't know the alignment yet.  */
+	str	tmp2, [sp, #-FRAME_SIZE]!
+	and	tmp2, src, #7
+	and	tmp1, dst, #7
+	cmp	tmp1, tmp2
+	bne	.Lcpy_notaligned
+
+#ifdef USE_VFP
+	/* Magic dust alert!  Force VFP on Cortex-A9.  Experiments show
+	   that the FP pipeline is much better at streaming loads and
+	   stores.  This is outside the critical loop.  */
+	vmov.f32	s0, s0
+#endif
+
+	/* SRC and DST have the same mutual 32-bit alignment, but we may
+	   still need to pre-copy some bytes to get to natural alignment.
+	   We bring DST into full 64-bit alignment.  */
+	lsls	tmp2, dst, #29
+	beq	1f
+	rsbs	tmp2, tmp2, #0
+	sub	count, count, tmp2, lsr #29
+	ldrmi	tmp1, [src], #4
+	strmi	tmp1, [dst], #4
+	lsls	tmp2, tmp2, #2
+	ldrhcs	tmp1, [src], #2
+	ldrbne	tmp2, [src], #1
+	strhcs	tmp1, [dst], #2
+	strbne	tmp2, [dst], #1
+
+1:
+	subs	tmp2, count, #64	/* Use tmp2 for count.  */
+	blt	.Ltail63aligned
+
+	cmp	tmp2, #512
+	bge	.Lcpy_body_long
+
+.Lcpy_body_medium:			/* Count in tmp2.  */
+#ifdef USE_VFP
+1:
+	vldr	d0, [src, #0]
+	subs	tmp2, tmp2, #64
+	vldr	d1, [src, #8]
+	vstr	d0, [dst, #0]
+	vldr	d0, [src, #16]
+	vstr	d1, [dst, #8]
+	vldr	d1, [src, #24]
+	vstr	d0, [dst, #16]
+	vldr	d0, [src, #32]
+	vstr	d1, [dst, #24]
+	vldr	d1, [src, #40]
+	vstr	d0, [dst, #32]
+	vldr	d0, [src, #48]
+	vstr	d1, [dst, #40]
+	vldr	d1, [src, #56]
+	vstr	d0, [dst, #48]
+	add	src, src, #64
+	vstr	d1, [dst, #56]
+	add	dst, dst, #64
+	bge	1b
+	tst	tmp2, #0x3f
+	beq	.Ldone
+
+.Ltail63aligned:			/* Count in tmp2.  */
+	and	tmp1, tmp2, #0x38
+	add	dst, dst, tmp1
+	add	src, src, tmp1
+	rsb	tmp1, tmp1, #(56 - PC_OFFSET + INSN_SIZE)
+	add	pc, pc, tmp1
+
+	vldr	d0, [src, #-56]	/* 14 words to go.  */
+	vstr	d0, [dst, #-56]
+	vldr	d0, [src, #-48]	/* 12 words to go.  */
+	vstr	d0, [dst, #-48]
+	vldr	d0, [src, #-40]	/* 10 words to go.  */
+	vstr	d0, [dst, #-40]
+	vldr	d0, [src, #-32]	/* 8 words to go.  */
+	vstr	d0, [dst, #-32]
+	vldr	d0, [src, #-24]	/* 6 words to go.  */
+	vstr	d0, [dst, #-24]
+	vldr	d0, [src, #-16]	/* 4 words to go.  */
+	vstr	d0, [dst, #-16]
+	vldr	d0, [src, #-8]	/* 2 words to go.  */
+	vstr	d0, [dst, #-8]
+#else
+	sub	src, src, #8
+	sub	dst, dst, #8
+1:
+	ldrd	A_l, A_h, [src, #8]
+	strd	A_l, A_h, [dst, #8]
+	ldrd	A_l, A_h, [src, #16]
+	strd	A_l, A_h, [dst, #16]
+	ldrd	A_l, A_h, [src, #24]
+	strd	A_l, A_h, [dst, #24]
+	ldrd	A_l, A_h, [src, #32]
+	strd	A_l, A_h, [dst, #32]
+	ldrd	A_l, A_h, [src, #40]
+	strd	A_l, A_h, [dst, #40]
+	ldrd	A_l, A_h, [src, #48]
+	strd	A_l, A_h, [dst, #48]
+	ldrd	A_l, A_h, [src, #56]
+	strd	A_l, A_h, [dst, #56]
+	ldrd	A_l, A_h, [src, #64]!
+	strd	A_l, A_h, [dst, #64]!
+	subs	tmp2, tmp2, #64
+	bge	1b
+	tst	tmp2, #0x3f
+	bne	1f
+	ldr	tmp2,[sp], #FRAME_SIZE
+	bx	lr
+1:
+	add	src, src, #8
+	add	dst, dst, #8
+
+.Ltail63aligned:			/* Count in tmp2.  */
+	/* Copy up to 7 d-words of data.  Similar to Ltail63unaligned, but
+	   we know that the src and dest are 32-bit aligned so we can use
+	   LDRD/STRD to improve efficiency.  */
+	/* TMP2 is now negative, but we don't care about that.  The bottom
+	   six bits still tell us how many bytes are left to copy.  */
+
+	and	tmp1, tmp2, #0x38
+	add	dst, dst, tmp1
+	add	src, src, tmp1
+	rsb	tmp1, tmp1, #(56 - PC_OFFSET + INSN_SIZE)
+	add	pc, pc, tmp1
+	ldrd	A_l, A_h, [src, #-56]	/* 14 words to go.  */
+	strd	A_l, A_h, [dst, #-56]
+	ldrd	A_l, A_h, [src, #-48]	/* 12 words to go.  */
+	strd	A_l, A_h, [dst, #-48]
+	ldrd	A_l, A_h, [src, #-40]	/* 10 words to go.  */
+	strd	A_l, A_h, [dst, #-40]
+	ldrd	A_l, A_h, [src, #-32]	/* 8 words to go.  */
+	strd	A_l, A_h, [dst, #-32]
+	ldrd	A_l, A_h, [src, #-24]	/* 6 words to go.  */
+	strd	A_l, A_h, [dst, #-24]
+	ldrd	A_l, A_h, [src, #-16]	/* 4 words to go.  */
+	strd	A_l, A_h, [dst, #-16]
+	ldrd	A_l, A_h, [src, #-8]	/* 2 words to go.  */
+	strd	A_l, A_h, [dst, #-8]
+
+#endif
+	tst	tmp2, #4
+	ldrne	tmp1, [src], #4
+	strne	tmp1, [dst], #4
+	lsls	tmp2, tmp2, #31		/* Count (tmp2) now dead. */
+	ldrhcs	tmp1, [src], #2
+	ldrbne	tmp2, [src]
+	strhcs	tmp1, [dst], #2
+	strbne	tmp2, [dst]
+
+.Ldone:
+	ldr	tmp2, [sp], #FRAME_SIZE
+	bx	lr
+
+.Lcpy_body_long:			/* Count in tmp2.  */
+
+	/* Long copy.  We know that there's at least (prefetch_lines * 64)
+	   bytes to go.  */
+#ifdef USE_VFP
+	/* Don't use PLD.  Instead, read some data in advance of the current
+	   copy position into a register.  This should act like a PLD
+	   operation but we won't have to repeat the transfer.  */
+
+	vldr	d3, [src, #0]
+	vldr	d4, [src, #64]
+	vldr	d5, [src, #128]
+	vldr	d6, [src, #192]
+	vldr	d7, [src, #256]
+
+	vldr	d0, [src, #8]
+	vldr	d1, [src, #16]
+	vldr	d2, [src, #24]
+	add	src, src, #32
+
+	subs	tmp2, tmp2, #prefetch_lines * 64 * 2
+	blt	2f
+1:
+	cpy_line_vfp	d3, 0
+	cpy_line_vfp	d4, 64
+	cpy_line_vfp	d5, 128
+	add	dst, dst, #3 * 64
+	add	src, src, #3 * 64
+	cpy_line_vfp	d6, 0
+	cpy_line_vfp	d7, 64
+	add	dst, dst, #2 * 64
+	add	src, src, #2 * 64
+	subs	tmp2, tmp2, #prefetch_lines * 64
+	bge	1b
+
+2:
+	cpy_tail_vfp	d3, 0
+	cpy_tail_vfp	d4, 64
+	cpy_tail_vfp	d5, 128
+	add	src, src, #3 * 64
+	add	dst, dst, #3 * 64
+	cpy_tail_vfp	d6, 0
+	vstr	d7, [dst, #64]
+	vldr	d7, [src, #64]
+	vstr	d0, [dst, #64 + 8]
+	vldr	d0, [src, #64 + 8]
+	vstr	d1, [dst, #64 + 16]
+	vldr	d1, [src, #64 + 16]
+	vstr	d2, [dst, #64 + 24]
+	vldr	d2, [src, #64 + 24]
+	vstr	d7, [dst, #64 + 32]
+	add	src, src, #96
+	vstr	d0, [dst, #64 + 40]
+	vstr	d1, [dst, #64 + 48]
+	vstr	d2, [dst, #64 + 56]
+	add	dst, dst, #128
+	add	tmp2, tmp2, #prefetch_lines * 64
+	b	.Lcpy_body_medium
+#else
+	/* Long copy.  Use an SMS style loop to maximize the I/O
+	   bandwidth of the core.  We don't have enough spare registers
+	   to synthesise prefetching, so use PLD operations.  */
+	/* Pre-bias src and dst.  */
+	sub	src, src, #8
+	sub	dst, dst, #8
+	pld	[src, #8]
+	pld	[src, #72]
+	subs	tmp2, tmp2, #64
+	pld	[src, #136]
+	ldrd	A_l, A_h, [src, #8]
+	strd	B_l, B_h, [sp, #8]
+	ldrd	B_l, B_h, [src, #16]
+	strd	C_l, C_h, [sp, #16]
+	ldrd	C_l, C_h, [src, #24]
+	strd	D_l, D_h, [sp, #24]
+	pld	[src, #200]
+	ldrd	D_l, D_h, [src, #32]!
+	b	1f
+	.p2align	6
+2:
+	pld	[src, #232]
+	strd	A_l, A_h, [dst, #40]
+	ldrd	A_l, A_h, [src, #40]
+	strd	B_l, B_h, [dst, #48]
+	ldrd	B_l, B_h, [src, #48]
+	strd	C_l, C_h, [dst, #56]
+	ldrd	C_l, C_h, [src, #56]
+	strd	D_l, D_h, [dst, #64]!
+	ldrd	D_l, D_h, [src, #64]!
+	subs	tmp2, tmp2, #64
+1:
+	strd	A_l, A_h, [dst, #8]
+	ldrd	A_l, A_h, [src, #8]
+	strd	B_l, B_h, [dst, #16]
+	ldrd	B_l, B_h, [src, #16]
+	strd	C_l, C_h, [dst, #24]
+	ldrd	C_l, C_h, [src, #24]
+	strd	D_l, D_h, [dst, #32]
+	ldrd	D_l, D_h, [src, #32]
+	bcs	2b
+	/* Save the remaining bytes and restore the callee-saved regs.  */
+	strd	A_l, A_h, [dst, #40]
+	add	src, src, #40
+	strd	B_l, B_h, [dst, #48]
+	ldrd	B_l, B_h, [sp, #8]
+	strd	C_l, C_h, [dst, #56]
+	ldrd	C_l, C_h, [sp, #16]
+	strd	D_l, D_h, [dst, #64]
+	ldrd	D_l, D_h, [sp, #24]
+	add	dst, dst, #72
+	tst	tmp2, #0x3f
+	bne	.Ltail63aligned
+	ldr	tmp2, [sp], #FRAME_SIZE
+	bx	lr
+#endif
+
+.Lcpy_notaligned:
+	pld	[src]
+	pld	[src, #64]
+	/* There's at least 64 bytes to copy, but there is no mutual
+	   alignment.  */
+	/* Bring DST to 64-bit alignment.  */
+	lsls	tmp2, dst, #29
+	pld	[src, #(2 * 64)]
+	beq	1f
+	rsbs	tmp2, tmp2, #0
+	sub	count, count, tmp2, lsr #29
+	ldrmi	tmp1, [src], #4
+	strmi	tmp1, [dst], #4
+	lsls	tmp2, tmp2, #2
+	ldrbne	tmp1, [src], #1
+	ldrhcs	tmp2, [src], #2
+	strbne	tmp1, [dst], #1
+	strhcs	tmp2, [dst], #2
+1:
+	pld	[src, #(3 * 64)]
+	subs	count, count, #64
+	ldrmi	tmp2, [sp], #FRAME_SIZE
+	bmi	.Ltail63unaligned
+	pld	[src, #(4 * 64)]
+
+#ifdef USE_NEON
+	vld1.8	{d0-d3}, [src]!
+	vld1.8	{d4-d7}, [src]!
+	subs	count, count, #64
+	bmi	2f
+1:
+	pld	[src, #(4 * 64)]
+	vst1.8	{d0-d3}, [ALIGN (dst, 64)]!
+	vld1.8	{d0-d3}, [src]!
+	vst1.8	{d4-d7}, [ALIGN (dst, 64)]!
+	vld1.8	{d4-d7}, [src]!
+	subs	count, count, #64
+	bpl	1b
+2:
+	vst1.8	{d0-d3}, [ALIGN (dst, 64)]!
+	vst1.8	{d4-d7}, [ALIGN (dst, 64)]!
+	ands	count, count, #0x3f
+#else
+	/* Use an SMS style loop to maximize the I/O bandwidth.  */
+	sub	src, src, #4
+	sub	dst, dst, #8
+	subs	tmp2, count, #64	/* Use tmp2 for count.  */
+	ldr	A_l, [src, #4]
+	ldr	A_h, [src, #8]
+	strd	B_l, B_h, [sp, #8]
+	ldr	B_l, [src, #12]
+	ldr	B_h, [src, #16]
+	strd	C_l, C_h, [sp, #16]
+	ldr	C_l, [src, #20]
+	ldr	C_h, [src, #24]
+	strd	D_l, D_h, [sp, #24]
+	ldr	D_l, [src, #28]
+	ldr	D_h, [src, #32]!
+	b	1f
+	.p2align	6
+2:
+	pld	[src, #(5 * 64) - (32 - 4)]
+	strd	A_l, A_h, [dst, #40]
+	ldr	A_l, [src, #36]
+	ldr	A_h, [src, #40]
+	strd	B_l, B_h, [dst, #48]
+	ldr	B_l, [src, #44]
+	ldr	B_h, [src, #48]
+	strd	C_l, C_h, [dst, #56]
+	ldr	C_l, [src, #52]
+	ldr	C_h, [src, #56]
+	strd	D_l, D_h, [dst, #64]!
+	ldr	D_l, [src, #60]
+	ldr	D_h, [src, #64]!
+	subs	tmp2, tmp2, #64
+1:
+	strd	A_l, A_h, [dst, #8]
+	ldr	A_l, [src, #4]
+	ldr	A_h, [src, #8]
+	strd	B_l, B_h, [dst, #16]
+	ldr	B_l, [src, #12]
+	ldr	B_h, [src, #16]
+	strd	C_l, C_h, [dst, #24]
+	ldr	C_l, [src, #20]
+	ldr	C_h, [src, #24]
+	strd	D_l, D_h, [dst, #32]
+	ldr	D_l, [src, #28]
+	ldr	D_h, [src, #32]
+	bcs	2b
+
+	/* Save the remaining bytes and restore the callee-saved regs.  */
+	strd	A_l, A_h, [dst, #40]
+	add	src, src, #36
+	strd	B_l, B_h, [dst, #48]
+	ldrd	B_l, B_h, [sp, #8]
+	strd	C_l, C_h, [dst, #56]
+	ldrd	C_l, C_h, [sp, #16]
+	strd	D_l, D_h, [dst, #64]
+	ldrd	D_l, D_h, [sp, #24]
+	add	dst, dst, #72
+	ands	count, tmp2, #0x3f
+#endif
+	ldr	tmp2, [sp], #FRAME_SIZE
+	bne	.Ltail63unaligned
+	bx	lr
+
+	.size	memcpy, . - memcpy
+
--- a/src/libc/src/memcpy.c
+++ b/src/libc/src/memcpy.c
@ -0,0 +1,56 @@
+
+/*
+ * Copyright (c) 2014 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stddef.h>
+
+/* According to the Run-time ABI for the ARM Architecture.  This
+   function is allowed to corrupt only the integer core register
+   permitted to be corrupted by the [AAPCS] (r0-r3, ip, lr, and
+   CPSR).
+   The FP registers are used in memcpy for target __ARM_ARCH_7A.
+   Therefore, we can't just simply use alias to support the function
+   aeabi_memcpy for target __ARM_ARCH_7A.  Instead, we choose the
+   previous versions of memcpy to suppport it as an alternative.  */
+
+/* NOTE: This ifdef MUST match the one in aeabi_memcpy-armv7a.S.  */
+/* Support the alias for the __aeabi_memcpy which may
+   assume memory alignment.  */
+void __aeabi_memcpy4 (void *dest, const void *source, size_t n)
+	__attribute__((alias ("__aeabi_memcpy")));
+
+void __aeabi_memcpy8 (void *dest, const void *source, size_t n)
+	__attribute__((alias ("__aeabi_memcpy")));
+
+/* Support the routine __aeabi_memcpy.  Can't alias to memcpy
+   because it's not defined in the same translation unit.  */
+void __aeabi_memcpy (void *dest, const void *source, size_t n)
+{
+  extern void fast_memcpy (void *dest, const void *source, size_t n);
+  fast_memcpy (dest, source, n);
+}
--- a/src/libconfig/Cargo.toml
+++ b/src/libconfig/Cargo.toml
@ -0,0 +1,15 @@
+[package]
+name = "libconfig"
+version = "0.1.0"
+authors = ["M-Labs"]
+edition = "2018"
+
+[dependencies]
+libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+core_io = { version = "0.1", features = ["collections"] }
+fatfs = { version = "0.3", features = ["core_io"], default-features = false }
+log = "0.4"
+
+[features]
+ipv6 = []
+
--- a/src/libconfig/src/bootgen.rs
+++ b/src/libconfig/src/bootgen.rs
@ -0,0 +1,181 @@
+use alloc::vec::Vec;
+use core_io::{Error, Read, Seek, SeekFrom};
+use libboard_zynq::devc;
+use log::debug;
+
+#[derive(Debug)]
+pub enum BootgenLoadingError {
+    InvalidBootImageHeader,
+    MissingPartition,
+    EncryptedBitstream,
+    IoError(Error),
+    DevcError(devc::DevcError),
+}
+
+impl From<Error> for BootgenLoadingError {
+    fn from(error: Error) -> Self {
+        BootgenLoadingError::IoError(error)
+    }
+}
+
+impl From<devc::DevcError> for BootgenLoadingError {
+    fn from(error: devc::DevcError) -> Self {
+        BootgenLoadingError::DevcError(error)
+    }
+}
+
+impl core::fmt::Display for BootgenLoadingError {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        use BootgenLoadingError::*;
+        match self {
+            InvalidBootImageHeader => write!(
+                f,
+                "Invalid boot image header. Check if the file is correct."
+            ),
+            MissingPartition => write!(f, "Partition not found. Check your compile configuration."),
+            EncryptedBitstream => write!(f, "Encrypted bitstream is not supported."),
+            IoError(e) => write!(f, "Error while reading: {}", e),
+            DevcError(e) => write!(f, "PCAP interface error: {}", e),
+        }
+    }
+}
+
+#[repr(C)]
+struct PartitionHeader {
+    pub encrypted_length: u32,
+    pub unencrypted_length: u32,
+    pub word_length: u32,
+    pub dest_load_addr: u32,
+    pub dest_exec_addr: u32,
+    pub data_offset: u32,
+    pub attribute_bits: u32,
+    pub section_count: u32,
+    pub checksum_offset: u32,
+    pub header_offset: u32,
+    pub cert_offset: u32,
+    pub reserved: [u32; 4],
+    pub checksum: u32,
+}
+
+/// Read a u32 word from the reader.
+fn read_u32<Reader: Read>(reader: &mut Reader) -> Result<u32, BootgenLoadingError> {
+    let mut buffer: [u8; 4] = [0; 4];
+    reader.read_exact(&mut buffer)?;
+    let mut result: u32 = 0;
+    for i in 0..4 {
+        result |= (buffer[i] as u32) << (i * 8);
+    }
+    Ok(result)
+}
+
+/// Load PL partition header.
+fn load_pl_header<File: Read + Seek>(
+    file: &mut File,
+) -> Result<Option<PartitionHeader>, BootgenLoadingError> {
+    let mut buffer: [u8; 0x40] = [0; 0x40];
+    file.read_exact(&mut buffer)?;
+    let header = unsafe { core::mem::transmute::<_, PartitionHeader>(buffer) };
+    if header.attribute_bits & (2 << 4) != 0 {
+        Ok(Some(header))
+    } else {
+        Ok(None)
+    }
+}
+
+fn load_ps_header<File: Read + Seek>(
+    file: &mut File,
+) -> Result<Option<PartitionHeader>, BootgenLoadingError> {
+    let mut buffer: [u8; 0x40] = [0; 0x40];
+    file.read_exact(&mut buffer)?;
+    let header = unsafe { core::mem::transmute::<_, PartitionHeader>(buffer) };
+    if header.attribute_bits & (1 << 4) != 0 {
+        Ok(Some(header))
+    } else {
+        Ok(None)
+    }
+}
+
+/// Locate the partition from the image, and return the size (in bytes) of the partition if successful.
+/// This function would seek the file to the location of the partition.
+fn locate<
+    File: Read + Seek,
+    F: Fn(&mut File) -> Result<Option<PartitionHeader>, BootgenLoadingError>,
+>(
+    file: &mut File,
+    f: F,
+) -> Result<usize, BootgenLoadingError> {
+    file.seek(SeekFrom::Start(0))?;
+    const BOOT_HEADER_SIGN: u32 = 0x584C4E58;
+    // read boot header signature
+    file.seek(SeekFrom::Start(0x24))?;
+    if read_u32(file)? != BOOT_HEADER_SIGN {
+        return Err(BootgenLoadingError::InvalidBootImageHeader);
+    }
+    // find fsbl offset
+    file.seek(SeekFrom::Start(0x30))?;
+    // the length is in bytes, we have to convert it to words to compare with the partition offset
+    // later
+    let fsbl = read_u32(file)? / 4;
+    // read partition header offset
+    file.seek(SeekFrom::Start(0x9C))?;
+    let ptr = read_u32(file)?;
+    debug!("Partition header pointer = {:0X}", ptr);
+    file.seek(SeekFrom::Start(ptr as u64))?;
+
+    // at most 3 partition headers
+    for _ in 0..3 {
+        if let Some(header) = f(file)? {
+            let encrypted_length = header.encrypted_length;
+            let unencrypted_length = header.unencrypted_length;
+            debug!("Unencrypted length = {:0X}", unencrypted_length);
+            if encrypted_length != unencrypted_length {
+                return Err(BootgenLoadingError::EncryptedBitstream);
+            }
+
+            let start_addr = header.data_offset;
+            // skip fsbl
+            if start_addr == fsbl {
+                continue;
+            }
+            debug!("Partition start address: {:0X}", start_addr);
+            file.seek(SeekFrom::Start(start_addr as u64 * 4))?;
+
+            return Ok(unencrypted_length as usize * 4);
+        }
+    }
+    Err(BootgenLoadingError::MissingPartition)
+}
+
+/// Load bitstream from bootgen file.
+/// This function parses the file, locate the bitstream and load it through the PCAP driver.
+/// It requires a large buffer, please enable the DDR RAM before using it.
+pub fn load_bitstream<File: Read + Seek>(file: &mut File) -> Result<(), BootgenLoadingError> {
+    let size = locate(file, load_pl_header)?;
+    unsafe {
+        // align to 64 bytes
+        let ptr = alloc::alloc::alloc(alloc::alloc::Layout::from_size_align(size, 64).unwrap());
+        let buffer = core::slice::from_raw_parts_mut(ptr, size);
+        file.read_exact(buffer).map_err(|e| {
+            core::ptr::drop_in_place(ptr);
+            e
+        })?;
+        let mut devcfg = devc::DevC::new();
+        devcfg.enable();
+        devcfg.program(&buffer).map_err(|e| {
+            core::ptr::drop_in_place(ptr);
+            e
+        })?;
+        core::ptr::drop_in_place(ptr);
+        Ok(())
+    }
+}
+
+pub fn get_runtime<File: Read + Seek>(file: &mut File) -> Result<Vec<u8>, BootgenLoadingError> {
+    let size = locate(file, load_ps_header)?;
+    let mut buffer = Vec::with_capacity(size);
+    unsafe {
+        buffer.set_len(size);
+    }
+    file.read_exact(&mut buffer)?;
+    Ok(buffer)
+}
--- a/src/libconfig/src/lib.rs
+++ b/src/libconfig/src/lib.rs
@ -0,0 +1,115 @@
+#![no_std]
+extern crate alloc;
+
+use core::fmt;
+use alloc::{string::FromUtf8Error, string::String, vec::Vec, rc::Rc};
+use core_io::{self as io, BufRead, BufReader, Read};
+use libboard_zynq::sdio;
+
+pub mod sd_reader;
+pub mod net_settings;
+pub mod bootgen;
+
+#[derive(Debug)]
+pub enum Error<'a> {
+    SdError(sdio::sd_card::CardInitializationError),
+    IoError(io::Error),
+    Utf8Error(FromUtf8Error),
+    KeyNotFoundError(&'a str),
+    NoConfig,
+}
+
+pub type Result<'a, T> = core::result::Result<T, Error<'a>>;
+
+impl<'a> fmt::Display for Error<'a> {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match self {
+            Error::SdError(error) => write!(f, "SD error: {}", error),
+            Error::IoError(error) => write!(f, "I/O error: {}", error),
+            Error::Utf8Error(error) => write!(f, "UTF-8 error: {}", error),
+            Error::KeyNotFoundError(name) => write!(f, "Configuration key `{}` not found", name),
+            Error::NoConfig => write!(f, "Configuration not present"),
+        }
+    }
+}
+
+impl<'a> From<sdio::sd_card::CardInitializationError> for Error<'a> {
+    fn from(error: sdio::sd_card::CardInitializationError) -> Self {
+        Error::SdError(error)
+    }
+}
+
+impl<'a> From<io::Error> for Error<'a> {
+    fn from(error: io::Error) -> Self {
+        Error::IoError(error)
+    }
+}
+
+impl<'a> From<FromUtf8Error> for Error<'a> {
+    fn from(error: FromUtf8Error) -> Self {
+        Error::Utf8Error(error)
+    }
+}
+
+fn parse_config<'a>(
+    key: &'a str,
+    buffer: &mut Vec<u8>,
+    file: fatfs::File<sd_reader::SdReader>,
+) -> Result<'a, ()> {
+    let prefix = [key, "="].concat();
+    for line in BufReader::new(file).lines() {
+        let line = line?;
+        if line.starts_with(&prefix) {
+            buffer.extend(line[prefix.len()..].as_bytes());
+            return Ok(());
+        }
+    }
+    Err(Error::KeyNotFoundError(key))
+}
+
+pub struct Config {
+    fs: Option<Rc<fatfs::FileSystem<sd_reader::SdReader>>>,
+}
+
+impl Config {
+    pub fn new() -> Result<'static, Self> {
+        let sdio = sdio::Sdio::sdio0(true);
+        if !sdio.is_card_inserted() {
+            Err(sdio::sd_card::CardInitializationError::NoCardInserted)?;
+        }
+        let sd = sdio::sd_card::SdCard::from_sdio(sdio)?;
+        let reader = sd_reader::SdReader::new(sd);
+
+        let fs = reader.mount_fatfs(sd_reader::PartitionEntry::Entry1)?;
+        Ok(Config { fs: Some(Rc::new(fs)) })
+    }
+
+    pub fn from_fs(fs: Option<Rc<fatfs::FileSystem<sd_reader::SdReader>>>) -> Self {
+        Config { fs }
+    }
+
+    pub fn new_dummy() -> Self {
+        Config { fs: None }
+    }
+
+    pub fn read<'b>(&self, key: &'b str) -> Result<'b, Vec<u8>> {
+        if let Some(fs) = &self.fs {
+            let root_dir = fs.root_dir();
+            let mut buffer: Vec<u8> = Vec::new();
+            match root_dir.open_file(&["/CONFIG/", key, ".BIN"].concat()) {
+                Ok(mut f) => f.read_to_end(&mut buffer).map(|_| ())?,
+                Err(_) => match root_dir.open_file("/CONFIG.TXT") {
+                    Ok(f) => parse_config(key, &mut buffer, f)?,
+                    Err(_) => return Err(Error::KeyNotFoundError(key)),
+                },
+            };
+            Ok(buffer)
+        } else {
+            Err(Error::NoConfig)
+        }
+    }
+
+    pub fn read_str<'b>(&self, key: &'b str) -> Result<'b, String> {
+        Ok(String::from_utf8(self.read(key)?)?)
+    }
+}
--- a/src/libconfig/src/net_settings.rs
+++ b/src/libconfig/src/net_settings.rs
@ -0,0 +1,62 @@
+use core::fmt;
+
+use libboard_zynq::smoltcp::wire::{EthernetAddress, IpAddress};
+
+use super::Config;
+
+pub struct NetAddresses {
+    pub hardware_addr: EthernetAddress,
+    pub ipv4_addr: IpAddress,
+    #[cfg(feature = "ipv6")]
+    pub ipv6_ll_addr: IpAddress,
+    #[cfg(feature = "ipv6")]
+    pub ipv6_addr: Option<IpAddress>
+}
+
+impl fmt::Display for NetAddresses {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        write!(f, "MAC={} IPv4={} ",
+            self.hardware_addr, self.ipv4_addr)?;
+
+        #[cfg(feature = "ipv6")]
+        {
+            write!(f, "IPv6-LL={}", self.ipv6_ll_addr)?;
+            match self.ipv6_addr {
+                Some(addr) => write!(f, " {}", addr)?,
+                None => write!(f, " IPv6: no configured address")?
+            }
+        }
+        Ok(())
+    }
+}
+
+pub fn get_adresses(cfg: &Config) -> NetAddresses {
+    let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x52]);
+    let mut ipv4_addr = IpAddress::v4(192, 168, 1, 52);
+
+    if let Ok(Ok(addr)) = cfg.read_str("mac").map(|s| s.parse()) {
+        hardware_addr = addr;
+    }
+    if let Ok(Ok(addr)) = cfg.read_str("ip").map(|s| s.parse()) {
+        ipv4_addr = addr;
+    }
+    #[cfg(feature = "ipv6")]
+    let ipv6_addr = cfg.read_str("ipv6").ok().and_then(|s| s.parse().ok());
+
+    #[cfg(feature = "ipv6")]
+    let ipv6_ll_addr = IpAddress::v6(
+        0xfe80, 0x0000, 0x0000, 0x0000,
+        (((hardware_addr.0[0] ^ 0x02) as u16) << 8) | (hardware_addr.0[1] as u16),
+        ((hardware_addr.0[2] as u16) << 8) | 0x00ff,
+        0xfe00 | (hardware_addr.0[3] as u16),
+        ((hardware_addr.0[4] as u16) << 8) | (hardware_addr.0[5] as u16));
+
+    NetAddresses {
+        hardware_addr,
+        ipv4_addr,
+        #[cfg(feature = "ipv6")]
+        ipv6_ll_addr,
+        #[cfg(feature = "ipv6")]
+        ipv6_addr
+    }
+}
--- a/src/libconfig/src/sd_reader.rs
+++ b/src/libconfig/src/sd_reader.rs
@ -0,0 +1,303 @@
+use core_io::{BufRead, Error, ErrorKind, Read, Result as IoResult, Seek, SeekFrom, Write};
+use fatfs;
+use libboard_zynq::sdio::{sd_card::SdCard, CmdTransferError};
+use log::debug;
+use alloc::vec::Vec;
+
+const MBR_SIGNATURE: [u8; 2] = [0x55, 0xAA];
+const PARTID_FAT12: u8 = 0x01;
+const PARTID_FAT16_LESS32M: u8 = 0x04;
+const PARTID_FAT16: u8 = 0x06;
+const PARTID_FAT32: u8 = 0x0B;
+const PARTID_FAT32_LBA: u8 = 0x0C;
+
+fn cmd_error_to_io_error(_: CmdTransferError) -> Error {
+    Error::new(ErrorKind::Other, "Command transfer error")
+}
+
+const BLOCK_SIZE: usize = 512;
+
+/// SdReader struct implementing `Read + BufRead + Write + Seek` traits for `core_io`.
+/// Used as an adaptor for fatfs crate, but could be used directly for raw data access.
+///
+/// Implementation: all read/writes would be split into unaligned and block-aligned parts,
+/// unaligned read/writes would do a buffered read/write using a block-sized internal buffer,
+/// while aligned transactions would be sent to the SD card directly for performance reason.
+pub struct SdReader {
+    /// Internal SdCard handle.
+    sd: SdCard,
+    /// Read buffer with the size of 1 block.
+    buffer: Vec<u8>,
+    /// Address for the next byte.
+    byte_addr: u32,
+    /// Internal index for the next byte.
+    /// Normally in range `[0, BLOCK_SIZE - 1]`.
+    ///
+    /// `index = BLOCK_SIZE` means that the `buffer` is invalid for the current `byte_addr`,
+    /// the next `fill_buf` call would fill the buffer.
+    index: usize,
+    /// Dirty flag indicating the content has to be flushed.
+    dirty: bool,
+    /// Base offset for translation from logical address to physical address.
+    offset: u32,
+}
+
+#[derive(Copy, Clone)]
+#[allow(unused)]
+// Partition entry enum, normally we would use entry1.
+pub enum PartitionEntry {
+    Entry1 = 0x1BE,
+    Entry2 = 0x1CE,
+    Entry3 = 0x1DE,
+    Entry4 = 0x1EE,
+}
+
+impl SdReader {
+    /// Create SdReader from SdCard
+    pub fn new(sd: SdCard) -> SdReader {
+        let mut vec: Vec<u8> = Vec::with_capacity(BLOCK_SIZE);
+        unsafe {
+            vec.set_len(vec.capacity());
+        }
+        SdReader {
+            sd,
+            buffer: vec,
+            byte_addr: 0,
+            index: BLOCK_SIZE,
+            dirty: false,
+            offset: 0,
+        }
+    }
+
+    /// Internal read function for unaligned read.
+    /// The read must not cross block boundary.
+    fn read_unaligned(&mut self, buf: &mut [u8]) -> IoResult<usize> {
+        if buf.len() == 0 {
+            return Ok(0);
+        }
+        let filled_buffer = self.fill_buf()?;
+        for (dest, src) in buf.iter_mut().zip(filled_buffer.iter()) {
+            *dest = *src;
+        }
+        self.consume(buf.len());
+        Ok(buf.len())
+    }
+
+    /// Internal write function for unaligned write.
+    /// The write must not cross block boundary.
+    fn write_unaligned(&mut self, buf: &[u8]) -> IoResult<usize> {
+        if buf.len() == 0 {
+            return Ok(0);
+        }
+        // update buffer if needed, as we will flush the entire block later.
+        self.fill_buf()?;
+        self.dirty = true;
+        let dest_buffer = &mut self.buffer[self.index..];
+        for (src, dest) in buf.iter().zip(dest_buffer.iter_mut()) {
+            *dest = *src;
+        }
+        self.consume(buf.len());
+        Ok(buf.len())
+    }
+
+    /// Split the slice into three segments, with the middle block-aligned.
+    /// Alignment depends on the current `self.byte_addr` instead of the slice pointer address
+    fn block_align<'b>(&self, buf: &'b [u8]) -> (&'b [u8], &'b [u8], &'b [u8]) {
+        let head_len = BLOCK_SIZE - (self.byte_addr as usize % BLOCK_SIZE);
+        if head_len > buf.len() {
+            (buf, &[], &[])
+        } else {
+            let remaining_length = buf.len() - head_len;
+            let mid_length = remaining_length - remaining_length % BLOCK_SIZE;
+            let (head, remaining) = buf.split_at(head_len);
+            let (mid, tail) = remaining.split_at(mid_length);
+            (head, mid, tail)
+        }
+    }
+
+    /// Split the mutable slice into three segments, with the middle block-aligned.
+    /// Alignment depends on the current `self.byte_addr` instead of the slice pointer address
+    fn block_align_mut<'b>(&self, buf: &'b mut [u8]) -> (&'b mut [u8], &'b mut [u8], &'b mut [u8]) {
+        let head_len = BLOCK_SIZE - (self.byte_addr as usize % BLOCK_SIZE);
+        if head_len > buf.len() {
+            (buf, &mut [], &mut [])
+        } else {
+            let remaining_length = buf.len() - head_len;
+            let mid_length = remaining_length - remaining_length % BLOCK_SIZE;
+            let (head, remaining) = buf.split_at_mut(head_len);
+            let (mid, tail) = remaining.split_at_mut(mid_length);
+            (head, mid, tail)
+        }
+    }
+
+    /// Invalidate the buffer, so later unaligned read/write would reload the buffer from SD card.
+    fn invalidate_buffer(&mut self) {
+        self.index = BLOCK_SIZE;
+    }
+
+    /// Set the base offset of the SD card, to transform from physical address to logical address.
+    fn set_base_offset(&mut self, offset: u32) -> IoResult<u64> {
+        self.offset = offset;
+        self.seek(SeekFrom::Start(0))
+    }
+
+    /// Mount fatfs from partition entry, and return the fatfs object if success.
+    /// This takes the ownership of self, so currently there is no way to recover from an error,
+    /// except creating a new SD card instance.
+    pub fn mount_fatfs(mut self, entry: PartitionEntry) -> IoResult<fatfs::FileSystem<Self>> {
+        let mut buffer: [u8; 4] = [0; 4];
+        self.seek(SeekFrom::Start(0x1FE))?;
+        self.read_exact(&mut buffer[..2])?;
+        // check MBR signature
+        if buffer[..2] != MBR_SIGNATURE {
+            return Err(Error::new(
+                ErrorKind::InvalidData,
+                "Incorrect signature for MBR sector.",
+            ));
+        }
+        // Read partition ID.
+        self.seek(SeekFrom::Start(entry as u64 + 0x4))?;
+        self.read_exact(&mut buffer[..1])?;
+        debug!("Partition ID: {:0X}", buffer[0]);
+        match buffer[0] {
+            PARTID_FAT12 | PARTID_FAT16_LESS32M | PARTID_FAT16 |
+            PARTID_FAT32 | PARTID_FAT32_LBA => {}
+            _ => {
+                return Err(Error::new(
+                    ErrorKind::InvalidData,
+                    "No FAT partition found for the specified entry.",
+                ));
+            }
+        }
+        // Read LBA
+        self.seek(SeekFrom::Current(0x3))?;
+        self.read_exact(&mut buffer)?;
+        let mut lba: u32 = 0;
+        // Little endian
+        for i in 0..4 {
+            lba |= (buffer[i] as u32) << (i * 8);
+        }
+        // Set to logical address
+        self.set_base_offset(lba * BLOCK_SIZE as u32)?;
+        // setup fatfs
+        fatfs::FileSystem::new(self, fatfs::FsOptions::new())
+    }
+}
+
+impl Read for SdReader {
+    fn read(&mut self, buf: &mut [u8]) -> IoResult<usize> {
+        let total_length = buf.len();
+        let (a, b, c) = self.block_align_mut(buf);
+        self.read_unaligned(a)?;
+        if b.len() > 0 {
+            // invalidate internal buffer
+            self.invalidate_buffer();
+            if let Err(_) = self.sd.read_block(
+                self.byte_addr / BLOCK_SIZE as u32,
+                (b.len() / BLOCK_SIZE) as u16,
+                b,
+            ) {
+                // we have to allow partial read, as per the trait required
+                return Ok(a.len());
+            }
+            self.byte_addr += b.len() as u32;
+        }
+        if let Err(_) = self.read_unaligned(c) {
+            // we have to allow partial read, as per the trait required
+            return Ok(a.len() + b.len());
+        }
+        Ok(total_length)
+    }
+}
+
+impl BufRead for SdReader {
+    fn fill_buf(&mut self) -> IoResult<&[u8]> {
+        if self.index == BLOCK_SIZE {
+            // flush the buffer if it is dirty before overwriting it with new data
+            if self.dirty {
+                self.flush()?;
+            }
+            // reload buffer
+            self.sd
+                .read_block(self.byte_addr / (BLOCK_SIZE as u32), 1, &mut self.buffer)
+                .map_err(cmd_error_to_io_error)?;
+            self.index = (self.byte_addr as usize) % BLOCK_SIZE;
+        }
+        Ok(&self.buffer[self.index..])
+    }
+
+    fn consume(&mut self, amt: usize) {
+        self.index += amt;
+        self.byte_addr += amt as u32;
+    }
+}
+
+impl Write for SdReader {
+    fn write(&mut self, buf: &[u8]) -> IoResult<usize> {
+        let (a, b, c) = self.block_align(buf);
+        self.write_unaligned(a)?;
+        if b.len() > 0 {
+            self.flush()?;
+            self.invalidate_buffer();
+            if let Err(_) = self.sd.write_block(
+                self.byte_addr / BLOCK_SIZE as u32,
+                (b.len() / BLOCK_SIZE) as u16,
+                b,
+            ) {
+                return Ok(a.len());
+            }
+            self.byte_addr += b.len() as u32;
+        }
+        if let Err(_) = self.write_unaligned(c) {
+            return Ok(a.len() + b.len());
+        }
+        Ok(buf.len())
+    }
+
+    fn flush(&mut self) -> IoResult<()> {
+        if self.dirty {
+            let block_addr = (self.byte_addr - self.index as u32) / (BLOCK_SIZE as u32);
+            self.sd
+                .write_block(block_addr, 1, &self.buffer)
+                .map_err(cmd_error_to_io_error)?;
+            self.dirty = false;
+        }
+        Ok(())
+    }
+}
+
+impl Seek for SdReader {
+    fn seek(&mut self, pos: SeekFrom) -> IoResult<u64> {
+        let raw_target = match pos {
+            SeekFrom::Start(x) => self.offset as i64 + x as i64,
+            SeekFrom::Current(x) => self.byte_addr as i64 + x,
+            SeekFrom::End(_) => panic!("SD card does not support seek from end"),
+        };
+        if raw_target < self.offset as i64 || raw_target > core::u32::MAX as i64 {
+            return Err(Error::new(ErrorKind::InvalidInput, "Invalid address"));
+        }
+        let target_byte_addr = raw_target as u32;
+        let address_same_block =
+            self.byte_addr / (BLOCK_SIZE as u32) == target_byte_addr / (BLOCK_SIZE as u32);
+        // if the buffer was invalidated, we consider seek as different block
+        let same_block = address_same_block && self.index != BLOCK_SIZE;
+        if !same_block {
+            self.flush()?;
+        }
+        self.byte_addr = target_byte_addr;
+        self.index = if same_block {
+            target_byte_addr as usize % BLOCK_SIZE
+        } else {
+            // invalidate the buffer as we moved to a different block
+            BLOCK_SIZE
+        };
+        Ok((self.byte_addr - self.offset) as u64)
+    }
+}
+
+impl Drop for SdReader {
+    fn drop(&mut self) {
+        // just try to flush it, ignore error if any
+        self.flush().unwrap_or(());
+    }
+}
--- a/src/libcoreio/Cargo.toml
+++ b/src/libcoreio/Cargo.toml
@ -0,0 +1,14 @@
+[package]
+authors = ["M-Labs"]
+name = "core_io"
+version = "0.1.20200410"
+
+[lib]
+name = "core_io"
+
+[dependencies]
+memchr = { version = "2", default-features = false, optional = true }
+
+[features]
+alloc = []
+collections = ["alloc", "memchr"]
--- a/src/libcoreio/src/io/buffered.rs
+++ b/src/libcoreio/src/io/buffered.rs
--- a/src/libcoreio/src/io/cursor.rs
+++ b/src/libcoreio/src/io/cursor.rs
@ -0,0 +1,896 @@
+use crate::io::prelude::*;
+
+use core::cmp;
+use crate::io::{self, Error, ErrorKind, Initializer, SeekFrom};
+
+#[cfg(feature = "collections")]
+use core::convert::TryInto;
+
+#[cfg(feature="collections")] 
+use collections::vec::Vec;
+
+#[cfg(feature = "alloc")]
+use alloc::boxed::Box;
+
+/// A `Cursor` wraps an in-memory buffer and provides it with a
+/// [`Seek`] implementation.
+///
+/// `Cursor`s are used with in-memory buffers, anything implementing
+/// `AsRef<[u8]>`, to allow them to implement [`Read`] and/or [`Write`],
+/// allowing these buffers to be used anywhere you might use a reader or writer
+/// that does actual I/O.
+///
+/// The standard library implements some I/O traits on various types which
+/// are commonly used as a buffer, like `Cursor<`[`Vec`]`<u8>>` and
+/// `Cursor<`[`&[u8]`][bytes]`>`.
+///
+/// # Examples
+///
+/// We may want to write bytes to a [`File`] in our production
+/// code, but use an in-memory buffer in our tests. We can do this with
+/// `Cursor`:
+///
+/// [`Seek`]: trait.Seek.html
+/// [`Read`]: ../../std/io/trait.Read.html
+/// [`Write`]: ../../std/io/trait.Write.html
+/// [`Vec`]: ../../std/vec/struct.Vec.html
+/// [bytes]: ../../std/primitive.slice.html
+/// [`File`]: ../fs/struct.File.html
+///
+/// ```no_run
+/// use std::io::prelude::*;
+/// use std::io::{self, SeekFrom};
+/// use std::fs::File;
+///
+/// // a library function we've written
+/// fn write_ten_bytes_at_end<W: Write + Seek>(writer: &mut W) -> io::Result<()> {
+///     writer.seek(SeekFrom::End(-10))?;
+///
+///     for i in 0..10 {
+///         writer.write(&[i])?;
+///     }
+///
+///     // all went well
+///     Ok(())
+/// }
+///
+/// # fn foo() -> io::Result<()> {
+/// // Here's some code that uses this library function.
+/// //
+/// // We might want to use a BufReader here for efficiency, but let's
+/// // keep this example focused.
+/// let mut file = File::create("foo.txt")?;
+///
+/// write_ten_bytes_at_end(&mut file)?;
+/// # Ok(())
+/// # }
+///
+/// // now let's write a test
+/// #[test]
+/// fn test_writes_bytes() {
+///     // setting up a real File is much slower than an in-memory buffer,
+///     // let's use a cursor instead
+///     use std::io::Cursor;
+///     let mut buff = Cursor::new(vec![0; 15]);
+///
+///     write_ten_bytes_at_end(&mut buff).unwrap();
+///
+///     assert_eq!(&buff.get_ref()[5..15], &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9]);
+/// }
+/// ```
+#[derive(Clone, Debug, Default, Eq, PartialEq)]
+pub struct Cursor<T> {
+    inner: T,
+    pos: u64,
+}
+
+impl<T> Cursor<T> {
+    /// Creates a new cursor wrapping the provided underlying in-memory buffer.
+    ///
+    /// Cursor initial position is `0` even if underlying buffer (e.g., `Vec`)
+    /// is not empty. So writing to cursor starts with overwriting `Vec`
+    /// content, not with appending to it.
+    ///
+    /// # Examples
+    ///
+    /// ```
+    /// use std::io::Cursor;
+    ///
+    /// let buff = Cursor::new(Vec::new());
+    /// # fn force_inference(_: &Cursor<Vec<u8>>) {}
+    /// # force_inference(&buff);
+    /// ```
+    pub fn new(inner: T) -> Cursor<T> {
+        Cursor { pos: 0, inner }
+    }
+
+    /// Consumes this cursor, returning the underlying value.
+    ///
+    /// # Examples
+    ///
+    /// ```
+    /// use std::io::Cursor;
+    ///
+    /// let buff = Cursor::new(Vec::new());
+    /// # fn force_inference(_: &Cursor<Vec<u8>>) {}
+    /// # force_inference(&buff);
+    ///
+    /// let vec = buff.into_inner();
+    /// ```
+    pub fn into_inner(self) -> T {
+        self.inner
+    }
+
+    /// Gets a reference to the underlying value in this cursor.
+    ///
+    /// # Examples
+    ///
+    /// ```
+    /// use std::io::Cursor;
+    ///
+    /// let buff = Cursor::new(Vec::new());
+    /// # fn force_inference(_: &Cursor<Vec<u8>>) {}
+    /// # force_inference(&buff);
+    ///
+    /// let reference = buff.get_ref();
+    /// ```
+    pub fn get_ref(&self) -> &T {
+        &self.inner
+    }
+
+    /// Gets a mutable reference to the underlying value in this cursor.
+    ///
+    /// Care should be taken to avoid modifying the internal I/O state of the
+    /// underlying value as it may corrupt this cursor's position.
+    ///
+    /// # Examples
+    ///
+    /// ```
+    /// use std::io::Cursor;
+    ///
+    /// let mut buff = Cursor::new(Vec::new());
+    /// # fn force_inference(_: &Cursor<Vec<u8>>) {}
+    /// # force_inference(&buff);
+    ///
+    /// let reference = buff.get_mut();
+    /// ```
+    pub fn get_mut(&mut self) -> &mut T {
+        &mut self.inner
+    }
+
+    /// Returns the current position of this cursor.
+    ///
+    /// # Examples
+    ///
+    /// ```
+    /// use std::io::Cursor;
+    /// use std::io::prelude::*;
+    /// use std::io::SeekFrom;
+    ///
+    /// let mut buff = Cursor::new(vec![1, 2, 3, 4, 5]);
+    ///
+    /// assert_eq!(buff.position(), 0);
+    ///
+    /// buff.seek(SeekFrom::Current(2)).unwrap();
+    /// assert_eq!(buff.position(), 2);
+    ///
+    /// buff.seek(SeekFrom::Current(-1)).unwrap();
+    /// assert_eq!(buff.position(), 1);
+    /// ```
+    pub fn position(&self) -> u64 {
+        self.pos
+    }
+
+    /// Sets the position of this cursor.
+    ///
+    /// # Examples
+    ///
+    /// ```
+    /// use std::io::Cursor;
+    ///
+    /// let mut buff = Cursor::new(vec![1, 2, 3, 4, 5]);
+    ///
+    /// assert_eq!(buff.position(), 0);
+    ///
+    /// buff.set_position(2);
+    /// assert_eq!(buff.position(), 2);
+    ///
+    /// buff.set_position(4);
+    /// assert_eq!(buff.position(), 4);
+    /// ```
+    pub fn set_position(&mut self, pos: u64) {
+        self.pos = pos;
+    }
+}
+
+impl<T> io::Seek for Cursor<T>
+where
+    T: AsRef<[u8]>,
+{
+    fn seek(&mut self, style: SeekFrom) -> io::Result<u64> {
+        let (base_pos, offset) = match style {
+            SeekFrom::Start(n) => {
+                self.pos = n;
+                return Ok(n);
+            }
+            SeekFrom::End(n) => (self.inner.as_ref().len() as u64, n),
+            SeekFrom::Current(n) => (self.pos, n),
+        };
+        let new_pos = if offset >= 0 {
+            base_pos.checked_add(offset as u64)
+        } else {
+            base_pos.checked_sub((offset.wrapping_neg()) as u64)
+        };
+        match new_pos {
+            Some(n) => {
+                self.pos = n;
+                Ok(self.pos)
+            }
+            None => Err(Error::new(
+                ErrorKind::InvalidInput,
+                "invalid seek to a negative or overflowing position",
+            )),
+        }
+    }
+
+    fn stream_len(&mut self) -> io::Result<u64> {
+        Ok(self.inner.as_ref().len() as u64)
+    }
+
+    fn stream_position(&mut self) -> io::Result<u64> {
+        Ok(self.pos)
+    }
+}
+
+impl<T> Read for Cursor<T>
+where
+    T: AsRef<[u8]>,
+{
+    fn read(&mut self, buf: &mut [u8]) -> io::Result<usize> {
+        let n = Read::read(&mut self.get_ref().as_ref(), buf)?;
+        self.pos += n as u64;
+        Ok(n)
+    }
+
+    fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> {
+        let n = buf.len();
+        Read::read_exact(&mut self.get_ref().as_ref(), buf)?;
+        self.pos += n as u64;
+        Ok(())
+    }
+
+    #[inline]
+    unsafe fn initializer(&self) -> Initializer {
+        Initializer::nop()
+    }
+}
+
+#[cfg(feature = "collections")]
+impl<T> BufRead for Cursor<T>
+where
+    T: AsRef<[u8]>,
+{
+    fn fill_buf(&mut self) -> io::Result<&[u8]> {
+        let amt = cmp::min(self.pos, self.inner.as_ref().len() as u64);
+        Ok(&self.inner.as_ref()[(amt as usize)..])
+    }
+    fn consume(&mut self, amt: usize) {
+        self.pos += amt as u64;
+    }
+}
+
+// Non-resizing write implementation
+#[inline]
+fn slice_write(pos_mut: &mut u64, slice: &mut [u8], buf: &[u8]) -> io::Result<usize> {
+    let pos = cmp::min(*pos_mut, slice.len() as u64);
+    let amt = (&mut slice[(pos as usize)..]).write(buf)?;
+    *pos_mut += amt as u64;
+    Ok(amt)
+}
+
+// Resizing write implementation
+#[cfg(feature = "collections")]
+fn vec_write(pos_mut: &mut u64, vec: &mut Vec<u8>, buf: &[u8]) -> io::Result<usize> {
+    let pos: usize = (*pos_mut).try_into().map_err(|_| {
+        Error::new(
+            ErrorKind::InvalidInput,
+            "cursor position exceeds maximum possible vector length",
+        )
+    })?;
+    // Make sure the internal buffer is as least as big as where we
+    // currently are
+    let len = vec.len();
+    if len < pos {
+        // use `resize` so that the zero filling is as efficient as possible
+        vec.resize(pos, 0);
+    }
+    // Figure out what bytes will be used to overwrite what's currently
+    // there (left), and what will be appended on the end (right)
+    {
+        let space = vec.len() - pos;
+        let (left, right) = buf.split_at(cmp::min(space, buf.len()));
+        vec[pos..pos + left.len()].copy_from_slice(left);
+        vec.extend_from_slice(right);
+    }
+
+    // Bump us forward
+    *pos_mut = (pos + buf.len()) as u64;
+    Ok(buf.len())
+}
+
+impl Write for Cursor<&mut [u8]> {
+    #[inline]
+    fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
+        slice_write(&mut self.pos, self.inner, buf)
+    }
+
+    #[inline]
+    fn flush(&mut self) -> io::Result<()> {
+        Ok(())
+    }
+}
+
+#[cfg(feature = "collections")]
+impl Write for Cursor<&mut Vec<u8>> {
+    fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
+        vec_write(&mut self.pos, self.inner, buf)
+    }
+
+    #[inline]
+    fn flush(&mut self) -> io::Result<()> {
+        Ok(())
+    }
+}
+
+#[cfg(feature = "collections")]
+impl Write for Cursor<Vec<u8>> {
+    fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
+        vec_write(&mut self.pos, &mut self.inner, buf)
+    }
+
+    #[inline]
+    fn flush(&mut self) -> io::Result<()> {
+        Ok(())
+    }
+}
+
+#[cfg(feature = "alloc")]
+impl Write for Cursor<Box<[u8]>> {
+    #[inline]
+    fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
+        slice_write(&mut self.pos, &mut self.inner, buf)
+    }
+
+    #[inline]
+    fn flush(&mut self) -> io::Result<()> {
+        Ok(())
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use crate::io::prelude::*;
+    use crate::io::{Cursor, IoSlice, IoSliceMut, SeekFrom};
+
+    #[test]
+    fn test_vec_writer() {
+        let mut writer = Vec::new();
+        assert_eq!(writer.write(&[0]).unwrap(), 1);
+        assert_eq!(writer.write(&[1, 2, 3]).unwrap(), 3);
+        assert_eq!(writer.write(&[4, 5, 6, 7]).unwrap(), 4);
+        assert_eq!(
+            writer
+                .write_vectored(&[IoSlice::new(&[]), IoSlice::new(&[8, 9]), IoSlice::new(&[10])],)
+                .unwrap(),
+            3
+        );
+        let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10];
+        assert_eq!(writer, b);
+    }
+
+    #[test]
+    fn test_mem_writer() {
+        let mut writer = Cursor::new(Vec::new());
+        assert_eq!(writer.write(&[0]).unwrap(), 1);
+        assert_eq!(writer.write(&[1, 2, 3]).unwrap(), 3);
+        assert_eq!(writer.write(&[4, 5, 6, 7]).unwrap(), 4);
+        assert_eq!(
+            writer
+                .write_vectored(&[IoSlice::new(&[]), IoSlice::new(&[8, 9]), IoSlice::new(&[10])],)
+                .unwrap(),
+            3
+        );
+        let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10];
+        assert_eq!(&writer.get_ref()[..], b);
+    }
+
+    #[test]
+    fn test_mem_mut_writer() {
+        let mut vec = Vec::new();
+        let mut writer = Cursor::new(&mut vec);
+        assert_eq!(writer.write(&[0]).unwrap(), 1);
+        assert_eq!(writer.write(&[1, 2, 3]).unwrap(), 3);
+        assert_eq!(writer.write(&[4, 5, 6, 7]).unwrap(), 4);
+        assert_eq!(
+            writer
+                .write_vectored(&[IoSlice::new(&[]), IoSlice::new(&[8, 9]), IoSlice::new(&[10])],)
+                .unwrap(),
+            3
+        );
+        let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10];
+        assert_eq!(&writer.get_ref()[..], b);
+    }
+
+    #[test]
+    fn test_box_slice_writer() {
+        let mut writer = Cursor::new(vec![0u8; 9].into_boxed_slice());
+        assert_eq!(writer.position(), 0);
+        assert_eq!(writer.write(&[0]).unwrap(), 1);
+        assert_eq!(writer.position(), 1);
+        assert_eq!(writer.write(&[1, 2, 3]).unwrap(), 3);
+        assert_eq!(writer.write(&[4, 5, 6, 7]).unwrap(), 4);
+        assert_eq!(writer.position(), 8);
+        assert_eq!(writer.write(&[]).unwrap(), 0);
+        assert_eq!(writer.position(), 8);
+
+        assert_eq!(writer.write(&[8, 9]).unwrap(), 1);
+        assert_eq!(writer.write(&[10]).unwrap(), 0);
+        let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8];
+        assert_eq!(&**writer.get_ref(), b);
+    }
+
+    #[test]
+    fn test_box_slice_writer_vectored() {
+        let mut writer = Cursor::new(vec![0u8; 9].into_boxed_slice());
+        assert_eq!(writer.position(), 0);
+        assert_eq!(writer.write_vectored(&[IoSlice::new(&[0])]).unwrap(), 1);
+        assert_eq!(writer.position(), 1);
+        assert_eq!(
+            writer
+                .write_vectored(&[IoSlice::new(&[1, 2, 3]), IoSlice::new(&[4, 5, 6, 7]),])
+                .unwrap(),
+            7,
+        );
+        assert_eq!(writer.position(), 8);
+        assert_eq!(writer.write_vectored(&[]).unwrap(), 0);
+        assert_eq!(writer.position(), 8);
+
+        assert_eq!(writer.write_vectored(&[IoSlice::new(&[8, 9])]).unwrap(), 1);
+        assert_eq!(writer.write_vectored(&[IoSlice::new(&[10])]).unwrap(), 0);
+        let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8];
+        assert_eq!(&**writer.get_ref(), b);
+    }
+
+    #[test]
+    fn test_buf_writer() {
+        let mut buf = [0 as u8; 9];
+        {
+            let mut writer = Cursor::new(&mut buf[..]);
+            assert_eq!(writer.position(), 0);
+            assert_eq!(writer.write(&[0]).unwrap(), 1);
+            assert_eq!(writer.position(), 1);
+            assert_eq!(writer.write(&[1, 2, 3]).unwrap(), 3);
+            assert_eq!(writer.write(&[4, 5, 6, 7]).unwrap(), 4);
+            assert_eq!(writer.position(), 8);
+            assert_eq!(writer.write(&[]).unwrap(), 0);
+            assert_eq!(writer.position(), 8);
+
+            assert_eq!(writer.write(&[8, 9]).unwrap(), 1);
+            assert_eq!(writer.write(&[10]).unwrap(), 0);
+        }
+        let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8];
+        assert_eq!(buf, b);
+    }
+
+    #[test]
+    fn test_buf_writer_vectored() {
+        let mut buf = [0 as u8; 9];
+        {
+            let mut writer = Cursor::new(&mut buf[..]);
+            assert_eq!(writer.position(), 0);
+            assert_eq!(writer.write_vectored(&[IoSlice::new(&[0])]).unwrap(), 1);
+            assert_eq!(writer.position(), 1);
+            assert_eq!(
+                writer
+                    .write_vectored(&[IoSlice::new(&[1, 2, 3]), IoSlice::new(&[4, 5, 6, 7])],)
+                    .unwrap(),
+                7,
+            );
+            assert_eq!(writer.position(), 8);
+            assert_eq!(writer.write_vectored(&[]).unwrap(), 0);
+            assert_eq!(writer.position(), 8);
+
+            assert_eq!(writer.write_vectored(&[IoSlice::new(&[8, 9])]).unwrap(), 1);
+            assert_eq!(writer.write_vectored(&[IoSlice::new(&[10])]).unwrap(), 0);
+        }
+        let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8];
+        assert_eq!(buf, b);
+    }
+
+    #[test]
+    fn test_buf_writer_seek() {
+        let mut buf = [0 as u8; 8];
+        {
+            let mut writer = Cursor::new(&mut buf[..]);
+            assert_eq!(writer.position(), 0);
+            assert_eq!(writer.write(&[1]).unwrap(), 1);
+            assert_eq!(writer.position(), 1);
+
+            assert_eq!(writer.seek(SeekFrom::Start(2)).unwrap(), 2);
+            assert_eq!(writer.position(), 2);
+            assert_eq!(writer.write(&[2]).unwrap(), 1);
+            assert_eq!(writer.position(), 3);
+
+            assert_eq!(writer.seek(SeekFrom::Current(-2)).unwrap(), 1);
+            assert_eq!(writer.position(), 1);
+            assert_eq!(writer.write(&[3]).unwrap(), 1);
+            assert_eq!(writer.position(), 2);
+
+            assert_eq!(writer.seek(SeekFrom::End(-1)).unwrap(), 7);
+            assert_eq!(writer.position(), 7);
+            assert_eq!(writer.write(&[4]).unwrap(), 1);
+            assert_eq!(writer.position(), 8);
+        }
+        let b: &[_] = &[1, 3, 2, 0, 0, 0, 0, 4];
+        assert_eq!(buf, b);
+    }
+
+    #[test]
+    fn test_buf_writer_error() {
+        let mut buf = [0 as u8; 2];
+        let mut writer = Cursor::new(&mut buf[..]);
+        assert_eq!(writer.write(&[0]).unwrap(), 1);
+        assert_eq!(writer.write(&[0, 0]).unwrap(), 1);
+        assert_eq!(writer.write(&[0, 0]).unwrap(), 0);
+    }
+
+    #[test]
+    fn test_mem_reader() {
+        let mut reader = Cursor::new(vec![0, 1, 2, 3, 4, 5, 6, 7]);
+        let mut buf = [];
+        assert_eq!(reader.read(&mut buf).unwrap(), 0);
+        assert_eq!(reader.position(), 0);
+        let mut buf = [0];
+        assert_eq!(reader.read(&mut buf).unwrap(), 1);
+        assert_eq!(reader.position(), 1);
+        let b: &[_] = &[0];
+        assert_eq!(buf, b);
+        let mut buf = [0; 4];
+        assert_eq!(reader.read(&mut buf).unwrap(), 4);
+        assert_eq!(reader.position(), 5);
+        let b: &[_] = &[1, 2, 3, 4];
+        assert_eq!(buf, b);
+        assert_eq!(reader.read(&mut buf).unwrap(), 3);
+        let b: &[_] = &[5, 6, 7];
+        assert_eq!(&buf[..3], b);
+        assert_eq!(reader.read(&mut buf).unwrap(), 0);
+    }
+
+    #[test]
+    fn test_mem_reader_vectored() {
+        let mut reader = Cursor::new(vec![0, 1, 2, 3, 4, 5, 6, 7]);
+        let mut buf = [];
+        assert_eq!(reader.read_vectored(&mut [IoSliceMut::new(&mut buf)]).unwrap(), 0);
+        assert_eq!(reader.position(), 0);
+        let mut buf = [0];
+        assert_eq!(
+            reader
+                .read_vectored(&mut [IoSliceMut::new(&mut []), IoSliceMut::new(&mut buf),])
+                .unwrap(),
+            1,
+        );
+        assert_eq!(reader.position(), 1);
+        let b: &[_] = &[0];
+        assert_eq!(buf, b);
+        let mut buf1 = [0; 4];
+        let mut buf2 = [0; 4];
+        assert_eq!(
+            reader
+                .read_vectored(&mut [IoSliceMut::new(&mut buf1), IoSliceMut::new(&mut buf2),])
+                .unwrap(),
+            7,
+        );
+        let b1: &[_] = &[1, 2, 3, 4];
+        let b2: &[_] = &[5, 6, 7];
+        assert_eq!(buf1, b1);
+        assert_eq!(&buf2[..3], b2);
+        assert_eq!(reader.read(&mut buf).unwrap(), 0);
+    }
+
+    #[test]
+    fn test_boxed_slice_reader() {
+        let mut reader = Cursor::new(vec![0, 1, 2, 3, 4, 5, 6, 7].into_boxed_slice());
+        let mut buf = [];
+        assert_eq!(reader.read(&mut buf).unwrap(), 0);
+        assert_eq!(reader.position(), 0);
+        let mut buf = [0];
+        assert_eq!(reader.read(&mut buf).unwrap(), 1);
+        assert_eq!(reader.position(), 1);
+        let b: &[_] = &[0];
+        assert_eq!(buf, b);
+        let mut buf = [0; 4];
+        assert_eq!(reader.read(&mut buf).unwrap(), 4);
+        assert_eq!(reader.position(), 5);
+        let b: &[_] = &[1, 2, 3, 4];
+        assert_eq!(buf, b);
+        assert_eq!(reader.read(&mut buf).unwrap(), 3);
+        let b: &[_] = &[5, 6, 7];
+        assert_eq!(&buf[..3], b);
+        assert_eq!(reader.read(&mut buf).unwrap(), 0);
+    }
+
+    #[test]
+    fn test_boxed_slice_reader_vectored() {
+        let mut reader = Cursor::new(vec![0, 1, 2, 3, 4, 5, 6, 7].into_boxed_slice());
+        let mut buf = [];
+        assert_eq!(reader.read_vectored(&mut [IoSliceMut::new(&mut buf)]).unwrap(), 0);
+        assert_eq!(reader.position(), 0);
+        let mut buf = [0];
+        assert_eq!(
+            reader
+                .read_vectored(&mut [IoSliceMut::new(&mut []), IoSliceMut::new(&mut buf),])
+                .unwrap(),
+            1,
+        );
+        assert_eq!(reader.position(), 1);
+        let b: &[_] = &[0];
+        assert_eq!(buf, b);
+        let mut buf1 = [0; 4];
+        let mut buf2 = [0; 4];
+        assert_eq!(
+            reader
+                .read_vectored(&mut [IoSliceMut::new(&mut buf1), IoSliceMut::new(&mut buf2)],)
+                .unwrap(),
+            7,
+        );
+        let b1: &[_] = &[1, 2, 3, 4];
+        let b2: &[_] = &[5, 6, 7];
+        assert_eq!(buf1, b1);
+        assert_eq!(&buf2[..3], b2);
+        assert_eq!(reader.read(&mut buf).unwrap(), 0);
+    }
+
+    #[test]
+    fn read_to_end() {
+        let mut reader = Cursor::new(vec![0, 1, 2, 3, 4, 5, 6, 7]);
+        let mut v = Vec::new();
+        reader.read_to_end(&mut v).unwrap();
+        assert_eq!(v, [0, 1, 2, 3, 4, 5, 6, 7]);
+    }
+
+    #[test]
+    fn test_slice_reader() {
+        let in_buf = vec![0, 1, 2, 3, 4, 5, 6, 7];
+        let reader = &mut &in_buf[..];
+        let mut buf = [];
+        assert_eq!(reader.read(&mut buf).unwrap(), 0);
+        let mut buf = [0];
+        assert_eq!(reader.read(&mut buf).unwrap(), 1);
+        assert_eq!(reader.len(), 7);
+        let b: &[_] = &[0];
+        assert_eq!(&buf[..], b);
+        let mut buf = [0; 4];
+        assert_eq!(reader.read(&mut buf).unwrap(), 4);
+        assert_eq!(reader.len(), 3);
+        let b: &[_] = &[1, 2, 3, 4];
+        assert_eq!(&buf[..], b);
+        assert_eq!(reader.read(&mut buf).unwrap(), 3);
+        let b: &[_] = &[5, 6, 7];
+        assert_eq!(&buf[..3], b);
+        assert_eq!(reader.read(&mut buf).unwrap(), 0);
+    }
+
+    #[test]
+    fn test_slice_reader_vectored() {
+        let in_buf = vec![0, 1, 2, 3, 4, 5, 6, 7];
+        let reader = &mut &in_buf[..];
+        let mut buf = [];
+        assert_eq!(reader.read_vectored(&mut [IoSliceMut::new(&mut buf)]).unwrap(), 0);
+        let mut buf = [0];
+        assert_eq!(
+            reader
+                .read_vectored(&mut [IoSliceMut::new(&mut []), IoSliceMut::new(&mut buf),])
+                .unwrap(),
+            1,
+        );
+        assert_eq!(reader.len(), 7);
+        let b: &[_] = &[0];
+        assert_eq!(buf, b);
+        let mut buf1 = [0; 4];
+        let mut buf2 = [0; 4];
+        assert_eq!(
+            reader
+                .read_vectored(&mut [IoSliceMut::new(&mut buf1), IoSliceMut::new(&mut buf2)],)
+                .unwrap(),
+            7,
+        );
+        let b1: &[_] = &[1, 2, 3, 4];
+        let b2: &[_] = &[5, 6, 7];
+        assert_eq!(buf1, b1);
+        assert_eq!(&buf2[..3], b2);
+        assert_eq!(reader.read(&mut buf).unwrap(), 0);
+    }
+
+    #[test]
+    fn test_read_exact() {
+        let in_buf = vec![0, 1, 2, 3, 4, 5, 6, 7];
+        let reader = &mut &in_buf[..];
+        let mut buf = [];
+        assert!(reader.read_exact(&mut buf).is_ok());
+        let mut buf = [8];
+        assert!(reader.read_exact(&mut buf).is_ok());
+        assert_eq!(buf[0], 0);
+        assert_eq!(reader.len(), 7);
+        let mut buf = [0, 0, 0, 0, 0, 0, 0];
+        assert!(reader.read_exact(&mut buf).is_ok());
+        assert_eq!(buf, [1, 2, 3, 4, 5, 6, 7]);
+        assert_eq!(reader.len(), 0);
+        let mut buf = [0];
+        assert!(reader.read_exact(&mut buf).is_err());
+    }
+
+    #[test]
+    fn test_buf_reader() {
+        let in_buf = vec![0, 1, 2, 3, 4, 5, 6, 7];
+        let mut reader = Cursor::new(&in_buf[..]);
+        let mut buf = [];
+        assert_eq!(reader.read(&mut buf).unwrap(), 0);
+        assert_eq!(reader.position(), 0);
+        let mut buf = [0];
+        assert_eq!(reader.read(&mut buf).unwrap(), 1);
+        assert_eq!(reader.position(), 1);
+        let b: &[_] = &[0];
+        assert_eq!(buf, b);
+        let mut buf = [0; 4];
+        assert_eq!(reader.read(&mut buf).unwrap(), 4);
+        assert_eq!(reader.position(), 5);
+        let b: &[_] = &[1, 2, 3, 4];
+        assert_eq!(buf, b);
+        assert_eq!(reader.read(&mut buf).unwrap(), 3);
+        let b: &[_] = &[5, 6, 7];
+        assert_eq!(&buf[..3], b);
+        assert_eq!(reader.read(&mut buf).unwrap(), 0);
+    }
+
+    #[test]
+    fn seek_past_end() {
+        let buf = [0xff];
+        let mut r = Cursor::new(&buf[..]);
+        assert_eq!(r.seek(SeekFrom::Start(10)).unwrap(), 10);
+        assert_eq!(r.read(&mut [0]).unwrap(), 0);
+
+        let mut r = Cursor::new(vec![10]);
+        assert_eq!(r.seek(SeekFrom::Start(10)).unwrap(), 10);
+        assert_eq!(r.read(&mut [0]).unwrap(), 0);
+
+        let mut buf = [0];
+        let mut r = Cursor::new(&mut buf[..]);
+        assert_eq!(r.seek(SeekFrom::Start(10)).unwrap(), 10);
+        assert_eq!(r.write(&[3]).unwrap(), 0);
+
+        let mut r = Cursor::new(vec![10].into_boxed_slice());
+        assert_eq!(r.seek(SeekFrom::Start(10)).unwrap(), 10);
+        assert_eq!(r.write(&[3]).unwrap(), 0);
+    }
+
+    #[test]
+    fn seek_past_i64() {
+        let buf = [0xff];
+        let mut r = Cursor::new(&buf[..]);
+        assert_eq!(r.seek(SeekFrom::Start(6)).unwrap(), 6);
+        assert_eq!(r.seek(SeekFrom::Current(0x7ffffffffffffff0)).unwrap(), 0x7ffffffffffffff6);
+        assert_eq!(r.seek(SeekFrom::Current(0x10)).unwrap(), 0x8000000000000006);
+        assert_eq!(r.seek(SeekFrom::Current(0)).unwrap(), 0x8000000000000006);
+        assert!(r.seek(SeekFrom::Current(0x7ffffffffffffffd)).is_err());
+        assert_eq!(r.seek(SeekFrom::Current(-0x8000000000000000)).unwrap(), 6);
+
+        let mut r = Cursor::new(vec![10]);
+        assert_eq!(r.seek(SeekFrom::Start(6)).unwrap(), 6);
+        assert_eq!(r.seek(SeekFrom::Current(0x7ffffffffffffff0)).unwrap(), 0x7ffffffffffffff6);
+        assert_eq!(r.seek(SeekFrom::Current(0x10)).unwrap(), 0x8000000000000006);
+        assert_eq!(r.seek(SeekFrom::Current(0)).unwrap(), 0x8000000000000006);
+        assert!(r.seek(SeekFrom::Current(0x7ffffffffffffffd)).is_err());
+        assert_eq!(r.seek(SeekFrom::Current(-0x8000000000000000)).unwrap(), 6);
+
+        let mut buf = [0];
+        let mut r = Cursor::new(&mut buf[..]);
+        assert_eq!(r.seek(SeekFrom::Start(6)).unwrap(), 6);
+        assert_eq!(r.seek(SeekFrom::Current(0x7ffffffffffffff0)).unwrap(), 0x7ffffffffffffff6);
+        assert_eq!(r.seek(SeekFrom::Current(0x10)).unwrap(), 0x8000000000000006);
+        assert_eq!(r.seek(SeekFrom::Current(0)).unwrap(), 0x8000000000000006);
+        assert!(r.seek(SeekFrom::Current(0x7ffffffffffffffd)).is_err());
+        assert_eq!(r.seek(SeekFrom::Current(-0x8000000000000000)).unwrap(), 6);
+
+        let mut r = Cursor::new(vec![10].into_boxed_slice());
+        assert_eq!(r.seek(SeekFrom::Start(6)).unwrap(), 6);
+        assert_eq!(r.seek(SeekFrom::Current(0x7ffffffffffffff0)).unwrap(), 0x7ffffffffffffff6);
+        assert_eq!(r.seek(SeekFrom::Current(0x10)).unwrap(), 0x8000000000000006);
+        assert_eq!(r.seek(SeekFrom::Current(0)).unwrap(), 0x8000000000000006);
+        assert!(r.seek(SeekFrom::Current(0x7ffffffffffffffd)).is_err());
+        assert_eq!(r.seek(SeekFrom::Current(-0x8000000000000000)).unwrap(), 6);
+    }
+
+    #[test]
+    fn seek_before_0() {
+        let buf = [0xff];
+        let mut r = Cursor::new(&buf[..]);
+        assert!(r.seek(SeekFrom::End(-2)).is_err());
+
+        let mut r = Cursor::new(vec![10]);
+        assert!(r.seek(SeekFrom::End(-2)).is_err());
+
+        let mut buf = [0];
+        let mut r = Cursor::new(&mut buf[..]);
+        assert!(r.seek(SeekFrom::End(-2)).is_err());
+
+        let mut r = Cursor::new(vec![10].into_boxed_slice());
+        assert!(r.seek(SeekFrom::End(-2)).is_err());
+    }
+
+    #[test]
+    fn test_seekable_mem_writer() {
+        let mut writer = Cursor::new(Vec::<u8>::new());
+        assert_eq!(writer.position(), 0);
+        assert_eq!(writer.write(&[0]).unwrap(), 1);
+        assert_eq!(writer.position(), 1);
+        assert_eq!(writer.write(&[1, 2, 3]).unwrap(), 3);
+        assert_eq!(writer.write(&[4, 5, 6, 7]).unwrap(), 4);
+        assert_eq!(writer.position(), 8);
+        let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7];
+        assert_eq!(&writer.get_ref()[..], b);
+
+        assert_eq!(writer.seek(SeekFrom::Start(0)).unwrap(), 0);
+        assert_eq!(writer.position(), 0);
+        assert_eq!(writer.write(&[3, 4]).unwrap(), 2);
+        let b: &[_] = &[3, 4, 2, 3, 4, 5, 6, 7];
+        assert_eq!(&writer.get_ref()[..], b);
+
+        assert_eq!(writer.seek(SeekFrom::Current(1)).unwrap(), 3);
+        assert_eq!(writer.write(&[0, 1]).unwrap(), 2);
+        let b: &[_] = &[3, 4, 2, 0, 1, 5, 6, 7];
+        assert_eq!(&writer.get_ref()[..], b);
+
+        assert_eq!(writer.seek(SeekFrom::End(-1)).unwrap(), 7);
+        assert_eq!(writer.write(&[1, 2]).unwrap(), 2);
+        let b: &[_] = &[3, 4, 2, 0, 1, 5, 6, 1, 2];
+        assert_eq!(&writer.get_ref()[..], b);
+
+        assert_eq!(writer.seek(SeekFrom::End(1)).unwrap(), 10);
+        assert_eq!(writer.write(&[1]).unwrap(), 1);
+        let b: &[_] = &[3, 4, 2, 0, 1, 5, 6, 1, 2, 0, 1];
+        assert_eq!(&writer.get_ref()[..], b);
+    }
+
+    #[test]
+    fn vec_seek_past_end() {
+        let mut r = Cursor::new(Vec::new());
+        assert_eq!(r.seek(SeekFrom::Start(10)).unwrap(), 10);
+        assert_eq!(r.write(&[3]).unwrap(), 1);
+    }
+
+    #[test]
+    fn vec_seek_before_0() {
+        let mut r = Cursor::new(Vec::new());
+        assert!(r.seek(SeekFrom::End(-2)).is_err());
+    }
+
+    #[test]
+    #[cfg(target_pointer_width = "32")]
+    fn vec_seek_and_write_past_usize_max() {
+        let mut c = Cursor::new(Vec::new());
+        c.set_position(<usize>::max_value() as u64 + 1);
+        assert!(c.write_all(&[1, 2, 3]).is_err());
+    }
+
+    #[test]
+    fn test_partial_eq() {
+        assert_eq!(Cursor::new(Vec::<u8>::new()), Cursor::new(Vec::<u8>::new()));
+    }
+
+    #[test]
+    fn test_eq() {
+        struct AssertEq<T: Eq>(pub T);
+
+        let _: AssertEq<Cursor<Vec<u8>>> = AssertEq(Cursor::new(Vec::new()));
+    }
+}
--- a/src/libcoreio/src/io/error.rs
+++ b/src/libcoreio/src/io/error.rs
@ -0,0 +1,551 @@
+#[cfg(feature="alloc")] use alloc::boxed::Box;
+#[cfg(not(feature="alloc"))] use ::FakeBox as Box;
+use core::convert::Into;
+use core::fmt;
+use core::marker::{Send, Sync};
+use core::option::Option::{self, Some, None};
+use core::result;
+#[cfg(feature="collections")] use collections::string::String;
+#[cfg(not(feature="collections"))] use ::ErrorString as String;
+use core::convert::From;
+
+/// A specialized [`Result`](../result/enum.Result.html) type for I/O
+/// operations.
+///
+/// This type is broadly used across [`std::io`] for any operation which may
+/// produce an error.
+///
+/// This typedef is generally used to avoid writing out [`io::Error`] directly and
+/// is otherwise a direct mapping to [`Result`].
+///
+/// While usual Rust style is to import types directly, aliases of [`Result`]
+/// often are not, to make it easier to distinguish between them. [`Result`] is
+/// generally assumed to be [`std::result::Result`][`Result`], and so users of this alias
+/// will generally use `io::Result` instead of shadowing the prelude's import
+/// of [`std::result::Result`][`Result`].
+///
+/// [`std::io`]: ../io/index.html
+/// [`io::Error`]: ../io/struct.Error.html
+/// [`Result`]: ../result/enum.Result.html
+///
+/// # Examples
+///
+/// A convenience function that bubbles an `io::Result` to its caller:
+///
+/// ```
+/// use std::io;
+///
+/// fn get_string() -> io::Result<String> {
+///     let mut buffer = String::new();
+///
+///     io::stdin().read_line(&mut buffer)?;
+///
+///     Ok(buffer)
+/// }
+/// ```
+pub type Result<T> = result::Result<T, Error>;
+
+/// The error type for I/O operations of the [`Read`], [`Write`], [`Seek`], and
+/// associated traits.
+///
+/// Errors mostly originate from the underlying OS, but custom instances of
+/// `Error` can be created with crafted error messages and a particular value of
+/// [`ErrorKind`].
+///
+/// [`Read`]: ../io/trait.Read.html
+/// [`Write`]: ../io/trait.Write.html
+/// [`Seek`]: ../io/trait.Seek.html
+/// [`ErrorKind`]: enum.ErrorKind.html
+pub struct Error {
+    repr: Repr,
+}
+
+impl fmt::Debug for Error {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        fmt::Debug::fmt(&self.repr, f)
+    }
+}
+
+enum Repr {
+    Os(i32),
+    Simple(ErrorKind),
+    #[cfg(feature="alloc")]
+    Custom(Box<Custom>),
+    #[cfg(not(feature="alloc"))]
+    Custom(Custom),
+}
+
+#[derive(Debug)]
+struct Custom {
+    kind: ErrorKind,
+    error: String,
+}
+
+/// A list specifying general categories of I/O error.
+///
+/// This list is intended to grow over time and it is not recommended to
+/// exhaustively match against it.
+///
+/// It is used with the [`io::Error`] type.
+///
+/// [`io::Error`]: struct.Error.html
+#[derive(Clone, Copy, Debug, Eq, Hash, Ord, PartialEq, PartialOrd)]
+#[allow(deprecated)]
+#[non_exhaustive]
+pub enum ErrorKind {
+    /// An entity was not found, often a file.
+    NotFound,
+    /// The operation lacked the necessary privileges to complete.
+    PermissionDenied,
+    /// The connection was refused by the remote server.
+    ConnectionRefused,
+    /// The connection was reset by the remote server.
+    ConnectionReset,
+    /// The connection was aborted (terminated) by the remote server.
+    ConnectionAborted,
+    /// The network operation failed because it was not connected yet.
+    NotConnected,
+    /// A socket address could not be bound because the address is already in
+    /// use elsewhere.
+    AddrInUse,
+    /// A nonexistent interface was requested or the requested address was not
+    /// local.
+    AddrNotAvailable,
+    /// The operation failed because a pipe was closed.
+    BrokenPipe,
+    /// An entity already exists, often a file.
+    AlreadyExists,
+    /// The operation needs to block to complete, but the blocking operation was
+    /// requested to not occur.
+    WouldBlock,
+    /// A parameter was incorrect.
+    InvalidInput,
+    /// Data not valid for the operation were encountered.
+    ///
+    /// Unlike [`InvalidInput`], this typically means that the operation
+    /// parameters were valid, however the error was caused by malformed
+    /// input data.
+    ///
+    /// For example, a function that reads a file into a string will error with
+    /// `InvalidData` if the file's contents are not valid UTF-8.
+    ///
+    /// [`InvalidInput`]: #variant.InvalidInput
+    InvalidData,
+    /// The I/O operation's timeout expired, causing it to be canceled.
+    TimedOut,
+    /// An error returned when an operation could not be completed because a
+    /// call to [`write`] returned [`Ok(0)`].
+    ///
+    /// This typically means that an operation could only succeed if it wrote a
+    /// particular number of bytes but only a smaller number of bytes could be
+    /// written.
+    ///
+    /// [`write`]: ../../std/io/trait.Write.html#tymethod.write
+    /// [`Ok(0)`]: ../../std/io/type.Result.html
+    WriteZero,
+    /// This operation was interrupted.
+    ///
+    /// Interrupted operations can typically be retried.
+    Interrupted,
+    /// Any I/O error not part of this list.
+    Other,
+
+    /// An error returned when an operation could not be completed because an
+    /// "end of file" was reached prematurely.
+    ///
+    /// This typically means that an operation could only succeed if it read a
+    /// particular number of bytes but only a smaller number of bytes could be
+    /// read.
+    UnexpectedEof,
+}
+
+impl ErrorKind {
+    pub(crate) fn as_str(&self) -> &'static str {
+        match *self {
+            ErrorKind::NotFound => "entity not found",
+            ErrorKind::PermissionDenied => "permission denied",
+            ErrorKind::ConnectionRefused => "connection refused",
+            ErrorKind::ConnectionReset => "connection reset",
+            ErrorKind::ConnectionAborted => "connection aborted",
+            ErrorKind::NotConnected => "not connected",
+            ErrorKind::AddrInUse => "address in use",
+            ErrorKind::AddrNotAvailable => "address not available",
+            ErrorKind::BrokenPipe => "broken pipe",
+            ErrorKind::AlreadyExists => "entity already exists",
+            ErrorKind::WouldBlock => "operation would block",
+            ErrorKind::InvalidInput => "invalid input parameter",
+            ErrorKind::InvalidData => "invalid data",
+            ErrorKind::TimedOut => "timed out",
+            ErrorKind::WriteZero => "write zero",
+            ErrorKind::Interrupted => "operation interrupted",
+            ErrorKind::Other => "other os error",
+            ErrorKind::UnexpectedEof => "unexpected end of file",
+        }
+    }
+}
+
+/// Intended for use for errors not exposed to the user, where allocating onto
+/// the heap (for normal construction via Error::new) is too costly.
+impl From<ErrorKind> for Error {
+    /// Converts an [`ErrorKind`] into an [`Error`].
+    ///
+    /// This conversion allocates a new error with a simple representation of error kind.
+    ///
+    /// # Examples
+    ///
+    /// ```
+    /// use std::io::{Error, ErrorKind};
+    ///
+    /// let not_found = ErrorKind::NotFound;
+    /// let error = Error::from(not_found);
+    /// assert_eq!("entity not found", format!("{}", error));
+    /// ```
+    ///
+    /// [`ErrorKind`]: ../../std/io/enum.ErrorKind.html
+    /// [`Error`]: ../../std/io/struct.Error.html
+    #[inline]
+    fn from(kind: ErrorKind) -> Error {
+        Error { repr: Repr::Simple(kind) }
+    }
+}
+
+impl Error {
+    /// Creates a new I/O error from a known kind of error as well as an
+    /// arbitrary error payload.
+    ///
+    /// This function is used to generically create I/O errors which do not
+    /// originate from the OS itself. The `error` argument is an arbitrary
+    /// payload which will be contained in this `Error`.
+    ///
+    /// # Examples
+    ///
+    /// ```
+    /// use std::io::{Error, ErrorKind};
+    ///
+    /// // errors can be created from strings
+    /// let custom_error = Error::new(ErrorKind::Other, "oh no!");
+    ///
+    /// // errors can also be created from other errors
+    /// let custom_error2 = Error::new(ErrorKind::Interrupted, custom_error);
+    /// ```
+    pub fn new<E>(kind: ErrorKind, error: E) -> Error
+    where
+        E: Into<String>,
+    {
+        Self::_new(kind, error.into())
+    }
+
+    fn _new(kind: ErrorKind, error: String) -> Error {
+        Error { repr: Repr::Custom(Box::new(Custom { kind, error })) }
+    }
+
+    /// Creates a new instance of an `Error` from a particular OS error code.
+    ///
+    /// # Examples
+    ///
+    /// On Linux:
+    ///
+    /// ```
+    /// # if cfg!(target_os = "linux") {
+    /// use std::io;
+    ///
+    /// let error = io::Error::from_raw_os_error(22);
+    /// assert_eq!(error.kind(), io::ErrorKind::InvalidInput);
+    /// # }
+    /// ```
+    ///
+    /// On Windows:
+    ///
+    /// ```
+    /// # if cfg!(windows) {
+    /// use std::io;
+    ///
+    /// let error = io::Error::from_raw_os_error(10022);
+    /// assert_eq!(error.kind(), io::ErrorKind::InvalidInput);
+    /// # }
+    /// ```
+    pub fn from_raw_os_error(code: i32) -> Error {
+        Error { repr: Repr::Os(code) }
+    }
+
+    /// Returns the OS error that this error represents (if any).
+    ///
+    /// If this `Error` was constructed via `last_os_error` or
+    /// `from_raw_os_error`, then this function will return `Some`, otherwise
+    /// it will return `None`.
+    ///
+    /// # Examples
+    ///
+    /// ```
+    /// use std::io::{Error, ErrorKind};
+    ///
+    /// fn print_os_error(err: &Error) {
+    ///     if let Some(raw_os_err) = err.raw_os_error() {
+    ///         println!("raw OS error: {:?}", raw_os_err);
+    ///     } else {
+    ///         println!("Not an OS error");
+    ///     }
+    /// }
+    ///
+    /// fn main() {
+    ///     // Will print "raw OS error: ...".
+    ///     print_os_error(&Error::last_os_error());
+    ///     // Will print "Not an OS error".
+    ///     print_os_error(&Error::new(ErrorKind::Other, "oh no!"));
+    /// }
+    /// ```
+    pub fn raw_os_error(&self) -> Option<i32> {
+        match self.repr {
+            Repr::Os(i) => Some(i),
+            Repr::Custom(..) => None,
+            Repr::Simple(..) => None,
+        }
+    }
+
+    /// Returns a reference to the inner error wrapped by this error (if any).
+    ///
+    /// If this `Error` was constructed via `new` then this function will
+    /// return `Some`, otherwise it will return `None`.
+    ///
+    /// # Examples
+    ///
+    /// ```
+    /// use std::io::{Error, ErrorKind};
+    ///
+    /// fn print_error(err: &Error) {
+    ///     if let Some(inner_err) = err.get_ref() {
+    ///         println!("Inner error: {:?}", inner_err);
+    ///     } else {
+    ///         println!("No inner error");
+    ///     }
+    /// }
+    ///
+    /// fn main() {
+    ///     // Will print "No inner error".
+    ///     print_error(&Error::last_os_error());
+    ///     // Will print "Inner error: ...".
+    ///     print_error(&Error::new(ErrorKind::Other, "oh no!"));
+    /// }
+    /// ```
+    pub fn get_ref(&self) -> Option<&String> {
+        match self.repr {
+            Repr::Os(..) => None,
+            Repr::Simple(..) => None,
+            Repr::Custom(ref c) => Some(&c.error),
+        }
+    }
+
+    /// Returns a mutable reference to the inner error wrapped by this error
+    /// (if any).
+    ///
+    /// If this `Error` was constructed via `new` then this function will
+    /// return `Some`, otherwise it will return `None`.
+    ///
+    /// # Examples
+    ///
+    /// ```
+    /// use std::io::{Error, ErrorKind};
+    /// use std::{error, fmt};
+    /// use std::fmt::Display;
+    ///
+    /// #[derive(Debug)]
+    /// struct MyError {
+    ///     v: String,
+    /// }
+    ///
+    /// impl MyError {
+    ///     fn new() -> MyError {
+    ///         MyError {
+    ///             v: "oh no!".to_string()
+    ///         }
+    ///     }
+    ///
+    ///     fn change_message(&mut self, new_message: &str) {
+    ///         self.v = new_message.to_string();
+    ///     }
+    /// }
+    ///
+    /// impl error::Error for MyError {}
+    ///
+    /// impl Display for MyError {
+    ///     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+    ///         write!(f, "MyError: {}", &self.v)
+    ///     }
+    /// }
+    ///
+    /// fn change_error(mut err: Error) -> Error {
+    ///     if let Some(inner_err) = err.get_mut() {
+    ///         inner_err.downcast_mut::<MyError>().unwrap().change_message("I've been changed!");
+    ///     }
+    ///     err
+    /// }
+    ///
+    /// fn print_error(err: &Error) {
+    ///     if let Some(inner_err) = err.get_ref() {
+    ///         println!("Inner error: {}", inner_err);
+    ///     } else {
+    ///         println!("No inner error");
+    ///     }
+    /// }
+    ///
+    /// fn main() {
+    ///     // Will print "No inner error".
+    ///     print_error(&change_error(Error::last_os_error()));
+    ///     // Will print "Inner error: ...".
+    ///     print_error(&change_error(Error::new(ErrorKind::Other, MyError::new())));
+    /// }
+    /// ```
+    pub fn get_mut(&mut self) -> Option<&mut String> {
+        match self.repr {
+            Repr::Os(..) => None,
+            Repr::Simple(..) => None,
+            Repr::Custom(ref mut c) => Some(&mut c.error),
+        }
+    }
+
+    /// Consumes the `Error`, returning its inner error (if any).
+    ///
+    /// If this `Error` was constructed via `new` then this function will
+    /// return `Some`, otherwise it will return `None`.
+    ///
+    /// # Examples
+    ///
+    /// ```
+    /// use std::io::{Error, ErrorKind};
+    ///
+    /// fn print_error(err: Error) {
+    ///     if let Some(inner_err) = err.into_inner() {
+    ///         println!("Inner error: {}", inner_err);
+    ///     } else {
+    ///         println!("No inner error");
+    ///     }
+    /// }
+    ///
+    /// fn main() {
+    ///     // Will print "No inner error".
+    ///     print_error(Error::last_os_error());
+    ///     // Will print "Inner error: ...".
+    ///     print_error(Error::new(ErrorKind::Other, "oh no!"));
+    /// }
+    /// ```
+    pub fn into_inner(self) -> Option<String> {
+        match self.repr {
+            Repr::Os(..) => None,
+            Repr::Simple(..) => None,
+            Repr::Custom(c) => Some(c.error),
+        }
+    }
+
+    /// Returns the corresponding `ErrorKind` for this error.
+    ///
+    /// # Examples
+    ///
+    /// ```
+    /// use std::io::{Error, ErrorKind};
+    ///
+    /// fn print_error(err: Error) {
+    ///     println!("{:?}", err.kind());
+    /// }
+    ///
+    /// fn main() {
+    ///     // Will print "No inner error".
+    ///     print_error(Error::last_os_error());
+    ///     // Will print "Inner error: ...".
+    ///     print_error(Error::new(ErrorKind::AddrInUse, "oh no!"));
+    /// }
+    /// ```
+    pub fn kind(&self) -> ErrorKind {
+        match self.repr {
+            Repr::Os(_code) => ErrorKind::Other,
+            Repr::Custom(ref c) => c.kind,
+            Repr::Simple(kind) => kind,
+        }
+    }
+}
+
+impl fmt::Debug for Repr {
+    fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match *self {
+            Repr::Os(code) => fmt
+                .debug_struct("Os")
+                .field("code", &code)
+                .finish(),
+            Repr::Custom(ref c) => fmt::Debug::fmt(&c, fmt),
+            Repr::Simple(kind) => fmt.debug_tuple("Kind").field(&kind).finish(),
+        }
+    }
+}
+
+impl fmt::Display for Error {
+    fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self.repr {
+            Repr::Os(code) => {
+                write!(fmt, "os error {}", code)
+            }
+            Repr::Custom(ref c) => c.error.fmt(fmt),
+            Repr::Simple(kind) => write!(fmt, "{}", kind.as_str()),
+        }
+    }
+}
+
+fn _assert_error_is_sync_send() {
+    fn _is_sync_send<T: Sync + Send>() {}
+    _is_sync_send::<Error>();
+}
+
+#[cfg(test)]
+mod test {
+    use super::{Custom, Error, ErrorKind, Repr};
+    use crate::error;
+    use crate::fmt;
+    use crate::sys::decode_error_kind;
+    use crate::sys::os::error_string;
+
+    #[test]
+    fn test_debug_error() {
+        let code = 6;
+        let msg = error_string(code);
+        let kind = decode_error_kind(code);
+        let err = Error {
+            repr: Repr::Custom(box Custom {
+                kind: ErrorKind::InvalidInput,
+                error: box Error { repr: super::Repr::Os(code) },
+            }),
+        };
+        let expected = format!(
+            "Custom {{ \
+             kind: InvalidInput, \
+             error: Os {{ \
+             code: {:?}, \
+             kind: {:?}, \
+             message: {:?} \
+             }} \
+             }}",
+            code, kind, msg
+        );
+        assert_eq!(format!("{:?}", err), expected);
+    }
+
+    #[test]
+    fn test_downcasting() {
+        #[derive(Debug)]
+        struct TestError;
+
+        impl fmt::Display for TestError {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                f.write_str("asdf")
+            }
+        }
+
+        impl error::Error for TestError {}
+
+        // we have to call all of these UFCS style right now since method
+        // resolution won't implicitly drop the Send+Sync bounds
+        let mut err = Error::new(ErrorKind::Other, TestError);
+        assert!(err.get_ref().unwrap().is::<TestError>());
+        assert_eq!("asdf", err.get_ref().unwrap().to_string());
+        assert!(err.get_mut().unwrap().is::<TestError>());
+        let extracted = err.into_inner().unwrap();
+        extracted.downcast::<TestError>().unwrap();
+    }
+}
--- a/src/libcoreio/src/io/impls.rs
+++ b/src/libcoreio/src/io/impls.rs
@ -0,0 +1,378 @@
+use core::cmp;
+use core::fmt;
+use crate::io::{
+    self, Error, ErrorKind, Initializer, Read, Seek, SeekFrom, Write,
+};
+#[cfg(feature = "collections")] use crate::io::BufRead;
+use core::mem;
+
+#[cfg(feature="collections")] 
+use collections::{
+    vec::Vec,
+    string::String,
+};
+#[cfg(feature = "alloc")]
+use alloc::boxed::Box;
+
+// =============================================================================
+// Forwarding implementations
+
+impl<R: Read + ?Sized> Read for &mut R {
+    #[inline]
+    fn read(&mut self, buf: &mut [u8]) -> io::Result<usize> {
+        (**self).read(buf)
+    }
+
+    #[inline]
+    unsafe fn initializer(&self) -> Initializer {
+        (**self).initializer()
+    }
+
+    #[cfg(feature="collections")]
+    #[inline]
+    fn read_to_end(&mut self, buf: &mut Vec<u8>) -> io::Result<usize> {
+        (**self).read_to_end(buf)
+    }
+
+    #[cfg(feature="collections")]
+    #[inline]
+    fn read_to_string(&mut self, buf: &mut String) -> io::Result<usize> {
+        (**self).read_to_string(buf)
+    }
+
+    #[inline]
+    fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> {
+        (**self).read_exact(buf)
+    }
+}
+impl<W: Write + ?Sized> Write for &mut W {
+    #[inline]
+    fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
+        (**self).write(buf)
+    }
+
+    #[inline]
+    fn flush(&mut self) -> io::Result<()> {
+        (**self).flush()
+    }
+
+    #[inline]
+    fn write_all(&mut self, buf: &[u8]) -> io::Result<()> {
+        (**self).write_all(buf)
+    }
+
+    #[inline]
+    fn write_fmt(&mut self, fmt: fmt::Arguments<'_>) -> io::Result<()> {
+        (**self).write_fmt(fmt)
+    }
+}
+impl<S: Seek + ?Sized> Seek for &mut S {
+    #[inline]
+    fn seek(&mut self, pos: SeekFrom) -> io::Result<u64> {
+        (**self).seek(pos)
+    }
+}
+#[cfg(feature = "collections")]
+impl<B: BufRead + ?Sized> BufRead for &mut B {
+    #[inline]
+    fn fill_buf(&mut self) -> io::Result<&[u8]> {
+        (**self).fill_buf()
+    }
+
+    #[inline]
+    fn consume(&mut self, amt: usize) {
+        (**self).consume(amt)
+    }
+
+    #[cfg(feature="collections")]
+    #[inline]
+    fn read_until(&mut self, byte: u8, buf: &mut Vec<u8>) -> io::Result<usize> {
+        (**self).read_until(byte, buf)
+    }
+
+    #[cfg(feature="collections")]
+    #[inline]
+    fn read_line(&mut self, buf: &mut String) -> io::Result<usize> {
+        (**self).read_line(buf)
+    }
+}
+
+#[cfg(feature="alloc")]
+#[cfg(feature="collections")]
+impl<R: Read + ?Sized> Read for Box<R> {
+    #[inline]
+    fn read(&mut self, buf: &mut [u8]) -> io::Result<usize> {
+        (**self).read(buf)
+    }
+
+    #[cfg(feature="collections")]
+    #[inline]
+    fn read_to_end(&mut self, buf: &mut Vec<u8>) -> io::Result<usize> {
+        (**self).read_to_end(buf)
+    }
+
+    #[cfg(feature="collections")]
+    #[inline]
+    fn read_to_string(&mut self, buf: &mut String) -> io::Result<usize> {
+        (**self).read_to_string(buf)
+    }
+
+    #[inline]
+    fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> {
+        (**self).read_exact(buf)
+    }
+}
+#[cfg(feature="alloc")]
+#[cfg(feature="collections")]
+impl<W: Write + ?Sized> Write for Box<W> {
+    #[inline]
+    fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
+        (**self).write(buf)
+    }
+
+    #[inline]
+    fn flush(&mut self) -> io::Result<()> {
+        (**self).flush()
+    }
+
+    #[inline]
+    fn write_all(&mut self, buf: &[u8]) -> io::Result<()> {
+        (**self).write_all(buf)
+    }
+
+    #[inline]
+    fn write_fmt(&mut self, fmt: fmt::Arguments<'_>) -> io::Result<()> {
+        (**self).write_fmt(fmt)
+    }
+}
+#[cfg(feature="collections")]
+impl<S: Seek + ?Sized> Seek for Box<S> {
+    #[inline]
+    fn seek(&mut self, pos: SeekFrom) -> io::Result<u64> {
+        (**self).seek(pos)
+    }
+}
+#[cfg(feature="collections")]
+impl<B: BufRead + ?Sized> BufRead for Box<B> {
+    #[inline]
+    fn fill_buf(&mut self) -> io::Result<&[u8]> {
+        (**self).fill_buf()
+    }
+
+    #[inline]
+    fn consume(&mut self, amt: usize) {
+        (**self).consume(amt)
+    }
+
+    #[inline]
+    fn read_until(&mut self, byte: u8, buf: &mut Vec<u8>) -> io::Result<usize> {
+        (**self).read_until(byte, buf)
+    }
+
+    #[inline]
+    fn read_line(&mut self, buf: &mut String) -> io::Result<usize> {
+        (**self).read_line(buf)
+    }
+}
+
+// Used by panicking::default_hook
+#[cfg(test)]
+/// This impl is only used by printing logic, so any error returned is always
+/// of kind `Other`, and should be ignored.
+#[cfg(feature="collections")]
+impl Write for Box<dyn (::realstd::io::Write) + Send> {
+    fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
+        (**self).write(buf).map_err(|_| ErrorKind::Other.into())
+    }
+
+    fn flush(&mut self) -> io::Result<()> {
+        (**self).flush().map_err(|_| ErrorKind::Other.into())
+    }
+}
+
+// =============================================================================
+// In-memory buffer implementations
+
+/// Read is implemented for `&[u8]` by copying from the slice.
+///
+/// Note that reading updates the slice to point to the yet unread part.
+/// The slice will be empty when EOF is reached.
+impl Read for &[u8] {
+    #[inline]
+    fn read(&mut self, buf: &mut [u8]) -> io::Result<usize> {
+        let amt = cmp::min(buf.len(), self.len());
+        let (a, b) = self.split_at(amt);
+
+        // First check if the amount of bytes we want to read is small:
+        // `copy_from_slice` will generally expand to a call to `memcpy`, and
+        // for a single byte the overhead is significant.
+        if amt == 1 {
+            buf[0] = a[0];
+        } else {
+            buf[..amt].copy_from_slice(a);
+        }
+
+        *self = b;
+        Ok(amt)
+    }
+
+    #[inline]
+    unsafe fn initializer(&self) -> Initializer {
+        Initializer::nop()
+    }
+
+    #[inline]
+    fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> {
+        if buf.len() > self.len() {
+            return Err(Error::new(ErrorKind::UnexpectedEof, "failed to fill whole buffer"));
+        }
+        let (a, b) = self.split_at(buf.len());
+
+        // First check if the amount of bytes we want to read is small:
+        // `copy_from_slice` will generally expand to a call to `memcpy`, and
+        // for a single byte the overhead is significant.
+        if buf.len() == 1 {
+            buf[0] = a[0];
+        } else {
+            buf.copy_from_slice(a);
+        }
+
+        *self = b;
+        Ok(())
+    }
+
+    #[cfg(feature="collections")]
+    #[inline]
+    fn read_to_end(&mut self, buf: &mut Vec<u8>) -> io::Result<usize> {
+        buf.extend_from_slice(*self);
+        let len = self.len();
+        *self = &self[len..];
+        Ok(len)
+    }
+}
+
+#[cfg(feature="collections")]
+impl BufRead for &[u8] {
+    #[inline]
+    fn fill_buf(&mut self) -> io::Result<&[u8]> {
+        Ok(*self)
+    }
+
+    #[inline]
+    fn consume(&mut self, amt: usize) {
+        *self = &self[amt..];
+    }
+}
+
+/// Write is implemented for `&mut [u8]` by copying into the slice, overwriting
+/// its data.
+///
+/// Note that writing updates the slice to point to the yet unwritten part.
+/// The slice will be empty when it has been completely overwritten.
+impl Write for &mut [u8] {
+    #[inline]
+    fn write(&mut self, data: &[u8]) -> io::Result<usize> {
+        let amt = cmp::min(data.len(), self.len());
+        let (a, b) = mem::replace(self, &mut []).split_at_mut(amt);
+        a.copy_from_slice(&data[..amt]);
+        *self = b;
+        Ok(amt)
+    }
+
+    #[inline]
+    fn write_all(&mut self, data: &[u8]) -> io::Result<()> {
+        if self.write(data)? == data.len() {
+            Ok(())
+        } else {
+            Err(Error::new(ErrorKind::WriteZero, "failed to write whole buffer"))
+        }
+    }
+
+    #[inline]
+    fn flush(&mut self) -> io::Result<()> {
+        Ok(())
+    }
+}
+
+/// Write is implemented for `Vec<u8>` by appending to the vector.
+/// The vector will grow as needed.
+#[cfg(feature="collections")]
+impl Write for Vec<u8> {
+    #[inline]
+    fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
+        self.extend_from_slice(buf);
+        Ok(buf.len())
+    }
+
+    #[inline]
+    fn write_all(&mut self, buf: &[u8]) -> io::Result<()> {
+        self.extend_from_slice(buf);
+        Ok(())
+    }
+
+    #[inline]
+    fn flush(&mut self) -> io::Result<()> {
+        Ok(())
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use crate::io::prelude::*;
+
+    #[bench]
+    fn bench_read_slice(b: &mut test::Bencher) {
+        let buf = [5; 1024];
+        let mut dst = [0; 128];
+
+        b.iter(|| {
+            let mut rd = &buf[..];
+            for _ in 0..8 {
+                let _ = rd.read(&mut dst);
+                test::black_box(&dst);
+            }
+        })
+    }
+
+    #[bench]
+    fn bench_write_slice(b: &mut test::Bencher) {
+        let mut buf = [0; 1024];
+        let src = [5; 128];
+
+        b.iter(|| {
+            let mut wr = &mut buf[..];
+            for _ in 0..8 {
+                let _ = wr.write_all(&src);
+                test::black_box(&wr);
+            }
+        })
+    }
+
+    #[bench]
+    fn bench_read_vec(b: &mut test::Bencher) {
+        let buf = vec![5; 1024];
+        let mut dst = [0; 128];
+
+        b.iter(|| {
+            let mut rd = &buf[..];
+            for _ in 0..8 {
+                let _ = rd.read(&mut dst);
+                test::black_box(&dst);
+            }
+        })
+    }
+
+    #[bench]
+    fn bench_write_vec(b: &mut test::Bencher) {
+        let mut buf = Vec::with_capacity(1024);
+        let src = [5; 128];
+
+        b.iter(|| {
+            let mut wr = &mut buf[..];
+            for _ in 0..8 {
+                let _ = wr.write_all(&src);
+                test::black_box(&wr);
+            }
+        })
+    }
+}
--- a/src/libcoreio/src/io/mod.rs
+++ b/src/libcoreio/src/io/mod.rs
--- a/src/libcoreio/src/io/prelude.rs
+++ b/src/libcoreio/src/io/prelude.rs
@ -0,0 +1,13 @@
+//! The I/O Prelude
+//!
+//! The purpose of this module is to alleviate imports of many common I/O traits
+//! by adding a glob import to the top of I/O heavy modules:
+//!
+//! ```
+//! # #![allow(unused_imports)]
+//! use std::io::prelude::*;
+//! ```
+
+
+pub use super::{Read, Seek, Write};
+#[cfg(feature = "collections")] pub use super::BufRead;
--- a/src/libcoreio/src/io/util.rs
+++ b/src/libcoreio/src/io/util.rs
@ -0,0 +1,269 @@
+#![allow(missing_copy_implementations)]
+
+use core::fmt;
+use core::mem;
+use crate::io::{self, ErrorKind, Initializer, Read, Write};
+#[cfg(feature = "collections")] use crate::io::BufRead;
+
+/// Copies the entire contents of a reader into a writer.
+///
+/// This function will continuously read data from `reader` and then
+/// write it into `writer` in a streaming fashion until `reader`
+/// returns EOF.
+///
+/// On success, the total number of bytes that were copied from
+/// `reader` to `writer` is returned.
+///
+/// If you’re wanting to copy the contents of one file to another and you’re
+/// working with filesystem paths, see the [`fs::copy`] function.
+///
+/// [`fs::copy`]: ../fs/fn.copy.html
+///
+/// # Errors
+///
+/// This function will return an error immediately if any call to `read` or
+/// `write` returns an error. All instances of `ErrorKind::Interrupted` are
+/// handled by this function and the underlying operation is retried.
+///
+/// # Examples
+///
+/// ```
+/// use std::io;
+///
+/// fn main() -> io::Result<()> {
+///     let mut reader: &[u8] = b"hello";
+///     let mut writer: Vec<u8> = vec![];
+///
+///     io::copy(&mut reader, &mut writer)?;
+///
+///     assert_eq!(&b"hello"[..], &writer[..]);
+///     Ok(())
+/// }
+/// ```
+pub fn copy<R: ?Sized, W: ?Sized>(reader: &mut R, writer: &mut W) -> io::Result<u64>
+where
+    R: Read,
+    W: Write,
+{
+    let mut buf = unsafe {
+        #[allow(deprecated)]
+        let mut buf: [u8; super::DEFAULT_BUF_SIZE] = mem::uninitialized();
+        reader.initializer().initialize(&mut buf);
+        buf
+    };
+
+    let mut written = 0;
+    loop {
+        let len = match reader.read(&mut buf) {
+            Ok(0) => return Ok(written),
+            Ok(len) => len,
+            Err(ref e) if e.kind() == ErrorKind::Interrupted => continue,
+            Err(e) => return Err(e),
+        };
+        writer.write_all(&buf[..len])?;
+        written += len as u64;
+    }
+}
+
+/// A reader which is always at EOF.
+///
+/// This struct is generally created by calling [`empty`]. Please see
+/// the documentation of [`empty()`][`empty`] for more details.
+///
+/// [`empty`]: fn.empty.html
+pub struct Empty {
+    _priv: (),
+}
+
+/// Constructs a new handle to an empty reader.
+///
+/// All reads from the returned reader will return [`Ok`]`(0)`.
+///
+/// [`Ok`]: ../result/enum.Result.html#variant.Ok
+///
+/// # Examples
+///
+/// A slightly sad example of not reading anything into a buffer:
+///
+/// ```
+/// use std::io::{self, Read};
+///
+/// let mut buffer = String::new();
+/// io::empty().read_to_string(&mut buffer).unwrap();
+/// assert!(buffer.is_empty());
+/// ```
+pub fn empty() -> Empty {
+    Empty { _priv: () }
+}
+
+impl Read for Empty {
+    #[inline]
+    fn read(&mut self, _buf: &mut [u8]) -> io::Result<usize> {
+        Ok(0)
+    }
+
+    #[inline]
+    unsafe fn initializer(&self) -> Initializer {
+        Initializer::nop()
+    }
+}
+
+#[cfg(feature="collections")]
+impl BufRead for Empty {
+    #[inline]
+    fn fill_buf(&mut self) -> io::Result<&[u8]> {
+        Ok(&[])
+    }
+    #[inline]
+    fn consume(&mut self, _n: usize) {}
+}
+
+impl fmt::Debug for Empty {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.pad("Empty { .. }")
+    }
+}
+
+/// A reader which yields one byte over and over and over and over and over and...
+///
+/// This struct is generally created by calling [`repeat`][repeat]. Please
+/// see the documentation of `repeat()` for more details.
+///
+/// [repeat]: fn.repeat.html
+pub struct Repeat {
+    byte: u8,
+}
+
+/// Creates an instance of a reader that infinitely repeats one byte.
+///
+/// All reads from this reader will succeed by filling the specified buffer with
+/// the given byte.
+///
+/// # Examples
+///
+/// ```
+/// use std::io::{self, Read};
+///
+/// let mut buffer = [0; 3];
+/// io::repeat(0b101).read_exact(&mut buffer).unwrap();
+/// assert_eq!(buffer, [0b101, 0b101, 0b101]);
+/// ```
+pub fn repeat(byte: u8) -> Repeat {
+    Repeat { byte }
+}
+
+impl Read for Repeat {
+    #[inline]
+    fn read(&mut self, buf: &mut [u8]) -> io::Result<usize> {
+        for slot in &mut *buf {
+            *slot = self.byte;
+        }
+        Ok(buf.len())
+    }
+
+    #[inline]
+    unsafe fn initializer(&self) -> Initializer {
+        Initializer::nop()
+    }
+}
+
+impl fmt::Debug for Repeat {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.pad("Repeat { .. }")
+    }
+}
+
+/// A writer which will move data into the void.
+///
+/// This struct is generally created by calling [`sink`][sink]. Please
+/// see the documentation of `sink()` for more details.
+///
+/// [sink]: fn.sink.html
+pub struct Sink {
+    _priv: (),
+}
+
+/// Creates an instance of a writer which will successfully consume all data.
+///
+/// All calls to `write` on the returned instance will return `Ok(buf.len())`
+/// and the contents of the buffer will not be inspected.
+///
+/// # Examples
+///
+/// ```rust
+/// use std::io::{self, Write};
+///
+/// let buffer = vec![1, 2, 3, 5, 8];
+/// let num_bytes = io::sink().write(&buffer).unwrap();
+/// assert_eq!(num_bytes, 5);
+/// ```
+pub fn sink() -> Sink {
+    Sink { _priv: () }
+}
+
+impl Write for Sink {
+    #[inline]
+    fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
+        Ok(buf.len())
+    }
+
+    #[inline]
+    fn flush(&mut self) -> io::Result<()> {
+        Ok(())
+    }
+}
+
+impl fmt::Debug for Sink {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.pad("Sink { .. }")
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use crate::io::prelude::*;
+    use crate::io::{copy, empty, repeat, sink};
+
+    #[test]
+    fn copy_copies() {
+        let mut r = repeat(0).take(4);
+        let mut w = sink();
+        assert_eq!(copy(&mut r, &mut w).unwrap(), 4);
+
+        let mut r = repeat(0).take(1 << 17);
+        assert_eq!(copy(&mut r as &mut dyn Read, &mut w as &mut dyn Write).unwrap(), 1 << 17);
+    }
+
+    #[test]
+    fn sink_sinks() {
+        let mut s = sink();
+        assert_eq!(s.write(&[]).unwrap(), 0);
+        assert_eq!(s.write(&[0]).unwrap(), 1);
+        assert_eq!(s.write(&[0; 1024]).unwrap(), 1024);
+        assert_eq!(s.by_ref().write(&[0; 1024]).unwrap(), 1024);
+    }
+
+    #[test]
+    fn empty_reads() {
+        let mut e = empty();
+        assert_eq!(e.read(&mut []).unwrap(), 0);
+        assert_eq!(e.read(&mut [0]).unwrap(), 0);
+        assert_eq!(e.read(&mut [0; 1024]).unwrap(), 0);
+        assert_eq!(e.by_ref().read(&mut [0; 1024]).unwrap(), 0);
+    }
+
+    #[test]
+    fn repeat_repeats() {
+        let mut r = repeat(4);
+        let mut b = [0; 1024];
+        assert_eq!(r.read(&mut b).unwrap(), 1024);
+        assert!(b.iter().all(|b| *b == 4));
+    }
+
+    #[test]
+    fn take_some_bytes() {
+        assert_eq!(repeat(4).take(100).bytes().count(), 100);
+        assert_eq!(repeat(4).take(100).bytes().next().unwrap().unwrap(), 4);
+        assert_eq!(repeat(1).take(10).chain(repeat(2).take(10)).bytes().count(), 20);
+    }
+}
--- a/src/libcoreio/src/lib.rs
+++ b/src/libcoreio/src/lib.rs
@ -0,0 +1,51 @@
+//! <p id="core_io-show-docblock"></p>
+//! This is just a listing of the functionality available in this crate. See
+//! the [std documentation](https://doc.rust-lang.org/nightly/std/io/index.html)
+//! for a full description of the functionality.
+#![allow(stable_features,unused_features)]
+#![feature(question_mark,const_fn,copy_from_slice,try_from,str_internals,align_offset,slice_internals)]
+#![cfg_attr(any(feature="alloc",feature="collections"),feature(alloc))]
+#![cfg_attr(pattern_guards,feature(bind_by_move_pattern_guards,nll))]
+#![cfg_attr(non_exhaustive,feature(non_exhaustive))]
+#![cfg_attr(unicode,feature(str_char))]
+#![cfg_attr(unicode,feature(unicode))]
+#![no_std]
+
+#[cfg_attr(feature="collections",macro_use)]
+#[cfg_attr(feature="collections",allow(unused_imports))]
+#[cfg(feature="collections")] extern crate alloc as collections;
+#[cfg(feature="alloc")] extern crate alloc;
+#[cfg(rustc_unicode)]
+extern crate rustc_unicode;
+#[cfg(std_unicode)]
+extern crate std_unicode;
+
+#[cfg(not(feature="collections"))]
+pub type ErrorString = &'static str;
+
+// Provide Box::new wrapper
+#[cfg(not(feature="alloc"))]
+struct FakeBox<T>(core::marker::PhantomData<T>);
+#[cfg(not(feature="alloc"))]
+impl<T> FakeBox<T> {
+	fn new(val: T) -> T {
+		val
+	}
+}
+
+// Needed for older compilers, to ignore vec!/format! macros in tests
+#[cfg(not(feature="collections"))]
+#[allow(unused)]
+macro_rules! vec (
+	( $ elem : expr ; $ n : expr ) => { () };
+	( $ ( $ x : expr ) , * ) => { () };
+	( $ ( $ x : expr , ) * ) => { () };
+);
+#[cfg(not(feature="collections"))]
+#[allow(unused)]
+macro_rules! format {
+	( $ ( $ arg : tt ) * ) => { () };
+}
+
+mod io;
+pub use io::*;
--- a/src/libdwarf/Cargo.toml
+++ b/src/libdwarf/Cargo.toml
@ -15,4 +15,3 @@ libc = { path = "../libc" }
 unwind = { path = "../libunwind" }
 compiler_builtins = "0.1.0"
 cfg-if = "0.1.8"
-cslice = "0.3"
--- a/src/libdwarf/src/eh.rs
+++ b/src/libdwarf/src/eh.rs
@ -13,7 +13,6 @@

 use crate::DwarfReader;
 use core::mem;
-use cslice::CSlice;

 pub const DW_EH_PE_omit: u8 = 0xFF;
 pub const DW_EH_PE_absptr: u8 = 0x00;
@ -52,45 +51,10 @@ pub enum EHAction {

 pub const USING_SJLJ_EXCEPTIONS: bool = cfg!(all(target_os = "ios", target_arch = "arm"));

-fn size_of_encoded_value(encoding: u8) -> usize {
-    if encoding == DW_EH_PE_omit {
-        0
-    } else {
-        let encoding = encoding & 0x07;
-        match encoding {
-            DW_EH_PE_absptr => core::mem::size_of::<*const ()>(),
-            DW_EH_PE_udata2 => 2,
-            DW_EH_PE_udata4 => 4,
-            DW_EH_PE_udata8 => 8,
-            _ => unreachable!(),
-        }
-    }
-}
-
-unsafe fn get_ttype_entry(
-    offset: usize,
-    encoding: u8,
-    ttype_base: usize,
-    ttype: *const u8,
-) -> Result<*const u8, ()> {
-    let i = (offset * size_of_encoded_value(encoding)) as isize;
-    read_encoded_pointer_with_base(
-        &mut DwarfReader::new(ttype.offset(-i)),
-        // the DW_EH_PE_pcrel is a hack.
-        // It seems that the default encoding is absolute, but we have to take reallocation into
-        // account. Unsure if we can fix this in the compiler setting or if this would be affected
-        // by updating the compiler
-        encoding | DW_EH_PE_pcrel,
-        ttype_base,
-    )
-    .map(|v| v as *const u8)
-}
-
 pub unsafe fn find_eh_action(
    lsda: *const u8,
    context: &EHContext<'_>,
    foreign_exception: bool,
-    id: u32,
 ) -> Result<EHAction, ()> {
    if lsda.is_null() {
        return Ok(EHAction::None);
@ -108,17 +72,10 @@ pub unsafe fn find_eh_action(
    };

    let ttype_encoding = reader.read::<u8>();
-    // we do care about the type table
-    let ttype_offset = if ttype_encoding != DW_EH_PE_omit {
-        reader.read_uleb128()
-    } else {
-        0
-    };
-    // for rust functions, it seems that there is no type table, so I just put whatever value here.
-    // we should not return an error, otherwise we would abort unwinding and cannot unwind through
-    // rust functions
-    let ttype_base = get_base(ttype_encoding, context).unwrap_or(1);
-    let ttype_table = reader.ptr.offset(ttype_offset as isize);
+    if ttype_encoding != DW_EH_PE_omit {
+        // Rust doesn't analyze exception types, so we don't care about the type table
+        reader.read_uleb128();
+    }

    let call_site_encoding = reader.read::<u8>();
    let call_site_table_length = reader.read_uleb128();
@ -137,53 +94,11 @@ pub unsafe fn find_eh_action(
                break;
            }
            if ip < func_start + cs_start + cs_len {
-                // https://github.com/gcc-mirror/gcc/blob/master/libstdc%2B%2B-v3/libsupc%2B%2B/eh_personality.cc#L528
-                let lpad = lpad_base + cs_lpad;
                if cs_lpad == 0 {
-                    // no cleanups/handler
-                    return Ok(EHAction::None);
-                } else if cs_action == 0 {
-                    return Ok(EHAction::Cleanup(lpad));
-                } else if foreign_exception {
                    return Ok(EHAction::None);
                } else {
-                    let mut saw_cleanup = false;
-                    let mut action_record = action_table.offset(cs_action as isize - 1);
-                    loop {
-                        let mut reader = DwarfReader::new(action_record);
-                        let ar_filter = reader.read_sleb128();
-                        action_record = reader.ptr;
-                        let ar_disp = reader.read_sleb128();
-                        if ar_filter == 0 {
-                            saw_cleanup = true;
-                        } else if ar_filter > 0 {
-                            let catch_type = get_ttype_entry(
-                                ar_filter as usize,
-                                ttype_encoding,
-                                ttype_base,
-                                ttype_table,
-                            )?;
-                            let clause_ptr = *(catch_type as *const *const u32);
-                            if clause_ptr.is_null() {
-                                return Ok(EHAction::Catch(lpad));
-                            }
-                            if *clause_ptr == id {
-                                return Ok(EHAction::Catch(lpad));
-                            }
-                        } else if ar_filter < 0 {
-                            // FIXME: how to handle this?
-                            break;
-                        }
-                        if ar_disp == 0 {
-                            break;
-                        }
-                        action_record = action_record.offset((ar_disp as usize) as isize);
-                    }
-                    if saw_cleanup {
-                        return Ok(EHAction::Cleanup(lpad));
-                    } else {
-                        return Ok(EHAction::None);
-                    }
+                    let lpad = lpad_base + cs_lpad;
+                    return Ok(interpret_cs_action(cs_action, lpad, foreign_exception));
                }
            }
        }
@ -191,7 +106,7 @@ pub unsafe fn find_eh_action(
        // So rather than returning EHAction::Terminate, we do this.
        Ok(EHAction::None)
    } else {
-        // SjLj version: (not yet modified)
+        // SjLj version:
        // The "IP" is an index into the call-site table, with two exceptions:
        // -1 means 'no-action', and 0 means 'terminate'.
        match ip as isize {
@ -231,41 +146,18 @@ fn interpret_cs_action(cs_action: u64, lpad: usize, foreign_exception: bool) ->

 #[inline]
 fn round_up(unrounded: usize, align: usize) -> Result<usize, ()> {
-    if align.is_power_of_two() {
-        Ok((unrounded + align - 1) & !(align - 1))
-    } else {
-        Err(())
-    }
-}
-
-fn get_base(encoding: u8, context: &EHContext<'_>) -> Result<usize, ()> {
-    match encoding & 0x70 {
-        DW_EH_PE_absptr | DW_EH_PE_pcrel | DW_EH_PE_aligned => Ok(0),
-        DW_EH_PE_textrel => Ok((*context.get_text_start)()),
-        DW_EH_PE_datarel => Ok((*context.get_data_start)()),
-        DW_EH_PE_funcrel if context.func_start != 0 => Ok(context.func_start),
-        _ => return Err(()),
-    }
+    if align.is_power_of_two() { Ok((unrounded + align - 1) & !(align - 1)) } else { Err(()) }
 }

 unsafe fn read_encoded_pointer(
    reader: &mut DwarfReader,
    context: &EHContext<'_>,
    encoding: u8,
-) -> Result<usize, ()> {
-    read_encoded_pointer_with_base(reader, encoding, get_base(encoding, context)?)
-}
-
-unsafe fn read_encoded_pointer_with_base(
-    reader: &mut DwarfReader,
-    encoding: u8,
-    base: usize,
 ) -> Result<usize, ()> {
    if encoding == DW_EH_PE_omit {
        return Err(());
    }

-    let original_ptr = reader.ptr;
    // DW_EH_PE_aligned implies it's an absolute pointer value
    if encoding == DW_EH_PE_aligned {
        reader.ptr = round_up(reader.ptr as usize, mem::size_of::<usize>())? as *const u8;
@ -285,10 +177,19 @@ unsafe fn read_encoded_pointer_with_base(
        _ => return Err(()),
    };

-    result += if (encoding & 0x70) == DW_EH_PE_pcrel {
-        original_ptr as usize
-    } else {
-        base
+    result += match encoding & 0x70 {
+        DW_EH_PE_absptr => 0,
+        // relative to address of the encoded value, despite the name
+        DW_EH_PE_pcrel => reader.ptr as usize,
+        DW_EH_PE_funcrel => {
+            if context.func_start == 0 {
+                return Err(());
+            }
+            context.func_start
+        }
+        DW_EH_PE_textrel => (*context.get_text_start)(),
+        DW_EH_PE_datarel => (*context.get_data_start)(),
+        _ => return Err(()),
    };

    if encoding & DW_EH_PE_indirect != 0 {
--- a/src/libdwarf/src/lib.rs
+++ b/src/libdwarf/src/lib.rs
@ -26,10 +26,6 @@ impl DwarfReader {
        DwarfReader { ptr }
    }

-    pub unsafe fn offset(&mut self, offset: isize) {
-        self.ptr = self.ptr.offset(offset);
-    }
-
    // DWARF streams are packed, so e.g., a u32 would not necessarily be aligned
    // on a 4-byte boundary. This may cause problems on platforms with strict
    // alignment requirements. By wrapping data in a "packed" struct, we are
--- a/src/libdyld/src/image.rs
+++ b/src/libdyld/src/image.rs
@ -3,7 +3,7 @@ use core::{
    mem,
    slice,
 };
-use alloc::alloc::{alloc_zeroed, dealloc, Layout, LayoutError};
+use alloc::alloc::{alloc_zeroed, dealloc, Layout, LayoutErr};
 use super::{
    elf::*,
    Error,
@ -27,7 +27,7 @@ pub struct Image {
 }

 impl Image {
-    pub fn new(size: usize, align: usize) -> Result<Self, LayoutError> {
+    pub fn new(size: usize, align: usize) -> Result<Self, LayoutErr> {
        let layout = Layout::from_size_align(size, align)?;
        let data = unsafe {
            let ptr = alloc_zeroed(layout);
--- a/src/libdyld/src/reloc.rs
+++ b/src/libdyld/src/reloc.rs
@ -77,7 +77,7 @@ impl RelType {

            R_OR1K_32 | R_OR1K_GLOB_DAT | R_OR1K_JMP_SLOT
                if arch == Arch::OpenRisc => Some(RelType::Lookup),
-            R_ARM_GLOB_DAT | R_ARM_JUMP_SLOT | R_ARM_ABS32
+            R_ARM_GLOB_DAT | R_ARM_JUMP_SLOT
                if arch == Arch::Arm => Some(RelType::Lookup),

            _ =>
@ -123,7 +123,7 @@ pub fn relocate<R: Relocatable>(
            if let Some(addr) = lib.lookup(sym_name) {
                // First, try to resolve against itself.
                trace!("looked up symbol {} in image", format_sym_name(sym_name));
-                value = addr;
+                value = lib.image.ptr() as u32 + addr;
            } else if let Some(addr) = resolve(sym_name) {
                // Second, call the user-provided function.
                trace!("resolved symbol {:?}", format_sym_name(sym_name));
--- a/src/libio/Cargo.toml
+++ b/src/libio/Cargo.toml
@ -1,17 +0,0 @@
-[package]
-authors = ["M-Labs"]
-name = "io"
-version = "0.0.0"
-
-[lib]
-name = "io"
-path = "lib.rs"
-
-[dependencies]
-core_io = { version = "0.1", features = ["collections"] }
-byteorder = { version = "1.0", default-features = false, optional = true }
-
-libsupport_zynq = { default-features = false, features = ["alloc_core"], git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
-
-[features]
-alloc = []
--- a/src/libio/cursor.rs
+++ b/src/libio/cursor.rs
@ -1,81 +0,0 @@
-use core_io::{Read, Write, Error as IoError};
-
-#[derive(Debug, Clone)]
-pub struct Cursor<T> {
-    inner: T,
-    pos:   usize
-}
-
-impl<T> Cursor<T> {
-    #[inline]
-    pub fn new(inner: T) -> Cursor<T> {
-        Cursor { inner, pos: 0 }
-    }
-
-    #[inline]
-    pub fn into_inner(self) -> T {
-        self.inner
-    }
-
-    #[inline]
-    pub fn get_ref(&self) -> &T {
-        &self.inner
-    }
-
-    #[inline]
-    pub fn get_mut(&mut self) -> &mut T {
-        &mut self.inner
-    }
-
-    #[inline]
-    pub fn position(&self) -> usize {
-        self.pos
-    }
-
-    #[inline]
-    pub fn set_position(&mut self, pos: usize) {
-        self.pos = pos
-    }
-}
-
-impl<T: AsRef<[u8]>> Read for Cursor<T> {
-
-    fn read(&mut self, buf: &mut [u8]) -> Result<usize, IoError> {
-        let data = &self.inner.as_ref()[self.pos..];
-        let len = buf.len().min(data.len());
-        buf[..len].copy_from_slice(&data[..len]);
-        self.pos += len;
-        Ok(len)
-    }
-}
-
-impl Write for Cursor<&mut [u8]> {
-
-    fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
-        let data = &mut self.inner[self.pos..];
-        let len  = buf.len().min(data.len());
-        data[..len].copy_from_slice(&buf[..len]);
-        self.pos += len;
-        Ok(len)
-    }
-
-    #[inline]
-    fn flush(&mut self) -> Result<(), IoError> {
-        Ok(())
-    }
-}
-
-#[cfg(feature = "alloc")]
-impl Write for Cursor<::alloc::Vec<u8>> {
-
-    #[inline]
-    fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
-        self.inner.extend_from_slice(buf);
-        Ok(buf.len())
-    }
-
-    #[inline]
-    fn flush(&mut self) -> Result<(), IoError> {
-        Ok(())
-    }
-}
--- a/src/libio/lib.rs
+++ b/src/libio/lib.rs
@ -1,22 +0,0 @@
-#![no_std]
-#![feature(never_type)]
-#![cfg_attr(feature = "alloc", feature(alloc))]
-
-extern crate alloc;
-extern crate core_io;
-
-#[cfg(feature = "alloc")]
-#[macro_use]
-use alloc;
-#[cfg(feature = "byteorder")]
-extern crate byteorder;
-
-pub mod cursor;
-#[cfg(feature = "byteorder")]
-pub mod proto;
-
-pub use cursor::Cursor;
-#[cfg(feature = "byteorder")]
-pub use proto::{ProtoRead, ProtoWrite};
-#[cfg(all(feature = "byteorder", feature = "alloc"))]
-pub use proto::ReadStringError;
--- a/src/libunwind/build.rs
+++ b/src/libunwind/build.rs
@ -6,7 +6,6 @@ fn main() {

 mod llvm_libunwind {
    use std::path::Path;
-    use std::env;

    fn setup_options(cfg: &mut cc::Build) {
        cfg.no_default_flags(true);
@ -17,13 +16,9 @@ mod llvm_libunwind {
        cfg.flag("-fno-PIC");
        cfg.flag("-Isrc");
        cfg.flag("-isystem../include");
-        if let Ok(extra_include) = env::var("CLANG_EXTRA_INCLUDE_DIR") {
-            cfg.flag(&("-isystem".to_owned() + &extra_include));
-        }
        cfg.flag("-fno-stack-protector");
        cfg.flag("--target=armv7-none-eabihf");
        cfg.flag("-O2");
-        cfg.flag("-flto");

        cfg.flag("-std=c99");
        cfg.flag("-fstrict-aliasing");
--- a/src/llvm_libunwind/include/unwind.h
+++ b/src/llvm_libunwind/include/unwind.h
@ -107,12 +107,9 @@ struct _Unwind_Control_Block {
 } __attribute__((__aligned__(8)));

 typedef _Unwind_Reason_Code (*_Unwind_Stop_Fn)
-    (int version,
-     _Unwind_Action actions,
-     uint64_t exceptionClass,
-     _Unwind_Exception* exceptionObject,
-     struct _Unwind_Context* context,
-     void* stop_parameter);
+      (_Unwind_State state,
+       _Unwind_Exception* exceptionObject,
+       struct _Unwind_Context* context);

 typedef _Unwind_Reason_Code (*__personality_routine)
      (_Unwind_State state,
--- a/src/llvm_libunwind/src/Unwind-EHABI.cpp
+++ b/src/llvm_libunwind/src/Unwind-EHABI.cpp
@ -95,11 +95,9 @@ _Unwind_Reason_Code ProcessDescriptors(
      case Descriptor::LU32:
        descriptor = getNextWord(descriptor, &length);
        descriptor = getNextWord(descriptor, &offset);
-        break;
      case Descriptor::LU16:
        descriptor = getNextNibble(descriptor, &length);
        descriptor = getNextNibble(descriptor, &offset);
-        break;
      default:
        assert(false);
        return _URC_FAILURE;
@ -185,14 +183,8 @@ static _Unwind_Reason_Code unwindOneFrame(_Unwind_State state,
  if (result != _URC_CONTINUE_UNWIND)
    return result;

-  switch (__unw_step(reinterpret_cast<unw_cursor_t *>(context))) {
-  case UNW_STEP_SUCCESS:
-    return _URC_CONTINUE_UNWIND;
-  case UNW_STEP_END:
-    return _URC_END_OF_STACK;
-  default:
+  if (__unw_step(reinterpret_cast<unw_cursor_t *>(context)) != UNW_STEP_SUCCESS)
    return _URC_FAILURE;
-  }
  return _URC_CONTINUE_UNWIND;
 }

@ -685,128 +677,6 @@ static _Unwind_Reason_Code unwind_phase2(unw_context_t *uc, unw_cursor_t *cursor
  return _URC_FATAL_PHASE2_ERROR;
 }

-static _Unwind_Reason_Code
-unwind_phase2_forced(unw_context_t *uc, unw_cursor_t *cursor,
-                     _Unwind_Exception *exception_object, _Unwind_Stop_Fn stop,
-                     void *stop_parameter) {
-  // See comment at the start of unwind_phase1 regarding VRS integrity.
-  __unw_init_local(cursor, uc);
-
-  _LIBUNWIND_TRACE_UNWINDING("unwind_phase2_forced(ex_ojb=%p)",
-                             static_cast<void *>(exception_object));
-
-  // Walk each frame until we reach where search phase said to stop.
-  bool end_of_stack = false;
-  // TODO: why can't libunwind handle end of stack properly?
-  // We should fix this kind of hack.
-  unw_word_t forced_phase2_prev_sp = 0x0;
-  while (!end_of_stack) {
-    // Get info about this frame.
-    unw_word_t sp;
-    unw_proc_info_t frameInfo;
-    __unw_get_reg(cursor, UNW_REG_SP, &sp);
-    if (sp == forced_phase2_prev_sp) {
-        break;
-    }
-    forced_phase2_prev_sp = sp;
-    if (__unw_get_proc_info(cursor, &frameInfo) != UNW_ESUCCESS) {
-      _LIBUNWIND_TRACE_UNWINDING(
-          "unwind_phase2_forced(ex_ojb=%p): __unw_get_proc_info "
-          "failed => _URC_FATAL_PHASE2_ERROR",
-          static_cast<void *>(exception_object));
-      return _URC_FATAL_PHASE2_ERROR;
-    }
-
-    // When tracing, print state information.
-    if (_LIBUNWIND_TRACING_UNWINDING) {
-      char functionBuf[512];
-      const char *functionName = functionBuf;
-      unw_word_t offset;
-      if ((__unw_get_proc_name(cursor, functionBuf, sizeof(functionBuf),
-                               &offset) != UNW_ESUCCESS) ||
-          (frameInfo.start_ip + offset > frameInfo.end_ip))
-        functionName = ".anonymous.";
-      _LIBUNWIND_TRACE_UNWINDING(
-          "unwind_phase2_forced(ex_ojb=%p): start_ip=0x%" PRIxPTR ", func=%s, sp=0x%" PRIxPTR ", "
-          "lsda=0x%" PRIxPTR ", personality=0x%" PRIxPTR "",
-          static_cast<void *>(exception_object), frameInfo.start_ip,
-          functionName, sp, frameInfo.lsda,
-          frameInfo.handler);
-    }
-
-    _Unwind_Action action =
-        (_Unwind_Action)(_UA_FORCE_UNWIND | _UA_CLEANUP_PHASE);
-    _Unwind_Reason_Code stopResult =
-        (*stop)(1, action, exception_object->exception_class, exception_object,
-                (_Unwind_Context *)(cursor), stop_parameter);
-
-    _LIBUNWIND_TRACE_UNWINDING(
-        "unwind_phase2_forced(ex_ojb=%p): stop function returned %d",
-        (void *)exception_object, stopResult);
-    if (stopResult != _URC_NO_REASON) {
-      _LIBUNWIND_TRACE_UNWINDING(
-          "unwind_phase2_forced(ex_ojb=%p): stopped by stop function",
-          (void *)exception_object);
-      return _URC_FATAL_PHASE2_ERROR;
-    }
-
-    // If there is a personality routine, tell it we are unwinding.
-    if (frameInfo.handler != 0) {
-      __personality_routine p =
-          (__personality_routine)(long)(frameInfo.handler);
-      struct _Unwind_Context *context = (struct _Unwind_Context *)(cursor);
-      // EHABI #7.2
-      exception_object->pr_cache.fnstart = frameInfo.start_ip;
-      exception_object->pr_cache.ehtp =
-          (_Unwind_EHT_Header *)frameInfo.unwind_info;
-      exception_object->pr_cache.additional = frameInfo.flags;
-      _Unwind_Reason_Code personalityResult =
-          (*p)(_US_FORCE_UNWIND | _US_UNWIND_FRAME_STARTING, exception_object,
-              context);
-      switch (personalityResult) {
-      case _URC_CONTINUE_UNWIND:
-        // Continue unwinding
-        _LIBUNWIND_TRACE_UNWINDING(
-            "unwind_phase2_forced(ex_ojb=%p): _URC_CONTINUE_UNWIND",
-            static_cast<void *>(exception_object));
-        break;
-      case _URC_INSTALL_CONTEXT:
-        _LIBUNWIND_TRACE_UNWINDING(
-            "unwind_phase2_forced(ex_ojb=%p): _URC_INSTALL_CONTEXT",
-            static_cast<void *>(exception_object));
-        {
-          // EHABI #7.4.1 says we need to preserve pc for when _Unwind_Resume
-          // is called back, to find this same frame.
-          unw_word_t pc;
-          __unw_get_reg(cursor, UNW_REG_IP, &pc);
-          exception_object->unwinder_cache.reserved2 = (uint32_t)pc;
-        }
-        // We may get control back if landing pad calls _Unwind_Resume().
-        __unw_resume(cursor);
-        break;
-      case _URC_END_OF_STACK:
-        end_of_stack = true;
-        break;
-      default:
-        // Personality routine returned an unknown result code.
-        _LIBUNWIND_DEBUG_LOG("personality function returned unknown result %d",
-                      personalityResult);
-        return _URC_FATAL_PHASE2_ERROR;
-      }
-    }
-  }
-  _LIBUNWIND_TRACE_UNWINDING("unwind_phase2_forced(ex_ojb=%p): calling stop "
-                             "function with _UA_END_OF_STACK",
-                             (void *)exception_object);
-  _Unwind_Action lastAction =
-      (_Unwind_Action)(_UA_FORCE_UNWIND | _UA_CLEANUP_PHASE | _UA_END_OF_STACK);
-  (*stop)(1, lastAction, exception_object->exception_class, exception_object,
-          (struct _Unwind_Context *)(cursor), stop_parameter);
-  return _URC_FATAL_PHASE2_ERROR;
-}
-
-
-
 /// Called by __cxa_throw.  Only returns if there is a fatal error.
 _LIBUNWIND_EXPORT _Unwind_Reason_Code
 _Unwind_RaiseException(_Unwind_Exception *exception_object) {
@ -854,36 +724,15 @@ _Unwind_Resume(_Unwind_Exception *exception_object) {
  unw_cursor_t cursor;
  __unw_getcontext(&uc);

-  if (exception_object->unwinder_cache.reserved1)
-    unwind_phase2_forced(
-        &uc, &cursor, exception_object,
-        (_Unwind_Stop_Fn)exception_object->unwinder_cache.reserved1,
-        (void *)exception_object->unwinder_cache.reserved3);
-  else
-    unwind_phase2(&uc, &cursor, exception_object, true);
+  // _Unwind_RaiseException on EHABI will always set the reserved1 field to 0,
+  // which is in the same position as private_1 below.
+  // TODO(ajwong): Who wronte the above? Why is it true?
+  unwind_phase2(&uc, &cursor, exception_object, true);

  // Clients assume _Unwind_Resume() does not return, so all we can do is abort.
  _LIBUNWIND_ABORT("_Unwind_Resume() can't return");
 }

-_LIBUNWIND_EXPORT _Unwind_Reason_Code
-_Unwind_ForcedUnwind(_Unwind_Exception *exception_object, _Unwind_Stop_Fn stop,
-                     void *stop_parameter) {
-  _LIBUNWIND_TRACE_API("_Unwind_ForcedUnwind(ex_obj=%p, stop=%p)",
-                       (void *)exception_object, (void *)(uintptr_t)stop);
-  unw_context_t uc;
-  unw_cursor_t cursor;
-  __unw_getcontext(&uc);
-
-  // Mark that this is a forced unwind, so _Unwind_Resume() can do
-  // the right thing.
-  exception_object->unwinder_cache.reserved1 = (uintptr_t)stop;
-  exception_object->unwinder_cache.reserved3 = (uintptr_t)stop_parameter;
-
-  return unwind_phase2_forced(&uc, &cursor, exception_object, stop,
-                              stop_parameter);
-}
-
 /// Called by personality handler during phase 2 to get LSDA for current frame.
 _LIBUNWIND_EXPORT uintptr_t
 _Unwind_GetLanguageSpecificData(struct _Unwind_Context *context) {
@ -1153,14 +1002,9 @@ extern "C" _LIBUNWIND_EXPORT _Unwind_Reason_Code
 __gnu_unwind_frame(_Unwind_Exception *exception_object,
                   struct _Unwind_Context *context) {
  unw_cursor_t *cursor = (unw_cursor_t *)context;
-  switch (__unw_step(cursor)) {
-  case UNW_STEP_SUCCESS:
-    return _URC_OK;
-  case UNW_STEP_END:
-    return _URC_END_OF_STACK;
-  default:
+  if (__unw_step(cursor) != UNW_STEP_SUCCESS)
    return _URC_FAILURE;
-  }
+  return _URC_OK;
 }

 #endif  // defined(_LIBUNWIND_ARM_EHABI)
--- a/src/runtime/Cargo.toml
+++ b/src/runtime/Cargo.toml
@ -6,13 +6,9 @@ authors = ["M-Labs"]
 edition = "2018"

 [features]
-target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706", "libboard_artiq/target_zc706"]
-target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc", "libboard_artiq/target_kasli_soc"]
+target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
 default = ["target_zc706"]

-[build-dependencies]
-build_zynq = { path = "../libbuild_zynq" }
-
 [dependencies]
 num-traits = { version = "0.2", default-features = false }
 num-derive = "0.3"
@ -34,11 +30,9 @@ libsupport_zynq = { default-features = false, features = ["alloc_core"], git = "
 libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
 libasync = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
 libregister = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
-libconfig = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["ipv6"] }

 dyld = { path = "../libdyld" }
 dwarf = { path = "../libdwarf" }
 unwind = { path = "../libunwind" }
 libc = { path = "../libc" }
-io = { path = "../libio" }
-libboard_artiq = { path = "../libboard_artiq" }
+libconfig = { path = "../libconfig", features = ["ipv6"]}
--- a/src/runtime/build.rs
+++ b/src/runtime/build.rs
@ -1,6 +1,28 @@
-extern crate build_zynq;
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::io::{BufRead, BufReader};
+use std::path::PathBuf;

 fn main() {
-    build_zynq::add_linker_script();
-    build_zynq::cfg();
+    // Put the linker script somewhere the linker can find it
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("link.x"))
+        .unwrap()
+        .write_all(include_bytes!("link.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+
+    // Only re-run the build script when link.x is changed,
+    // instead of when any part of the source code changes.
+    println!("cargo:rerun-if-changed=link.x");
+
+    // Handle rustc-cfg file
+    let cfg_path = "../../build/rustc-cfg";
+    println!("cargo:rerun-if-changed={}", cfg_path);
+
+    let f = BufReader::new(File::open(cfg_path).unwrap());
+    for line in f.lines() {
+        println!("cargo:rustc-cfg={}", line.unwrap());
+    }
 }
--- a/src/libbuild_zynq/link.x
+++ b/src/libbuild_zynq/link.x
@ -69,18 +69,4 @@ SECTIONS
        . += 0x20000;
        __stack0_start = .;
    } > SDRAM
-
-    .irq_stack1 (NOLOAD) : ALIGN(8)
-    {
-        __irq_stack1_end = .;
-        . += 0x100;
-        __irq_stack1_start = .;
-    } > SDRAM
-
-    .irq_stack0 (NOLOAD) : ALIGN(8)
-    {
-        __irq_stack0_end = .;
-        . += 0x100;
-        __irq_stack0_start = .;
-    } > SDRAM
 }
--- a/src/runtime/src/analyzer.rs
+++ b/src/runtime/src/analyzer.rs
@ -50,7 +50,6 @@ struct Header {
 }

 async fn write_header(stream: &mut TcpStream, header: &Header) -> Result<(), Error> {
-    stream.send_slice("e".as_bytes()).await?;
    write_i32(stream, header.sent_bytes as i32).await?;
    write_i64(stream, header.total_byte_count as i64).await?;
    write_i8(stream, header.error_occurred as i8).await?;
--- a/src/runtime/src/comms.rs
+++ b/src/runtime/src/comms.rs
@ -1,8 +1,8 @@
 use core::fmt;
 use core::cell::RefCell;
+use core::str::Utf8Error;
 use alloc::{vec, vec::Vec, string::String, collections::BTreeMap, rc::Rc};
 use log::{info, warn, error};
-use cslice::CSlice;

 use num_derive::{FromPrimitive, ToPrimitive};
 use num_traits::{FromPrimitive, ToPrimitive};
@ -21,7 +21,6 @@ use libcortex_a9::{semaphore::Semaphore, mutex::Mutex, sync_channel::{Sender, Re
 use futures::{select_biased, future::FutureExt};
 use libasync::{smoltcp::{Sockets, TcpStream}, task};
 use libconfig::{Config, net_settings};
-use libboard_artiq::drtio_routing;

 use crate::proto_async::*;
 use crate::kernel;
@ -29,9 +28,7 @@ use crate::rpc;
 use crate::moninj;
 use crate::mgmt;
 use crate::analyzer;
-use crate::rtio_mgt;
-#[cfg(has_drtio)]
-use crate::pl;
+

 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
 pub enum Error {
@ -39,6 +36,7 @@ pub enum Error {
    UnexpectedPattern,
    UnrecognizedPacket,
    BufferExhausted,
+    Utf8Error(Utf8Error),
 }

 pub type Result<T> = core::result::Result<T, Error>;
@ -50,6 +48,7 @@ impl fmt::Display for Error {
            Error::UnexpectedPattern   => write!(f, "unexpected pattern"),
            Error::UnrecognizedPacket  => write!(f, "unrecognized packet"),
            Error::BufferExhausted     => write!(f, "buffer exhausted"),
+            Error::Utf8Error(error)    => write!(f, "UTF-8 error: {}", error),
        }
    }
 }
@ -95,13 +94,13 @@ async fn read_request(stream: &TcpStream, allow_close: bool) -> Result<Option<Re
        Ok(true) => {}
        Ok(false) =>
            return Err(Error::UnexpectedPattern),
-        Err(smoltcp::Error::Finished) => {
+        Err(smoltcp::Error::Illegal) => {
            if allow_close {
                info!("peer closed connection");
                return Ok(None);
            } else {
                error!("peer unexpectedly closed connection");
-                return Err(smoltcp::Error::Finished)?;
+                return Err(smoltcp::Error::Illegal)?;
            }
        },
        Err(e) =>
@ -120,6 +119,11 @@ async fn read_bytes(stream: &TcpStream, max_length: usize) -> Result<Vec<u8>> {
    Ok(buffer)
 }

+async fn read_string(stream: &TcpStream, max_length: usize) -> Result<String> {
+    let bytes = read_bytes(stream, max_length).await?;
+    Ok(String::from_utf8(bytes).map_err(|err| Error::Utf8Error(err.utf8_error()))?)
+}
+
 const RETRY_LIMIT: usize = 100;

 async fn fast_send(sender: &mut Sender<'_, kernel::Message>, content: kernel::Message) {
@ -149,16 +153,6 @@ async fn fast_recv(receiver: &mut Receiver<'_, kernel::Message>) -> kernel::Mess
    receiver.async_recv().await
 }

-async fn write_exception_string(stream: &TcpStream, s: CSlice<'static, u8>) -> Result<()> {
-    if s.len() == usize::MAX {
-        write_i32(stream, -1).await?;
-        write_i32(stream, s.as_ptr() as i32).await?
-    } else {
-        write_chunk(stream, s.as_ref()).await?;
-    };
-    Ok(())
-}
-
 async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kernel::Control>>) -> Result<()> {
    control.borrow_mut().tx.async_send(kernel::Message::StartRequest).await;
    loop {
@ -207,17 +201,17 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
                                kernel::Message::RpcRecvRequest(_) => (),
                                other => panic!("expected (ignored) root value slot from kernel CPU, not {:?}", other),
                            }
-                            let id =       read_i32(stream).await? as u32;
-                            let message =  read_i32(stream).await? as u32;
+                            let name =     read_string(stream, 16384).await?;
+                            let message =  read_string(stream, 16384).await?;
                            let param =    [read_i64(stream).await?,
                                            read_i64(stream).await?,
                                            read_i64(stream).await?];
-                            let file =     read_i32(stream).await? as u32;
+                            let file =     read_string(stream, 16384).await?;
                            let line =     read_i32(stream).await?;
                            let column =   read_i32(stream).await?;
-                            let function = read_i32(stream).await? as u32;
+                            let function = read_string(stream, 16384).await?;
                            control.tx.async_send(kernel::Message::RpcRecvReply(Err(kernel::RPCException {
-                                id, message, param, file, line, column, function
+                                name, message, param, file, line, column, function
                            }))).await;
                        },
                        _ => {
@ -227,46 +221,34 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
                    }
                }
            },
-            kernel::Message::KernelFinished(async_errors) => {
+            kernel::Message::KernelFinished => {
                if let Some(stream) = stream {
                    write_header(stream, Reply::KernelFinished).await?;
-                    write_i8(stream, async_errors as i8).await?;
                }
                break;
            },
-            kernel::Message::KernelException(exceptions, stack_pointers, backtrace, async_errors) => {
+            kernel::Message::KernelException(exception, backtrace) => {
                match stream {
                    Some(stream) => {
                        // only send the exception data to host if there is host,
                        // i.e. not idle/startup kernel.
                        write_header(stream, Reply::KernelException).await?;
-                        write_i32(stream, exceptions.len() as i32).await?;
-                        for exception in exceptions.iter() {
-                            let exception = exception.as_ref().unwrap();
-                            write_i32(stream, exception.id as i32).await?;
-                            write_exception_string(stream, exception.message).await?;
-                            write_i64(stream, exception.param[0] as i64).await?;
-                            write_i64(stream, exception.param[1] as i64).await?;
-                            write_i64(stream, exception.param[2] as i64).await?;
-                            write_exception_string(stream, exception.file).await?;
-                            write_i32(stream, exception.line as i32).await?;
-                            write_i32(stream, exception.column as i32).await?;
-                            write_exception_string(stream, exception.function).await?;
-                        }
-                        for sp in stack_pointers.iter() {
-                            write_i32(stream, sp.stack_pointer as i32).await?;
-                            write_i32(stream, sp.initial_backtrace_size as i32).await?;
-                            write_i32(stream, sp.current_backtrace_size as i32).await?;
-                        }
+                        write_chunk(stream, exception.name.as_ref()).await?;
+                        write_chunk(stream, exception.message.as_ref()).await?;
+                        write_i64(stream, exception.param[0] as i64).await?;
+                        write_i64(stream, exception.param[1] as i64).await?;
+                        write_i64(stream, exception.param[2] as i64).await?;
+                        write_chunk(stream, exception.file.as_ref()).await?;
+                        write_i32(stream, exception.line as i32).await?;
+                        write_i32(stream, exception.column as i32).await?;
+                        write_chunk(stream, exception.function.as_ref()).await?;
                        write_i32(stream, backtrace.len() as i32).await?;
-                        for &(addr, sp) in backtrace {
+                        for &addr in backtrace {
                            write_i32(stream, addr as i32).await?;
-                            write_i32(stream, sp as i32).await?;
                        }
-                        write_i8(stream, async_errors as i8).await?;
                    },
                    None => {
-                        error!("Uncaught kernel exceptions: {:?}", exceptions);
+                        error!("Uncaught kernel exception: {:?}", exception);
                    }
                }
                break;
@ -331,13 +313,10 @@ async fn load_kernel(buffer: &Vec<u8>, control: &Rc<RefCell<kernel::Control>>, s
    }
 }

-async fn handle_connection(stream: &mut TcpStream, control: Rc<RefCell<kernel::Control>>) -> Result<()> {
-    stream.set_ack_delay(None);
-
+async fn handle_connection(stream: &TcpStream, control: Rc<RefCell<kernel::Control>>) -> Result<()> {
    if !expect(stream, b"ARTIQ coredev\n").await? {
        return Err(Error::UnexpectedPattern);
    }
-    stream.send_slice("e".as_bytes()).await?;
    loop {
        let request = read_request(stream, true).await?;
        if request.is_none() {
@ -364,8 +343,8 @@ async fn handle_connection(stream: &mut TcpStream, control: Rc<RefCell<kernel::C
    }
 }

-pub fn main(timer: GlobalTimer, cfg: Config) {
-    let net_addresses = net_settings::get_adresses(&cfg);
+pub fn main(timer: GlobalTimer, cfg: &Config) {
+    let net_addresses = net_settings::get_adresses(cfg);
    info!("network addresses: {}", net_addresses);

    let eth = zynq::eth::Eth::eth0(net_addresses.hardware_addr.0.clone());
@ -405,21 +384,9 @@ pub fn main(timer: GlobalTimer, cfg: Config) {

    Sockets::init(32);

-    // before, mutex was on io, but now that io isn't used...?
-    let aux_mutex: Rc<Mutex<bool>> = Rc::new(Mutex::new(false));
-    #[cfg(has_drtio)]
-    let drtio_routing_table = Rc::new(RefCell::new(
-        drtio_routing::config_routing_table(pl::csr::DRTIO.len(), &cfg)));
-    #[cfg(not(has_drtio))]
-    let drtio_routing_table = Rc::new(RefCell::new(drtio_routing::RoutingTable::default_empty()));
-    let up_destinations = Rc::new(RefCell::new([false; drtio_routing::DEST_COUNT]));
-    #[cfg(has_drtio_routing)]
-    drtio_routing::interconnect_disable_all();
-
-    rtio_mgt::startup(&aux_mutex, &drtio_routing_table, &up_destinations, timer);
-
+    mgmt::start();
    analyzer::start();
-    moninj::start(timer, aux_mutex, drtio_routing_table);
+    moninj::start(timer);

    let control: Rc<RefCell<kernel::Control>> = Rc::new(RefCell::new(kernel::Control::start()));
    let idle_kernel = Rc::new(cfg.read("idle").ok());
@ -434,13 +401,11 @@ pub fn main(timer: GlobalTimer, cfg: Config) {
        }
    }

-    mgmt::start(cfg);
-
    task::spawn(async move {
        let connection = Rc::new(Semaphore::new(1, 1));
        let terminate = Rc::new(Semaphore::new(0, 1));
        loop {
-            let mut stream = TcpStream::accept(1381, 0x10_000, 0x10_000).await.unwrap();
+            let stream = TcpStream::accept(1381, 0x10_000, 0x10_000).await.unwrap();

            if connection.try_wait().is_none() {
                // there is an existing connection
@ -458,16 +423,16 @@ pub fn main(timer: GlobalTimer, cfg: Config) {
            task::spawn(async move {
                select_biased! {
                    _ = (async {
-                        let _ = handle_connection(&mut stream, control.clone())
+                        let _ = handle_connection(&stream, control.clone())
                            .await
                            .map_err(|e| warn!("connection terminated: {}", e));
                        if let Some(buffer) = &*idle_kernel {
                            info!("Loading idle kernel");
                            let _ = load_kernel(&buffer, &control, None)
-                                .await.map_err(|_| warn!("error loading idle kernel"));
+                                .await.map_err(|e| warn!("error loading idle kernel"));
                            info!("Running idle kernel");
                            let _ = handle_run_kernel(None, &control)
-                                .await.map_err(|_| warn!("error running idle kernel"));
+                                .await.map_err(|e| warn!("error running idle kernel"));
                            info!("Idle kernel terminated");
                        }
                    }).fuse() => (),
--- a/src/runtime/src/eh_artiq.rs
+++ b/src/runtime/src/eh_artiq.rs
@ -15,9 +15,8 @@
 use core::mem;
 use cslice::CSlice;
 use unwind as uw;
-use libc::{c_int, c_void, uintptr_t};
-use log::{trace, error};
-use crate::kernel::KERNEL_IMAGE;
+use libc::{c_int, uintptr_t};
+use log::trace;

 use dwarf::eh::{self, EHAction, EHContext};

@ -27,12 +26,10 @@ const EXCEPTION_CLASS: uw::_Unwind_Exception_Class = 0x4d_4c_42_53_41_52_54_51;
 #[cfg(target_arch = "arm")]
 const UNWIND_DATA_REG: (i32, i32) = (0, 1); // R0, R1

-// Note: CSlice within an exception may not be actual cslice, they may be strings that exist only
-// in the host. If the length == usize:MAX, the pointer is actually a string key in the host.
 #[repr(C)]
 #[derive(Clone, Copy)]
 pub struct Exception<'a> {
-    pub id:       u32,
+    pub name:     CSlice<'a, u8>,
    pub file:     CSlice<'a, u8>,
    pub line:     u32,
    pub column:   u32,
@ -45,100 +42,31 @@ fn str_err(_: core::str::Utf8Error) -> core::fmt::Error {
    core::fmt::Error
 }

-fn exception_str<'a>(s: &'a CSlice<'a, u8>) -> Result<&'a str, core::str::Utf8Error> {
-    if s.len() == usize::MAX {
-        Ok("<host string>")
-    } else {
-        core::str::from_utf8(s.as_ref())
-    }
-}
-
 impl<'a> core::fmt::Debug for Exception<'a> {
    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
        write!(f, "Exception {} from {} in {}:{}:{}, message: {}",
-            self.id,
-            exception_str(&self.function).map_err(str_err)?,
-            exception_str(&self.file).map_err(str_err)?,
+            core::str::from_utf8(self.name.as_ref()).map_err(str_err)?,
+            core::str::from_utf8(self.function.as_ref()).map_err(str_err)?,
+            core::str::from_utf8(self.file.as_ref()).map_err(str_err)?,
            self.line, self.column,
-            exception_str(&self.message).map_err(str_err)?)
+            core::str::from_utf8(self.message.as_ref()).map_err(str_err)?)
    }
 }

-const MAX_INFLIGHT_EXCEPTIONS: usize = 10;
 const MAX_BACKTRACE_SIZE: usize = 128;

-#[derive(Debug, Default)]
-pub struct StackPointerBacktrace {
-    pub stack_pointer: usize,
-    pub initial_backtrace_size: usize,
-    pub current_backtrace_size: usize,
-}
-
-struct ExceptionBuffer {
-    // we need n _Unwind_Exception, because each will have their own private data
-    uw_exceptions: [uw::_Unwind_Exception; MAX_INFLIGHT_EXCEPTIONS],
-    exceptions: [Option<Exception<'static>>; MAX_INFLIGHT_EXCEPTIONS + 1],
-    exception_stack: [isize; MAX_INFLIGHT_EXCEPTIONS + 1],
-    // nested exceptions will share the backtrace buffer, treated as a tree
-    // backtrace contains a tuple of IP and SP
-    backtrace: [(usize, usize); MAX_BACKTRACE_SIZE],
-    backtrace_size: usize,
-    // stack pointers are stored to reconstruct backtrace for each exception
-    stack_pointers: [StackPointerBacktrace; MAX_INFLIGHT_EXCEPTIONS + 1],
-    // current allocated nested exceptions
-    exception_count: usize,
-}
-
-static mut EXCEPTION_BUFFER: ExceptionBuffer = ExceptionBuffer {
-    uw_exceptions: [uw::_Unwind_Exception {
-        exception_class:   EXCEPTION_CLASS,
-        exception_cleanup: cleanup,
-        private:           [0; uw::unwinder_private_data_size],
-    }; MAX_INFLIGHT_EXCEPTIONS],
-    exceptions: [None; MAX_INFLIGHT_EXCEPTIONS + 1],
-    exception_stack: [-1; MAX_INFLIGHT_EXCEPTIONS + 1],
-    backtrace: [(0, 0); MAX_BACKTRACE_SIZE],
-    backtrace_size: 0,
-    stack_pointers: [StackPointerBacktrace {
-        stack_pointer: 0,
-        initial_backtrace_size: 0,
-        current_backtrace_size: 0
-    }; MAX_INFLIGHT_EXCEPTIONS + 1],
-    exception_count: 0
-};
-
-pub unsafe extern fn reset_exception_buffer() {
-    trace!("reset exception buffer");
-    EXCEPTION_BUFFER.uw_exceptions = [uw::_Unwind_Exception {
-        exception_class:   EXCEPTION_CLASS,
-        exception_cleanup: cleanup,
-        private:           [0; uw::unwinder_private_data_size],
-    }; MAX_INFLIGHT_EXCEPTIONS];
-    EXCEPTION_BUFFER.exceptions = [None; MAX_INFLIGHT_EXCEPTIONS + 1];
-    EXCEPTION_BUFFER.exception_stack = [-1; MAX_INFLIGHT_EXCEPTIONS + 1];
-    EXCEPTION_BUFFER.backtrace_size = 0;
-    EXCEPTION_BUFFER.exception_count = 0;
-}
-
-type _Unwind_Stop_Fn = extern "C" fn(version: c_int,
-                                     actions: i32,
-                                     exception_class: uw::_Unwind_Exception_Class,
-                                     exception_object: *mut uw::_Unwind_Exception,
-                                     context: *mut uw::_Unwind_Context,
-                                     stop_parameter: *mut c_void)
-                                    -> uw::_Unwind_Reason_Code;
-
-extern {
-    // not defined in EHABI, but LLVM added it and is useful to us
-    fn _Unwind_ForcedUnwind(exception: *mut uw::_Unwind_Exception,
-                            stop_fn: _Unwind_Stop_Fn,
-                            stop_parameter: *mut c_void) -> uw::_Unwind_Reason_Code;
+#[repr(C)]
+struct ExceptionInfo {
+    uw_exception:   uw::_Unwind_Exception,
+    exception:      Option<Exception<'static>>,
+    handled:        bool,
+    backtrace:      [usize; MAX_BACKTRACE_SIZE],
+    backtrace_size: usize
 }

 unsafe fn find_eh_action(
    context: *mut uw::_Unwind_Context,
    foreign_exception: bool,
-    id: u32,
 ) -> Result<EHAction, ()> {
    let lsda = uw::_Unwind_GetLanguageSpecificData(context) as *const u8;
    let mut ip_before_instr: c_int = 0;
@ -151,14 +79,32 @@ unsafe fn find_eh_action(
        get_text_start: &|| uw::_Unwind_GetTextRelBase(context),
        get_data_start: &|| uw::_Unwind_GetDataRelBase(context),
    };
-    eh::find_eh_action(lsda, &eh_context, foreign_exception, id)
+    eh::find_eh_action(lsda, &eh_context, foreign_exception)
 }

-pub unsafe fn artiq_personality(_state: uw::_Unwind_State,
-                                exception_object: *mut uw::_Unwind_Exception,
-                                context: *mut uw::_Unwind_Context)
-                                -> uw::_Unwind_Reason_Code {
-    // we will only do phase 2 forced unwinding now
+pub unsafe fn artiq_personality(state: uw::_Unwind_State,
+                                         exception_object: *mut uw::_Unwind_Exception,
+                                         context: *mut uw::_Unwind_Context)
+                                         -> uw::_Unwind_Reason_Code {
+    let state = state as c_int;
+    let action = state & uw::_US_ACTION_MASK as c_int;
+    let search_phase = if action == uw::_US_VIRTUAL_UNWIND_FRAME as c_int {
+        // Backtraces on ARM will call the personality routine with
+        // state == _US_VIRTUAL_UNWIND_FRAME | _US_FORCE_UNWIND. In those cases
+        // we want to continue unwinding the stack, otherwise all our backtraces
+        // would end at __rust_try
+        if state & uw::_US_FORCE_UNWIND as c_int != 0 {
+            return continue_unwind(exception_object, context);
+        }
+        true
+    } else if action == uw::_US_UNWIND_FRAME_STARTING as c_int {
+        false
+    } else if action == uw::_US_UNWIND_FRAME_RESUME as c_int {
+        return continue_unwind(exception_object, context);
+    } else {
+        return uw::_URC_FAILURE;
+    };
+
    // The DWARF unwinder assumes that _Unwind_Context holds things like the function
    // and LSDA pointers, however ARM EHABI places them into the exception object.
    // To preserve signatures of functions like _Unwind_GetLanguageSpecificData(), which
@ -174,27 +120,45 @@ pub unsafe fn artiq_personality(_state: uw::_Unwind_State,

    let exception_class = (*exception_object).exception_class;
    let foreign_exception = exception_class != EXCEPTION_CLASS;
-    assert!(!foreign_exception, "we do not expect foreign exceptions");
-    let index = EXCEPTION_BUFFER.exception_stack[EXCEPTION_BUFFER.exception_count - 1];
-    assert!(index != -1);
-    let exception = EXCEPTION_BUFFER.exceptions[index as usize].as_ref().unwrap();
-
-    let id = exception.id;
-    let eh_action = match find_eh_action(context, foreign_exception, id) {
+    let eh_action = match find_eh_action(context, foreign_exception) {
        Ok(action) => action,
        Err(_) => return uw::_URC_FAILURE,
    };
-    match eh_action {
-        EHAction::None => return continue_unwind(exception_object, context),
-        EHAction::Cleanup(lpad) |
-        EHAction::Catch(lpad) => {
-            uw::_Unwind_SetGR(context, UNWIND_DATA_REG.0,
-                              exception_object as uintptr_t);
-            uw::_Unwind_SetGR(context, UNWIND_DATA_REG.1, exception as *const _ as uw::_Unwind_Word);
-            uw::_Unwind_SetIP(context, lpad);
-            return uw::_URC_INSTALL_CONTEXT;
+    let exception_info = &mut *(exception_object as *mut ExceptionInfo);
+    let exception = &exception_info.exception.unwrap();
+    if search_phase {
+        match eh_action {
+            EHAction::None => return continue_unwind(exception_object, context),
+            // Actually, cleanup should not return handler found, this is to workaround
+            // the issue of terminating directly when no catch cause is found while
+            // having some cleanup routines defined by finally.
+            // The best way to handle this is to force unwind the stack in the raise
+            // function when end of stack is reached, and call terminate at the end of
+            // the unwind. Unfortunately, there is no forced unwind function defined
+            // for EHABI, and I have no idea how to implement that, so this is a hack.
+            EHAction::Cleanup(_) => return uw::_URC_HANDLER_FOUND,
+            EHAction::Catch(_) => {
+                // EHABI requires the personality routine to update the
+                // SP value in the barrier cache of the exception object.
+                (*exception_object).private[5] =
+                    uw::_Unwind_GetGR(context, uw::UNWIND_SP_REG);
+                return uw::_URC_HANDLER_FOUND;
+            }
+            EHAction::Terminate => return uw::_URC_FAILURE,
+        }
+    } else {
+        match eh_action {
+            EHAction::None => return continue_unwind(exception_object, context),
+            EHAction::Cleanup(lpad) |
+            EHAction::Catch(lpad) => {
+                uw::_Unwind_SetGR(context, UNWIND_DATA_REG.0,
+                                  exception_object as uintptr_t);
+                uw::_Unwind_SetGR(context, UNWIND_DATA_REG.1, exception as *const _ as uw::_Unwind_Word);
+                uw::_Unwind_SetIP(context, lpad);
+                return uw::_URC_INSTALL_CONTEXT;
+            }
+            EHAction::Terminate => return uw::_URC_FAILURE,
        }
-        EHAction::Terminate => return uw::_URC_FAILURE,
    }

    // On ARM EHABI the personality routine is responsible for actually
@ -202,11 +166,10 @@ pub unsafe fn artiq_personality(_state: uw::_Unwind_State,
    unsafe fn continue_unwind(exception_object: *mut uw::_Unwind_Exception,
                              context: *mut uw::_Unwind_Context)
                              -> uw::_Unwind_Reason_Code {
-        let reason = __gnu_unwind_frame(exception_object, context);
-        if reason == uw::_URC_NO_REASON {
+        if __gnu_unwind_frame(exception_object, context) == uw::_URC_NO_REASON {
            uw::_URC_CONTINUE_UNWIND
        } else {
-            reason
+            uw::_URC_FAILURE
        }
    }
    // defined in libgcc
@ -217,223 +180,74 @@ pub unsafe fn artiq_personality(_state: uw::_Unwind_State,
    }
 }

+extern fn cleanup(_unwind_code: uw::_Unwind_Reason_Code,
+                  uw_exception: *mut uw::_Unwind_Exception) {
+    unsafe {
+        let exception_info = &mut *(uw_exception as *mut ExceptionInfo);
+
+        exception_info.exception = None;
+    }
+}
+
+static mut INFLIGHT: ExceptionInfo = ExceptionInfo {
+    uw_exception: uw::_Unwind_Exception {
+        exception_class:   EXCEPTION_CLASS,
+        exception_cleanup: cleanup,
+        private:           [0; uw::unwinder_private_data_size],
+    },
+    exception:      None,
+    handled:        true,
+    backtrace:      [0; MAX_BACKTRACE_SIZE],
+    backtrace_size: 0
+};
+
 pub unsafe extern fn raise(exception: *const Exception) -> ! {
+    trace!("Trying to raise exception");
+    // FIXME: unsound transmute
+    // This would cause stack memory corruption.
+    INFLIGHT.exception = Some(mem::transmute::<Exception, Exception<'static>>(*exception));
+    INFLIGHT.handled   = false;
+
+    let result = uw::_Unwind_RaiseException(&mut INFLIGHT.uw_exception);
+    assert!(result == uw::_URC_END_OF_STACK);
+
+    INFLIGHT.backtrace_size = 0;
+    // read backtrace
+    let _ = uw::backtrace(|ip| {
+        if INFLIGHT.backtrace_size < MAX_BACKTRACE_SIZE {
+            INFLIGHT.backtrace[INFLIGHT.backtrace_size] = ip;
+            INFLIGHT.backtrace_size += 1;
+        }
+    });
+    crate::kernel::core1::terminate(INFLIGHT.exception.as_ref().unwrap(), INFLIGHT.backtrace[..INFLIGHT.backtrace_size].as_mut());
+}
+
+pub unsafe extern fn reraise() -> ! {
    use cslice::AsCSlice;

-    let count = EXCEPTION_BUFFER.exception_count;
-    let stack = &mut EXCEPTION_BUFFER.exception_stack;
-    let diff = exception as isize - EXCEPTION_BUFFER.exceptions.as_ptr() as isize;
-    if 0 <= diff && diff <= (mem::size_of::<Option<Exception>>() * MAX_INFLIGHT_EXCEPTIONS) as isize {
-        let index = diff / (mem::size_of::<Option<Exception>>() as isize);
-        trace!("reraise at {}", index);
-
-        let mut found = false;
-        for i in 0..=MAX_INFLIGHT_EXCEPTIONS + 1 {
-            if found {
-                if stack[i] == -1 {
-                    stack[i - 1] = index;
-                    assert!(i == count);
-                    break;
-                } else {
-                    stack[i - 1] = stack[i];
-                }
-            } else {
-                if stack[i] == index {
-                    found = true;
-                }
-            }
-        }
-        assert!(found);
-        let _result = _Unwind_ForcedUnwind(&mut EXCEPTION_BUFFER.uw_exceptions[stack[count - 1] as usize],
-                                           stop_fn, core::ptr::null_mut());
-    } else {
-        if count < MAX_INFLIGHT_EXCEPTIONS {
-            trace!("raising exception at level {}", count);
-            let exception = &*exception;
-            for (i, slot) in EXCEPTION_BUFFER.exceptions.iter_mut().enumerate() {
-                // we should always be able to find a slot
-                if slot.is_none() {
-                    *slot = Some(
-                        *mem::transmute::<*const Exception, *const Exception<'static>>
-                        (exception));
-                    EXCEPTION_BUFFER.exception_stack[count] = i as isize;
-                    EXCEPTION_BUFFER.uw_exceptions[i].private =
-                        [0; uw::unwinder_private_data_size];
-                    EXCEPTION_BUFFER.stack_pointers[i] = StackPointerBacktrace {
-                        stack_pointer: 0,
-                        initial_backtrace_size: EXCEPTION_BUFFER.backtrace_size,
-                        current_backtrace_size: 0,
-                    };
-                    EXCEPTION_BUFFER.exception_count += 1;
-                    let _result = _Unwind_ForcedUnwind(&mut EXCEPTION_BUFFER.uw_exceptions[i],
-                                                       stop_fn, core::ptr::null_mut());
-                }
-            }
-        } else {
-            error!("too many nested exceptions");
-            // TODO: better reporting?
-            let exception = Exception {
-                id:       get_exception_id("RuntimeError"),
-                file:     file!().as_c_slice(),
-                line:     line!(),
-                column:   column!(),
-                // https://github.com/rust-lang/rfcs/pull/1719
-                function: "__artiq_raise".as_c_slice(),
-                message:  "too many nested exceptions".as_c_slice(),
-                param:    [0, 0, 0]
-            };
-            EXCEPTION_BUFFER.exceptions[MAX_INFLIGHT_EXCEPTIONS] = Some(mem::transmute(exception));
-            EXCEPTION_BUFFER.stack_pointers[MAX_INFLIGHT_EXCEPTIONS] = Default::default();
-            EXCEPTION_BUFFER.exception_count += 1;
-            uncaught_exception()
-        }
+    // Reraise is basically cxa_rethrow, which calls _Unwind_Resume_or_Rethrow,
+    // which for EHABI would always call _Unwind_RaiseException.
+    match INFLIGHT.exception {
+        Some(ref exception) => raise(exception),
+        None => raise(&Exception {
+            name:     "0:artiq.coredevice.exceptions.RuntimeError".as_c_slice(),
+            file:     file!().as_c_slice(),
+            line:     line!(),
+            column:   column!(),
+            // https://github.com/rust-lang/rfcs/pull/1719
+            function: "__artiq_reraise".as_c_slice(),
+            message:  "No active exception to reraise".as_c_slice(),
+            param:    [0, 0, 0]
+        })
    }
-    unreachable!();
-}
-
-pub unsafe extern fn resume() -> ! {
-    trace!("resume");
-    assert!(EXCEPTION_BUFFER.exception_count != 0);
-    let i = EXCEPTION_BUFFER.exception_stack[EXCEPTION_BUFFER.exception_count - 1];
-    assert!(i != -1);
-    let _result = _Unwind_ForcedUnwind(&mut EXCEPTION_BUFFER.uw_exceptions[i as usize],
-                                       stop_fn, core::ptr::null_mut());
-    unreachable!()
-}
-
-pub unsafe extern fn end_catch() {
-    let mut count = EXCEPTION_BUFFER.exception_count;
-    assert!(count != 0);
-    // we remove all exceptions with SP <= current exception SP
-    // i.e. the outer exception escapes the finally block
-    let index = EXCEPTION_BUFFER.exception_stack[count - 1] as usize;
-    EXCEPTION_BUFFER.exception_stack[count - 1] = -1;
-    EXCEPTION_BUFFER.exceptions[index] = None;
-    let outer_sp = EXCEPTION_BUFFER.stack_pointers
-        [index].stack_pointer;
-    count -= 1;
-    for i in (0..count).rev() {
-        let index = EXCEPTION_BUFFER.exception_stack[i];
-        assert!(index != -1);
-        let index = index as usize;
-        let sp = EXCEPTION_BUFFER.stack_pointers[index].stack_pointer;
-        if sp >= outer_sp {
-            break;
-        }
-        EXCEPTION_BUFFER.exceptions[index] = None;
-        EXCEPTION_BUFFER.exception_stack[i] = -1;
-        count -= 1;
-    }
-    EXCEPTION_BUFFER.exception_count = count;
-    EXCEPTION_BUFFER.backtrace_size = if count > 0 {
-        let index = EXCEPTION_BUFFER.exception_stack[count - 1];
-        assert!(index != -1);
-        EXCEPTION_BUFFER.stack_pointers[index as usize].current_backtrace_size
-    } else {
-        0
-    };
-}
-
-extern fn cleanup(_unwind_code: uw::_Unwind_Reason_Code,
-                  _uw_exception: *mut uw::_Unwind_Exception) {
-    unimplemented!()
-}
-
-fn uncaught_exception() -> ! {
-    unsafe {
-        // dump way to reorder the stack
-        for i in 0..EXCEPTION_BUFFER.exception_count {
-            if EXCEPTION_BUFFER.exception_stack[i] != i as isize {
-                // find the correct index
-                let index = EXCEPTION_BUFFER.exception_stack
-                    .iter()
-                    .position(|v| *v == i as isize).unwrap();
-                let a = EXCEPTION_BUFFER.exception_stack[index];
-                let b = EXCEPTION_BUFFER.exception_stack[i];
-                assert!(a != -1 && b != -1);
-                core::mem::swap(&mut EXCEPTION_BUFFER.exception_stack[index],
-                                &mut EXCEPTION_BUFFER.exception_stack[i]);
-                core::mem::swap(&mut EXCEPTION_BUFFER.exceptions[a as usize],
-                                &mut EXCEPTION_BUFFER.exceptions[b as usize]);
-                core::mem::swap(&mut EXCEPTION_BUFFER.stack_pointers[a as usize],
-                                &mut EXCEPTION_BUFFER.stack_pointers[b as usize]);
-            }
-        }
-    }
-    unsafe {
-        crate::kernel::core1::terminate(
-            EXCEPTION_BUFFER.exceptions[..EXCEPTION_BUFFER.exception_count].as_ref(),
-            EXCEPTION_BUFFER.stack_pointers[..EXCEPTION_BUFFER.exception_count].as_ref(),
-            EXCEPTION_BUFFER.backtrace[..EXCEPTION_BUFFER.backtrace_size].as_mut())
-    }
-}
-
-// stop function which would be executed when we unwind each frame
-extern fn stop_fn(_version: c_int,
-                  actions: i32,
-                  _uw_exception_class: uw::_Unwind_Exception_Class,
-                  _uw_exception: *mut uw::_Unwind_Exception,
-                  context: *mut uw::_Unwind_Context,
-                  _stop_parameter: *mut c_void) -> uw::_Unwind_Reason_Code {
-    unsafe {
-        let load_addr = KERNEL_IMAGE.as_ref().unwrap().get_load_addr();
-        let backtrace_size = EXCEPTION_BUFFER.backtrace_size;
-        // we try to remove unrelated backtrace here to save some buffer size
-        if backtrace_size < MAX_BACKTRACE_SIZE {
-            let ip = uw::_Unwind_GetIP(context);
-            if ip >= load_addr {
-                let ip = ip - load_addr;
-                let sp = uw::_Unwind_GetGR(context, uw::UNWIND_SP_REG);
-                trace!("SP: {:X}, backtrace_size: {}", sp, backtrace_size);
-                EXCEPTION_BUFFER.backtrace[backtrace_size] = (ip, sp);
-                EXCEPTION_BUFFER.backtrace_size += 1;
-                let last_index = EXCEPTION_BUFFER.exception_stack[EXCEPTION_BUFFER.exception_count - 1];
-                assert!(last_index != -1);
-                let sp_info = &mut EXCEPTION_BUFFER.stack_pointers[last_index as usize];
-                sp_info.stack_pointer = sp;
-                sp_info.current_backtrace_size = backtrace_size + 1;
-            }
-        } else {
-            trace!("backtrace size exceeded");
-        }
-
-        if actions as u32 & uw::_US_END_OF_STACK as u32 != 0 {
-            uncaught_exception()
-        } else {
-            uw::_URC_NO_REASON
-        }
-    }
-}
-
-static EXCEPTION_ID_LOOKUP: [(&str, u32); 10] = [
-    ("RuntimeError", 0),
-    ("RTIOUnderflow", 1),
-    ("RTIOOverflow", 2),
-    ("RTIODestinationUnreachable", 3),
-    ("DMAError", 4),
-    ("I2CError", 5),
-    ("CacheError", 6),
-    ("SPIError", 7),
-    ("ZeroDivisionError", 8),
-    ("IndexError", 9)
-];
-
-pub fn get_exception_id(name: &str) -> u32 {
-    for (n, id) in EXCEPTION_ID_LOOKUP.iter() {
-        if *n == name {
-            return *id
-        }
-    }
-    unimplemented!("unallocated internal exception id")
 }

 #[macro_export]
 macro_rules! artiq_raise {
    ($name:expr, $message:expr, $param0:expr, $param1:expr, $param2:expr) => ({
        use cslice::AsCSlice;
-        let name_id = $crate::eh_artiq::get_exception_id($name);
        let exn = $crate::eh_artiq::Exception {
-            id:       name_id,
+            name:     concat!("0:artiq.coredevice.exceptions.", $name).as_c_slice(),
            file:     file!().as_c_slice(),
            line:     line!(),
            column:   column!(),
@ -443,9 +257,7 @@ macro_rules! artiq_raise {
            param:    [$param0, $param1, $param2]
        };
        #[allow(unused_unsafe)]
-        unsafe {
-            $crate::eh_artiq::raise(&exn)
-        }
+        unsafe { $crate::eh_artiq::raise(&exn) }
    });
    ($name:expr, $message:expr) => ({
        artiq_raise!($name, $message, 0, 0, 0)
--- a/src/runtime/src/i2c.rs
+++ b/src/runtime/src/i2c.rs
@ -1,7 +1,8 @@
 use libboard_zynq;
+
 use crate::artiq_raise;

-pub static mut I2C_BUS: Option<libboard_zynq::i2c::I2c> = None;
+static mut I2C_BUS: Option<libboard_zynq::i2c::I2c> = None;

 pub extern fn start(busno: i32) {
    if busno > 0 {
--- a/src/runtime/src/irq.rs
+++ b/src/runtime/src/irq.rs
@ -1,10 +1,10 @@
 use libboard_zynq::{gic, mpcore, println, stdio};
 use libcortex_a9::{
-    asm, interrupt_handler,
-    regs::MPIDR,
+    asm,
+    regs::{MPIDR, SP},
    spin_lock_yield, notify_spin_lock
 };
-use libregister::RegisterR;
+use libregister::{RegisterR, RegisterW};
 use core::sync::atomic::{AtomicBool, Ordering};

 extern "C" {
@ -14,7 +14,10 @@ extern "C" {

 static CORE1_RESTART: AtomicBool = AtomicBool::new(false);

-interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
+#[link_section = ".text.boot"]
+#[no_mangle]
+#[naked]
+pub unsafe extern "C" fn IRQ() {
    if MPIDR.read().cpu_id() == 1 {
        let mpcore = mpcore::RegisterBlock::mpcore();
        let mut gic = gic::InterruptController::gic(mpcore);
@ -22,23 +25,17 @@ interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
        if id.0 == 0 {
            gic.end_interrupt(id);
            asm::exit_irq();
-            asm!("b core1_restart");
+            SP.write(&mut __stack1_start as *mut _ as u32);
+            asm::enable_irq();
+            CORE1_RESTART.store(false, Ordering::Relaxed);
+            notify_spin_lock();
+            main_core1();
        }
    }
    stdio::drop_uart();
    println!("IRQ");
    loop {}
-});
-
-// This is actually not an interrupt handler, just use the macro for convenience.
-// This function would be called in normal mode (instead of interrupt mode), the outer naked
-// function wrapper is to tell libunwind to stop when it reaches here.
-interrupt_handler!(core1_restart, core1_restart_impl, __stack0_start, __stack1_start, {
-    asm::enable_irq();
-    CORE1_RESTART.store(false, Ordering::Relaxed);
-    notify_spin_lock();
-    main_core1();
-});
+}

 pub fn restart_core1() {
    let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
--- a/src/runtime/src/kernel/api.rs
+++ b/src/runtime/src/kernel/api.rs
@ -64,15 +64,6 @@ macro_rules! api_libm_f64f64 {
    })
 }

-macro_rules! api_libm_f64f64f64 {
-    ($i:ident) => ({
-        extern fn $i(x: f64, y: f64) -> f64 {
-            libm::$i(x, y)
-        }
-        api!($i = $i)
-    })
-}
-
 pub fn resolve(required: &[u8]) -> Option<u32> {
    let api = &[
        // timing
@ -202,15 +193,9 @@ pub fn resolve(required: &[u8]) -> Option<u32> {

        // exceptions
        api!(_Unwind_Resume = unwind::_Unwind_Resume),
-        api!(__nac3_personality = eh_artiq::artiq_personality),
-        api!(__nac3_raise = eh_artiq::raise),
-        api!(__nac3_resume = eh_artiq::resume),
-        api!(__nac3_end_catch = eh_artiq::end_catch),
-        // legacy exception symbols
        api!(__artiq_personality = eh_artiq::artiq_personality),
        api!(__artiq_raise = eh_artiq::raise),
-        api!(__artiq_resume = eh_artiq::resume),
-        api!(__artiq_end_catch = eh_artiq::end_catch),
+        api!(__artiq_reraise = eh_artiq::reraise),

        // Implementations for LLVM math intrinsics
        api!(__powidf2),
@ -221,11 +206,15 @@ pub fn resolve(required: &[u8]) -> Option<u32> {
        api_libm_f64f64!(asin),
        api_libm_f64f64!(asinh),
        api_libm_f64f64!(atan),
-        api_libm_f64f64f64!(atan2),
+        {
+            extern fn atan2(y: f64, x: f64) -> f64 {
+                libm::atan2(y, x)
+            }
+            api!(atan2 = atan2)
+        },
        api_libm_f64f64!(atanh),
        api_libm_f64f64!(cbrt),
        api_libm_f64f64!(ceil),
-        api_libm_f64f64f64!(copysign),
        api_libm_f64f64!(cos),
        api_libm_f64f64!(cosh),
        api_libm_f64f64!(erf),
@ -242,10 +231,18 @@ pub fn resolve(required: &[u8]) -> Option<u32> {
            }
            api!(fma = fma)
        },
-        api_libm_f64f64f64!(fmax),
-        api_libm_f64f64f64!(fmin),
-        api_libm_f64f64f64!(fmod),
-        api_libm_f64f64f64!(hypot),
+        {
+            extern fn fmod(x: f64, y: f64) -> f64 {
+                libm::fmod(x, y)
+            }
+            api!(fmod = fmod)
+        },
+        {
+            extern fn hypot(x: f64, y: f64) -> f64 {
+                libm::hypot(x, y)
+            }
+            api!(hypot = hypot)
+        },
        api_libm_f64f64!(j0),
        api_libm_f64f64!(j1),
        {
@ -258,8 +255,12 @@ pub fn resolve(required: &[u8]) -> Option<u32> {
        api_libm_f64f64!(log),
        api_libm_f64f64!(log2),
        api_libm_f64f64!(log10),
-        api_libm_f64f64f64!(nextafter),
-        api_libm_f64f64f64!(pow),
+        {
+            extern fn pow(x: f64, y: f64) -> f64 {
+                libm::pow(x, y)
+            }
+            api!(pow = pow)
+        },
        api_libm_f64f64!(round),
        api_libm_f64f64!(sin),
        api_libm_f64f64!(sinh),
--- a/src/runtime/src/kernel/core1.rs
+++ b/src/runtime/src/kernel/core1.rs
@ -14,7 +14,7 @@ use libcortex_a9::{
 use libboard_zynq::{mpcore, gic};
 use libsupport_zynq::ram;
 use dyld::{self, Library};
-use crate::{eh_artiq, get_async_errors, rtio};
+use crate::{eh_artiq, rtio};
 use super::{
    api::resolve,
    rpc::rpc_send_async,
@ -29,9 +29,13 @@ use super::{

 // linker symbols
 extern "C" {
+    #[no_mangle]
    static __text_start: u32;
+    #[no_mangle]
    static __text_end: u32;
+    #[no_mangle]
    static __exidx_start: u32;
+    #[no_mangle]
    static __exidx_end: u32;
 }

@ -118,7 +122,7 @@ impl KernelImage {
        dsb();
        isb();

-        (mem::transmute::<u32, extern "C" fn()>(self.__modinit__))();
+        (mem::transmute::<u32, fn()>(self.__modinit__))();

        if let Some(typeinfo) = self.typeinfo {
            attribute_writeback(typeinfo as *const ());
@ -133,7 +137,7 @@ impl KernelImage {
 }

 #[no_mangle]
-pub extern "C" fn main_core1() {
+pub fn main_core1() {
    enable_fpu();
    debug!("Core1 started");

@ -182,7 +186,6 @@ pub extern "C" fn main_core1() {
                info!("kernel starting");
                if let Some(kernel) = loaded_kernel.take() {
                    unsafe {
-                        eh_artiq::reset_exception_buffer();
                        KERNEL_CHANNEL_0TO1 = Some(core1_rx);
                        KERNEL_CHANNEL_1TO0 = Some(core1_tx);
                        KERNEL_IMAGE = &kernel as *const KernelImage;
@ -193,8 +196,7 @@ pub extern "C" fn main_core1() {
                    }
                }
                info!("kernel finished");
-                let async_errors = unsafe { get_async_errors() };
-                core1_tx.send(Message::KernelFinished(async_errors));
+                core1_tx.send(Message::KernelFinished);
            }
            _ => error!("Core1 received unexpected message: {:?}", message),
        }
@ -202,13 +204,23 @@ pub extern "C" fn main_core1() {
 }

 /// Called by eh_artiq
-pub fn terminate(exceptions: &'static [Option<eh_artiq::Exception<'static>>],
-                 stack_pointers: &'static [eh_artiq::StackPointerBacktrace],
-                 backtrace: &'static mut [(usize, usize)]) -> ! {
+pub fn terminate(exception: &'static eh_artiq::Exception<'static>, backtrace: &'static mut [usize]) -> ! {
+    let load_addr = unsafe {
+        KERNEL_IMAGE.as_ref().unwrap().get_load_addr()
+    };
+    let mut cursor = 0;
+    // The address in the backtrace is relocated, so we have to convert it back to the address in
+    // the original python script, and remove those Rust function backtrace.
+    for i in 0..backtrace.len() {
+        if backtrace[i] >= load_addr {
+            backtrace[cursor] = backtrace[i] - load_addr;
+            cursor += 1;
+        }
+    }
+
    {
        let core1_tx = unsafe { KERNEL_CHANNEL_1TO0.as_mut().unwrap() };
-        let errors = unsafe { get_async_errors() };
-        core1_tx.send(Message::KernelException(exceptions, stack_pointers, backtrace, errors));
+        core1_tx.send(Message::KernelException(exception, &backtrace[..cursor]));
    }
    loop {}
 }
--- a/src/runtime/src/kernel/mod.rs
+++ b/src/runtime/src/kernel/mod.rs
@ -15,13 +15,13 @@ mod cache;

 #[derive(Debug, Clone)]
 pub struct RPCException {
-    pub id: u32,
-    pub message: u32,
+    pub name: String,
+    pub message: String,
    pub param: [i64; 3],
-    pub file: u32,
+    pub file: String,
    pub line: i32,
    pub column: i32,
-    pub function: u32
+    pub function: String
 }

 #[derive(Debug, Clone)]
@ -30,11 +30,8 @@ pub enum Message {
    LoadCompleted,
    LoadFailed,
    StartRequest,
-    KernelFinished(u8),
-    KernelException(&'static [Option<eh_artiq::Exception<'static>>],
-                    &'static [eh_artiq::StackPointerBacktrace],
-                    &'static [(usize, usize)],
-                    u8),
+    KernelFinished,
+    KernelException(&'static eh_artiq::Exception<'static>, &'static [usize]),
    RpcSend { is_async: bool, data: Vec<u8> },
    RpcRecvRequest(*mut ()),
    RpcRecvReply(Result<usize, RPCException>),
@ -56,7 +53,7 @@ static CHANNEL_SEM: Semaphore = Semaphore::new(0, 1);
 static mut KERNEL_CHANNEL_0TO1: Option<sync_channel::Receiver<'static, Message>> = None;
 static mut KERNEL_CHANNEL_1TO0: Option<sync_channel::Sender<'static, Message>> = None;

-pub static mut KERNEL_IMAGE: *const core1::KernelImage = ptr::null();
+static mut KERNEL_IMAGE: *const core1::KernelImage = ptr::null();

 static INIT_LOCK: Mutex<()> = Mutex::new(());

--- a/src/runtime/src/kernel/rpc.rs
+++ b/src/runtime/src/kernel/rpc.rs
@ -1,7 +1,7 @@
 //! Kernel-side RPC API

 use alloc::vec::Vec;
-use cslice::CSlice;
+use cslice::{CSlice, AsCSlice};

 use crate::eh_artiq;
 use crate::rpc::send_args;
@ -36,12 +36,12 @@ pub extern fn rpc_recv(slot: *mut ()) -> usize {
        Message::RpcRecvReply(Ok(alloc_size)) => alloc_size,
        Message::RpcRecvReply(Err(exception)) => unsafe {
            eh_artiq::raise(&eh_artiq::Exception {
-                id:       exception.id,
-                file:     CSlice::new(exception.file as *const u8, usize::MAX),
+                name:     exception.name.as_bytes().as_c_slice(),
+                file:     exception.file.as_bytes().as_c_slice(),
                line:     exception.line as u32,
                column:   exception.column as u32,
-                function: CSlice::new(exception.function as *const u8, usize::MAX),
-                message:  CSlice::new(exception.message as *const u8, usize::MAX),
+                function: exception.function.as_bytes().as_c_slice(),
+                message:  exception.message.as_bytes().as_c_slice(),
                param:    exception.param
            })
        },
--- a/src/libboard_artiq/src/logger.rs
+++ b/src/libboard_artiq/src/logger.rs
--- a/src/runtime/src/main.rs
+++ b/src/runtime/src/main.rs
@ -5,49 +5,125 @@
 #![feature(panic_info_message)]
 #![feature(c_variadic)]
 #![feature(const_btree_new)]
+#![feature(ptr_offset_from)]
 #![feature(const_in_array_repeat_expressions)]
 #![feature(naked_functions)]
-#![feature(asm)]

 extern crate alloc;

+use core::{cmp, str};
 use log::{info, warn, error};

-use libboard_zynq::{timer::GlobalTimer, mpcore, gic};
+use libboard_zynq::{timer::GlobalTimer, mpcore, gic, slcr};
 use libasync::{task, block_async};
 use libsupport_zynq::ram;
 use nb;
 use void::Void;
+use embedded_hal::blocking::delay::DelayMs;
 use libconfig::Config;
-use libcortex_a9::l2c::enable_l2_cache;
-use libboard_artiq::{logger, identifier_read, init_gateware, pl};
+use libregister::RegisterW;

+mod proto_core_io;
 mod proto_async;
 mod comms;
 mod rpc;
+#[path = "../../../build/pl.rs"]
+mod pl;
 #[cfg(ki_impl = "csr")]
 #[path = "rtio_csr.rs"]
 mod rtio;
 #[cfg(ki_impl = "acp")]
 #[path = "rtio_acp.rs"]
 mod rtio;
-mod rtio_mgt;
-mod rtio_clocking;
 mod kernel;
 mod moninj;
 mod eh_artiq;
 mod panic;
+mod logger;
 mod mgmt;
 mod analyzer;
 mod irq;
 mod i2c;

-static mut SEEN_ASYNC_ERRORS: u8 = 0;
+fn init_gateware() {
+    // Set up PS->PL clocks
+    slcr::RegisterBlock::unlocked(|slcr| {
+        // As we are touching the mux, the clock may glitch, so reset the PL.
+        slcr.fpga_rst_ctrl.write(
+            slcr::FpgaRstCtrl::zeroed()
+                .fpga0_out_rst(true)
+                .fpga1_out_rst(true)
+                .fpga2_out_rst(true)
+                .fpga3_out_rst(true)
+        );
+        slcr.fpga0_clk_ctrl.write(
+            slcr::Fpga0ClkCtrl::zeroed()
+                .src_sel(slcr::PllSource::IoPll)
+                .divisor0(8)
+                .divisor1(1)
+        );
+        slcr.fpga_rst_ctrl.write(
+            slcr::FpgaRstCtrl::zeroed()
+        );
+    });
+}

-pub unsafe fn get_async_errors() -> u8 {
-    let errors = SEEN_ASYNC_ERRORS;
-    SEEN_ASYNC_ERRORS = 0;
-    errors
+fn identifier_read(buf: &mut [u8]) -> &str {
+    unsafe {
+        pl::csr::identifier::address_write(0);
+        let len = pl::csr::identifier::data_read();
+        let len = cmp::min(len, buf.len() as u8);
+        for i in 0..len {
+            pl::csr::identifier::address_write(1 + i);
+            buf[i as usize] = pl::csr::identifier::data_read();
+        }
+        str::from_utf8_unchecked(&buf[..len as usize])
+    }
+}
+
+fn init_rtio(timer: &mut GlobalTimer, cfg: &Config) {
+    let clock_sel =
+        if let Ok(rtioclk) = cfg.read_str("rtioclk") {
+            match rtioclk.as_ref() {
+                "internal" => {
+                    info!("using internal RTIO clock");
+                    0
+                },
+                "external" => {
+                    info!("using external RTIO clock");
+                    1
+                },
+                other => {
+                    warn!("RTIO clock specification '{}' not recognized", other);
+                    info!("using internal RTIO clock");
+                    0
+                },
+            }
+        } else {
+            info!("using internal RTIO clock (default)");
+            0
+        };
+
+    loop {
+        unsafe {
+            pl::csr::rtio_crg::pll_reset_write(1);
+            pl::csr::rtio_crg::clock_sel_write(clock_sel);
+            pl::csr::rtio_crg::pll_reset_write(0);
+        }
+        timer.delay_ms(1);
+        let locked = unsafe { pl::csr::rtio_crg::pll_locked_read() != 0 };
+        if locked {
+            info!("RTIO PLL locked");
+            break;
+        } else {
+            warn!("RTIO PLL failed to lock, retrying...");
+            timer.delay_ms(500);
+        }
+    }
+
+    unsafe {
+        pl::csr::rtio_core::reset_phy_write(1);
+    }
 }

 fn wait_for_async_rtio_error() -> nb::Result<(), Void> {
@ -77,19 +153,15 @@ async fn report_async_rtio_errors() {
                error!("RTIO sequence error involving channel {}",
                       pl::csr::rtio_core::sequence_error_channel_read());
            }
-            SEEN_ASYNC_ERRORS = errors;
            pl::csr::rtio_core::async_error_write(errors);
        }
    }
 }

-
-
 static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17];

 #[no_mangle]
 pub fn main_core0() {
-    enable_l2_cache(0x8);
    let mut timer = GlobalTimer::start();

    let buffer_logger = unsafe {
@ -117,9 +189,8 @@ pub fn main_core0() {
        }
    };

-    rtio_clocking::init(&mut timer, &cfg);
-
+    init_rtio(&mut timer, &cfg);
    task::spawn(report_async_rtio_errors());

-    comms::main(timer, cfg);
+    comms::main(timer, &cfg);
 }
--- a/src/runtime/src/mgmt.rs
+++ b/src/runtime/src/mgmt.rs
@ -1,12 +1,11 @@
 use futures::{future::poll_fn, task::Poll};
 use libasync::{smoltcp::TcpStream, task};
 use libboard_zynq::smoltcp;
-use libconfig::Config;
 use core::cell::RefCell;
-use alloc::{rc::Rc, vec::Vec, string::String};
-use log::{self, info, debug, warn, error, LevelFilter};
+use alloc::rc::Rc;
+use log::{self, info, warn, LevelFilter};

-use libboard_artiq::logger::{BufferLogger, LogBufferRef};
+use crate::logger::{BufferLogger, LogBufferRef};
 use crate::proto_async::*;
 use num_derive::FromPrimitive;
 use num_traits::FromPrimitive;
@ -45,18 +44,12 @@ pub enum Request {
    PullLog = 7,
    SetLogFilter = 3,
    SetUartLogFilter = 6,
-
-    ConfigRead = 12,
-    ConfigWrite = 13,
-    ConfigRemove = 14,
 }

 #[repr(i8)]
 pub enum Reply {
    Success = 1,
    LogContent = 2,
-    Error = 6,
-    ConfigData = 7,
 }

 async fn read_log_level_filter(stream: &mut TcpStream) -> Result<log::LevelFilter> {
@ -92,36 +85,14 @@ async fn get_logger_buffer() -> LogBufferRef<'static> {
    get_logger_buffer_pred(|_| true).await
 }

-async fn read_key(stream: &mut TcpStream) -> Result<String> {
-    let len = read_i32(stream).await?;
-    if len <= 0 {
-        write_i8(stream, Reply::Error as i8).await?;
-        return Err(Error::UnexpectedPattern);
-    }
-    let mut buffer = Vec::with_capacity(len as usize);
-    for _ in 0..len {
-        buffer.push(0);
-    }
-    read_chunk(stream, &mut buffer).await?;
-    if !buffer.is_ascii() {
-        write_i8(stream, Reply::Error as i8).await?;
-        return Err(Error::UnexpectedPattern);
-    }
-    Ok(String::from_utf8(buffer).unwrap())
-}
-
-async fn handle_connection(
-    stream: &mut TcpStream,
-    pull_id: Rc<RefCell<u32>>,
-    cfg: Rc<Config>) -> Result<()> {
+async fn handle_connection(stream: &mut TcpStream, pull_id: Rc<RefCell<u32>>) -> Result<()> {
    if !expect(&stream, b"ARTIQ management\n").await? {
        return Err(Error::UnexpectedPattern);
    }
-    stream.send_slice("e".as_bytes()).await?;

    loop {
        let msg = read_i8(stream).await;
-        if let Err(smoltcp::Error::Finished) = msg {
+        if let Err(smoltcp::Error::Illegal) = msg {
            return Ok(());
        }
        let msg: Request = FromPrimitive::from_i8(msg?).ok_or(Error::UnrecognizedPacket)?;
@ -179,70 +150,19 @@ async fn handle_connection(
                }
                write_i8(stream, Reply::Success as i8).await?;
            }
-            Request::ConfigRead => {
-                let key = read_key(stream).await?;
-                debug!("read key: {}", key);
-                let value = cfg.read(&key);
-                if let Ok(value) = value {
-                    debug!("got value");
-                    write_i8(stream, Reply::ConfigData as i8).await?;
-                    write_chunk(stream, &value).await?;
-                } else {
-                    warn!("read error: no such key");
-                    write_i8(stream, Reply::Error as i8).await?;
-                }
-            },
-            Request::ConfigWrite => {
-                let key = read_key(stream).await?;
-                warn!("write key: {}", key);
-                let len = read_i32(stream).await?;
-                let len = if len <= 0 {
-                    0
-                } else {
-                    len as usize
-                };
-                let mut buffer = Vec::with_capacity(len);
-                unsafe {
-                    buffer.set_len(len);
-                }
-                read_chunk(stream, &mut buffer).await?;
-                let value = cfg.write(&key, buffer);
-                if value.is_ok() {
-                    debug!("write success");
-                    write_i8(stream, Reply::Success as i8).await?;
-                } else {
-                    // this is an error because we do not expect write to fail
-                    error!("failed to write: {:?}", value);
-                    write_i8(stream, Reply::Error as i8).await?;
-                }
-            },
-            Request::ConfigRemove => {
-                let key = read_key(stream).await?;
-                debug!("erase key: {}", key);
-                let value = cfg.remove(&key);
-                if value.is_ok() {
-                    debug!("erase success");
-                    write_i8(stream, Reply::Success as i8).await?;
-                } else {
-                    warn!("erase failed");
-                    write_i8(stream, Reply::Error as i8).await?;
-                }
-            }
        }
    }
 }

-pub fn start(cfg: Config) {
+pub fn start() {
    task::spawn(async move {
        let pull_id = Rc::new(RefCell::new(0u32));
-        let cfg = Rc::new(cfg);
        loop {
            let mut stream = TcpStream::accept(1380, 2048, 2048).await.unwrap();
            let pull_id = pull_id.clone();
-            let cfg = cfg.clone();
            task::spawn(async move {
                info!("received connection");
-                let _ = handle_connection(&mut stream, pull_id, cfg)
+                let _ = handle_connection(&mut stream, pull_id)
                    .await
                    .map_err(|e| warn!("connection terminated: {:?}", e));
                let _ = stream.flush().await;
--- a/src/runtime/src/moninj.rs
+++ b/src/runtime/src/moninj.rs
@ -1,19 +1,17 @@
-use core::{fmt, cell::RefCell};
-use alloc::{collections::BTreeMap, rc::Rc};
+use core::fmt;
+use alloc::collections::BTreeMap;
 use log::{debug, info, warn};
 use void::Void;

-use libboard_artiq::drtio_routing;
-
 use libboard_zynq::{smoltcp, timer::GlobalTimer, time::Milliseconds};
 use libasync::{task, smoltcp::TcpStream, block_async, nb};
-use libcortex_a9::mutex::Mutex;

 use num_derive::{FromPrimitive, ToPrimitive};
 use num_traits::{FromPrimitive, ToPrimitive};
 use futures::{pin_mut, select_biased, FutureExt};

 use crate::proto_async::*;
+use crate::pl::csr;


 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
@ -21,6 +19,7 @@ pub enum Error {
    NetworkError(smoltcp::Error),
    UnexpectedPattern,
    UnrecognizedPacket,
+
 }

 pub type Result<T> = core::result::Result<T, Error>;
@ -55,113 +54,35 @@ enum DeviceMessage {
    InjectionStatus = 1
 }

-#[cfg(has_drtio)]
-mod remote_moninj {
-    use super::*;
-    use libboard_artiq::drtioaux;
-    use crate::rtio_mgt::drtio;
-    use log::error;
-
-    pub fn read_probe(aux_mutex: &Rc<Mutex<bool>>, timer: GlobalTimer, linkno: u8, destination: u8, channel: i32, probe: i8) -> i32 {
-        let reply = task::block_on(drtio::aux_transact(aux_mutex, linkno, &drtioaux::Packet::MonitorRequest { 
-            destination: destination,
-            channel: channel as _,
-            probe: probe as _},
-            timer));
-        match reply {
-            Ok(drtioaux::Packet::MonitorReply { value }) => return value as i32,
-            Ok(packet) => error!("received unexpected aux packet: {:?}", packet),
-            Err(e) => error!("aux packet error ({})", e)
-        }
-        0
-    }
-
-    pub fn inject(aux_mutex: &Rc<Mutex<bool>>, _timer: GlobalTimer, linkno: u8, destination: u8, channel: i32, overrd: i8, value: i8) {
-        let _lock = aux_mutex.lock();
-        drtioaux::send(linkno, &drtioaux::Packet::InjectionRequest {
-            destination: destination,
-            channel: channel as _,
-            overrd: overrd as _,
-            value: value as _
-        }).unwrap();
-    }
-
-    pub fn read_injection_status(aux_mutex: &Rc<Mutex<bool>>, timer: GlobalTimer, linkno: u8, destination: u8, channel: i32, overrd: i8) -> i8 {
-        let reply = task::block_on(drtio::aux_transact(aux_mutex, 
-            linkno, 
-            &drtioaux::Packet::InjectionStatusRequest {
-                destination: destination,
-                channel: channel as _,
-                overrd: overrd as _},
-            timer));
-        match reply {
-            Ok(drtioaux::Packet::InjectionStatusReply { value }) => return value as i8,
-            Ok(packet) => error!("received unexpected aux packet: {:?}", packet),
-            Err(e) => error!("aux packet error ({})", e)
-        }
-        0
+fn read_probe(channel: i32, probe: i8) -> i32 {
+    unsafe {
+        csr::rtio_moninj::mon_chan_sel_write(channel as _);
+        csr::rtio_moninj::mon_probe_sel_write(probe as _);
+        csr::rtio_moninj::mon_value_update_write(1);
+        csr::rtio_moninj::mon_value_read() as i32
    }
 }

-mod local_moninj {
-    use libboard_artiq::pl::csr;
-
-    pub fn read_probe(channel: i32, probe: i8) -> i32 {
-        unsafe {
-            csr::rtio_moninj::mon_chan_sel_write(channel as _);
-            csr::rtio_moninj::mon_probe_sel_write(probe as _);
-            csr::rtio_moninj::mon_value_update_write(1);
-            csr::rtio_moninj::mon_value_read() as i32
-        }
-    }
-
-    pub fn inject(channel: i32, overrd: i8, value: i8) {
-        unsafe {
-            csr::rtio_moninj::inj_chan_sel_write(channel as _);
-            csr::rtio_moninj::inj_override_sel_write(overrd as _);
-            csr::rtio_moninj::inj_value_write(value as _);
-        }
-    }
-
-    pub fn read_injection_status(channel: i32, overrd: i8) -> i8 {
-        unsafe {
-            csr::rtio_moninj::inj_chan_sel_write(channel as _);
-            csr::rtio_moninj::inj_override_sel_write(overrd as _);
-            csr::rtio_moninj::inj_value_read() as i8
-        }
+fn inject(channel: i32, overrd: i8, value: i8) {
+    unsafe {
+        csr::rtio_moninj::inj_chan_sel_write(channel as _);
+        csr::rtio_moninj::inj_override_sel_write(overrd as _);
+        csr::rtio_moninj::inj_value_write(value as _);
    }
 }

-#[cfg(has_drtio)]
-macro_rules! dispatch {
-    ($timer:ident, $aux_mutex:ident, $routing_table:ident, $channel:expr, $func:ident $(, $param:expr)*) => {{
-        let destination = ($channel >> 16) as u8;
-        let channel = $channel;
-        let routing_table = $routing_table.borrow_mut();
-        let hop = routing_table.0[destination as usize][0];
-        if hop == 0 {
-            local_moninj::$func(channel.into(), $($param, )*)
-        } else {
-            let linkno = hop - 1 as u8;
-            remote_moninj::$func($aux_mutex, $timer, linkno, destination, channel, $($param, )*)
-        }
-    }}
+fn read_injection_status(channel: i32, overrd: i8) -> i8 {
+    unsafe {
+        csr::rtio_moninj::inj_chan_sel_write(channel as _);
+        csr::rtio_moninj::inj_override_sel_write(overrd as _);
+        csr::rtio_moninj::inj_value_read() as i8
+    }
 }

-#[cfg(not(has_drtio))]
-macro_rules! dispatch {
-    ($timer:ident, $aux_mutex:ident, $routing_table:ident, $channel:expr, $func:ident $(, $param:expr)*) => {{
-        let channel = $channel as u16;
-        local_moninj::$func(channel.into(), $($param, )*)
-    }}
-}
-
-async fn handle_connection(stream: &TcpStream, timer: GlobalTimer, 
-        _aux_mutex: &Rc<Mutex<bool>>, _routing_table: &Rc<RefCell<drtio_routing::RoutingTable>>) -> Result<()> {
+async fn handle_connection(stream: &TcpStream, timer: GlobalTimer) -> Result<()> {
    if !expect(&stream, b"ARTIQ moninj\n").await? {
        return Err(Error::UnexpectedPattern);
    }
-    stream.send_slice("e".as_bytes()).await?;

    let mut probe_watch_list: BTreeMap<(i32, i8), Option<i32>> = BTreeMap::new();
    let mut inject_watch_list: BTreeMap<(i32, i8), Option<i8>> = BTreeMap::new();
@ -213,13 +134,13 @@ async fn handle_connection(stream: &TcpStream, timer: GlobalTimer,
                        let channel = read_i32(&stream).await?;
                        let overrd = read_i8(&stream).await?;
                        let value = read_i8(&stream).await?;
-                        dispatch!(timer, _aux_mutex, _routing_table, channel, inject, overrd, value);
+                        inject(channel, overrd, value);
                        debug!("INJECT channel {}, overrd {}, value {}", channel, overrd, value);
                    },
                    HostMessage::GetInjectionStatus => {
                        let channel = read_i32(&stream).await?;
                        let overrd = read_i8(&stream).await?;
-                        let value = dispatch!(timer, _aux_mutex, _routing_table, channel, read_injection_status, overrd);
+                        let value = read_injection_status(channel, overrd);
                        write_i8(&stream, DeviceMessage::InjectionStatus.to_i8().unwrap()).await?;
                        write_i32(&stream, channel).await?;
                        write_i8(&stream, overrd).await?;
@ -229,7 +150,7 @@ async fn handle_connection(stream: &TcpStream, timer: GlobalTimer,
            },
            _ = timeout_f => {
                for (&(channel, probe), previous) in probe_watch_list.iter_mut() {
-                    let current = dispatch!(timer, _aux_mutex, _routing_table, channel, read_probe, probe);
+                    let current = read_probe(channel, probe);
                    if previous.is_none() || previous.unwrap() != current {
                        write_i8(&stream, DeviceMessage::MonitorStatus.to_i8().unwrap()).await?;
                        write_i32(&stream, channel).await?;
@ -239,7 +160,7 @@ async fn handle_connection(stream: &TcpStream, timer: GlobalTimer,
                    }
                }
                for (&(channel, overrd), previous) in inject_watch_list.iter_mut() {
-                    let current = dispatch!(timer, _aux_mutex, _routing_table, channel, read_injection_status, overrd);
+                    let current = read_injection_status(channel, overrd);
                    if previous.is_none() || previous.unwrap() != current {
                        write_i8(&stream, DeviceMessage::InjectionStatus.to_i8().unwrap()).await?;
                        write_i32(&stream, channel).await?;
@ -254,17 +175,15 @@ async fn handle_connection(stream: &TcpStream, timer: GlobalTimer,
    }
 }

-pub fn start(timer: GlobalTimer, aux_mutex: Rc<Mutex<bool>>, routing_table: Rc<RefCell<drtio_routing::RoutingTable>>) {
+pub fn start(timer: GlobalTimer) {
    task::spawn(async move {
        loop {
-            let aux_mutex = aux_mutex.clone();
-            let routing_table = routing_table.clone();
            let stream = TcpStream::accept(1383, 2048, 2048).await.unwrap();
            task::spawn(async move {
                info!("received connection");
-                let result = handle_connection(&stream, timer, &aux_mutex, &routing_table).await;
+                let result = handle_connection(&stream, timer).await;
                match result {
-                    Err(Error::NetworkError(smoltcp::Error::Finished)) => info!("peer closed connection"),
+                    Err(Error::NetworkError(smoltcp::Error::Illegal)) => info!("peer closed connection"),
                    Err(error) => warn!("connection terminated: {}", error),
                    _ => (),
                }
--- a/src/runtime/src/proto_async.rs
+++ b/src/runtime/src/proto_async.rs
@ -54,13 +54,13 @@ pub async fn read_i8(stream: &TcpStream) -> Result<i8> {
 pub async fn read_i32(stream: &TcpStream) -> Result<i32> {
    let mut buffer: [u8; 4] = [0; 4];
    read_chunk(stream, &mut buffer).await?;
-    Ok(i32::from_le_bytes(buffer))
+    Ok(i32::from_be_bytes(buffer))
 }

 pub async fn read_i64(stream: &TcpStream) -> Result<i64> {
    let mut buffer: [u8; 8] = [0; 8];
    read_chunk(stream, &mut buffer).await?;
-    Ok(i64::from_le_bytes(buffer))
+    Ok(i64::from_be_bytes(buffer))
 }

 pub async fn read_chunk(stream: &TcpStream, destination: &mut [u8]) -> Result<()> {
@ -90,12 +90,12 @@ pub async fn write_bool(stream: &TcpStream, value: bool) -> Result<()> {
 }

 pub async fn write_i32(stream: &TcpStream, value: i32) -> Result<()> {
-    stream.send_slice(&value.to_le_bytes()).await?;
+    stream.send_slice(&value.to_be_bytes()).await?;
    Ok(())
 }

 pub async fn write_i64(stream: &TcpStream, value: i64) -> Result<()> {
-    stream.send_slice(&value.to_le_bytes()).await?;
+    stream.send_slice(&value.to_be_bytes()).await?;
    Ok(())
 }

--- a/src/runtime/src/proto_core_io.rs
+++ b/src/runtime/src/proto_core_io.rs
@ -1,5 +1,5 @@
 use core::str::Utf8Error;
-use byteorder::{ByteOrder, NativeEndian};
+use byteorder::{ByteOrder, NetworkEndian};
 use alloc::vec;
 use alloc::string::String;

@ -28,21 +28,21 @@ pub trait ProtoRead {
    fn read_u16(&mut self) -> Result<u16, Self::ReadError> {
        let mut bytes = [0; 2];
        self.read_exact(&mut bytes)?;
-        Ok(NativeEndian::read_u16(&bytes))
+        Ok(NetworkEndian::read_u16(&bytes))
    }

    #[inline]
    fn read_u32(&mut self) -> Result<u32, Self::ReadError> {
        let mut bytes = [0; 4];
        self.read_exact(&mut bytes)?;
-        Ok(NativeEndian::read_u32(&bytes))
+        Ok(NetworkEndian::read_u32(&bytes))
    }

    #[inline]
    fn read_u64(&mut self) -> Result<u64, Self::ReadError> {
        let mut bytes = [0; 8];
        self.read_exact(&mut bytes)?;
-        Ok(NativeEndian::read_u64(&bytes))
+        Ok(NetworkEndian::read_u64(&bytes))
    }

    #[inline]
@ -85,42 +85,42 @@ pub trait ProtoWrite {
    #[inline]
    fn write_u16(&mut self, value: u16) -> Result<(), Self::WriteError> {
        let mut bytes = [0; 2];
-        NativeEndian::write_u16(&mut bytes, value);
+        NetworkEndian::write_u16(&mut bytes, value);
        self.write_all(&bytes)
    }

    #[inline]
    fn write_i16(&mut self, value: i16) -> Result<(), Self::WriteError> {
        let mut bytes = [0; 2];
-        NativeEndian::write_i16(&mut bytes, value);
+        NetworkEndian::write_i16(&mut bytes, value);
        self.write_all(&bytes)
    }

    #[inline]
    fn write_u32(&mut self, value: u32) -> Result<(), Self::WriteError> {
        let mut bytes = [0; 4];
-        NativeEndian::write_u32(&mut bytes, value);
+        NetworkEndian::write_u32(&mut bytes, value);
        self.write_all(&bytes)
    }

    #[inline]
    fn write_i32(&mut self, value: i32) -> Result<(), Self::WriteError> {
        let mut bytes = [0; 4];
-        NativeEndian::write_i32(&mut bytes, value);
+        NetworkEndian::write_i32(&mut bytes, value);
        self.write_all(&bytes)
    }

    #[inline]
    fn write_u64(&mut self, value: u64) -> Result<(), Self::WriteError> {
        let mut bytes = [0; 8];
-        NativeEndian::write_u64(&mut bytes, value);
+        NetworkEndian::write_u64(&mut bytes, value);
        self.write_all(&bytes)
    }

    #[inline]
    fn write_i64(&mut self, value: i64) -> Result<(), Self::WriteError> {
        let mut bytes = [0; 8];
-        NativeEndian::write_i64(&mut bytes, value);
+        NetworkEndian::write_i64(&mut bytes, value);
        self.write_all(&bytes)
    }

--- a/src/runtime/src/rpc.rs
+++ b/src/runtime/src/rpc.rs
@ -2,7 +2,7 @@ use core::str;
 use core::future::Future;
 use cslice::{CSlice, CMutSlice};
 use log::trace;
-use byteorder::{NativeEndian, ByteOrder};
+use byteorder::{NetworkEndian, ByteOrder};

 use core_io::{Write, Error};
 use libboard_zynq::smoltcp;
@ -10,24 +10,19 @@ use libasync::smoltcp::TcpStream;
 use alloc::boxed::Box;
 use async_recursion::async_recursion;

-use io::proto::ProtoWrite;
+use crate::proto_core_io::ProtoWrite;
 use crate::proto_async;
 use self::tag::{Tag, TagIterator, split_tag};

-#[inline]
-fn alignment_offset(alignment: isize, ptr: isize) -> isize {
-    (alignment - ptr % alignment) % alignment
-}
-
 unsafe fn align_ptr<T>(ptr: *const ()) -> *const T {
    let alignment = core::mem::align_of::<T>() as isize;
-    let fix = alignment_offset(alignment, ptr as isize);
+    let fix = (alignment - (ptr as isize) % alignment) % alignment;
    ((ptr as isize) + fix) as *const T
 }

 unsafe fn align_ptr_mut<T>(ptr: *mut ()) -> *mut T {
    let alignment = core::mem::align_of::<T>() as isize;
-    let fix = alignment_offset(alignment, ptr as isize);
+    let fix = (alignment - (ptr as isize) % alignment) % alignment;
    ((ptr as isize) + fix) as *mut T
 }

@ -71,7 +66,6 @@ async unsafe fn recv_value<F>(stream: &TcpStream, tag: Tag<'async_recursion>, da
            })
        }
        Tag::Tuple(it, arity) => {
-            *data = (*data).offset(alignment_offset(tag.alignment() as isize, *data as isize));
            let mut it = it.clone();
            for _ in 0..arity {
                let tag = it.next().expect("truncated tag");
@ -81,43 +75,36 @@ async unsafe fn recv_value<F>(stream: &TcpStream, tag: Tag<'async_recursion>, da
        }
        Tag::List(it) => {
            #[repr(C)]
-            struct List { elements: *mut (), length: u32 }
+            struct List { elements: *mut (), length: u32 };
            consume_value!(List, |ptr| {
                let length = proto_async::read_i32(stream).await? as usize;
                (*ptr).length  = length as u32;
                let tag = it.clone().next().expect("truncated tag");
-                let data_size = tag.size() * length as usize +
-                    match tag {
-                        Tag::Int64 | Tag::Float64 => 4,
-                        _ => 0
-                    };
-                let mut data = alloc(data_size).await;
+                let mut data = alloc(tag.size() * length as usize).await;

-                let alignment = tag.alignment();
-                data = data.offset(alignment_offset(alignment as isize, data as isize));
                (*ptr).elements = data;
                match tag {
                    Tag::Bool => {
-                        let ptr = data as *mut u8;
+                        let ptr = align_ptr_mut::<u8>(data);
                        let dest = core::slice::from_raw_parts_mut(ptr, length);
                        proto_async::read_chunk(stream, dest).await?;
                    },
                    Tag::Int32 => {
-                        let ptr = data as *mut u32;
+                        let ptr = align_ptr_mut::<u32>(data);
                        // reading as raw bytes and do endianness conversion later
                        let dest = core::slice::from_raw_parts_mut(ptr as *mut u8, length * 4);
                        proto_async::read_chunk(stream, dest).await?;
                        drop(dest);
                        let dest = core::slice::from_raw_parts_mut(ptr, length);
-                        NativeEndian::from_slice_u32(dest);
+                        NetworkEndian::from_slice_u32(dest);
                    },
                    Tag::Int64 | Tag::Float64 => {
-                        let ptr = data as *mut u64;
+                        let ptr = align_ptr_mut::<u64>(data);
                        let dest = core::slice::from_raw_parts_mut(ptr as *mut u8, length * 8);
                        proto_async::read_chunk(stream, dest).await?;
                        drop(dest);
                        let dest = core::slice::from_raw_parts_mut(ptr, length);
-                        NativeEndian::from_slice_u64(dest);
+                        NetworkEndian::from_slice_u64(dest);
                    },
                    _ => {
                        for _ in 0..(*ptr).length as usize {
@ -138,38 +125,31 @@ async unsafe fn recv_value<F>(stream: &TcpStream, tag: Tag<'async_recursion>, da
                }

                let elt_tag = it.clone().next().expect("truncated tag");
-                let data_size = elt_tag.size() * total_len as usize +
-                    match elt_tag {
-                        Tag::Int64 | Tag::Float64 => 4,
-                        _ => 0
-                    };
-                let mut data = alloc(data_size).await;
+                *buffer = alloc(elt_tag.size() * total_len as usize).await;

-                let alignment = tag.alignment();
-                data = data.offset(alignment_offset(alignment as isize, data as isize));
-                *buffer = data;
                let length = total_len as usize;
+                let mut data = *buffer;
                match elt_tag {
                    Tag::Bool => {
-                        let ptr = data as *mut u8;
+                        let ptr = align_ptr_mut::<u8>(data);
                        let dest = core::slice::from_raw_parts_mut(ptr, length);
                        proto_async::read_chunk(stream, dest).await?;
                    },
                    Tag::Int32 => {
-                        let ptr = data as *mut u32;
+                        let ptr = align_ptr_mut::<u32>(data);
                        let dest = core::slice::from_raw_parts_mut(ptr as *mut u8, length * 4);
                        proto_async::read_chunk(stream, dest).await?;
                        drop(dest);
                        let dest = core::slice::from_raw_parts_mut(ptr, length);
-                        NativeEndian::from_slice_u32(dest);
+                        NetworkEndian::from_slice_u32(dest);
                    },
                    Tag::Int64 | Tag::Float64 => {
-                        let ptr = data as *mut u64;
+                        let ptr = align_ptr_mut::<u64>(data);
                        let dest = core::slice::from_raw_parts_mut(ptr as *mut u8, length * 8);
                        proto_async::read_chunk(stream, dest).await?;
                        drop(dest);
                        let dest = core::slice::from_raw_parts_mut(ptr, length);
-                        NativeEndian::from_slice_u64(dest);
+                        NetworkEndian::from_slice_u64(dest);
                    },
                    _ => {
                        for _ in 0..length {
@ -181,7 +161,6 @@ async unsafe fn recv_value<F>(stream: &TcpStream, tag: Tag<'async_recursion>, da
            })
        }
        Tag::Range(it) => {
-            *data = (*data).offset(alignment_offset(tag.alignment() as isize, *data as isize));
            let tag = it.clone().next().expect("truncated tag");
            recv_value(stream, tag, data, alloc).await?;
            recv_value(stream, tag, data, alloc).await?;
@ -249,7 +228,7 @@ unsafe fn send_value<W>(writer: &mut W, tag: Tag, data: &mut *const ())
        }
        Tag::List(it) => {
            #[repr(C)]
-            struct List { elements: *const (), length: u32 }
+            struct List { elements: *const (), length: u32 };
            consume_value!(List, |ptr| {
                let length = (*ptr).length as isize;
                writer.write_u32((*ptr).length)?;
@ -265,13 +244,25 @@ unsafe fn send_value<W>(writer: &mut W, tag: Tag, data: &mut *const ())
                    },
                    Tag::Int32 => {
                        let ptr1 = align_ptr::<i32>(data);
-                        let slice = core::slice::from_raw_parts(ptr1 as *const u8, length as usize * 4);
-                        writer.write_all(slice)?;
+                        let slice = core::slice::from_raw_parts(ptr1, length as usize);
+                        let mut v: alloc::vec::Vec<i32> = slice.to_vec();
+                        NetworkEndian::from_slice_i32(&mut v);
+                        let slice2 = core::slice::from_raw_parts(
+                            v.as_ptr() as usize as *const u8,
+                            length as usize * 4
+                        );
+                        writer.write_all(slice2)?;
                    },
                    Tag::Int64 | Tag::Float64 => {
                        let ptr1 = align_ptr::<i64>(data);
-                        let slice = core::slice::from_raw_parts(ptr1 as *const u8, length as usize * 8);
-                        writer.write_all(slice)?;
+                        let slice = core::slice::from_raw_parts(ptr1, length as usize);
+                        let mut v: alloc::vec::Vec<i64> = slice.to_vec();
+                        NetworkEndian::from_slice_i64(&mut v);
+                        let slice2 = core::slice::from_raw_parts(
+                            v.as_ptr() as usize as *const u8,
+                            length as usize * 8
+                        );
+                        writer.write_all(slice2)?;
                    },
                    // non-primitive types, not sure if this would happen but we can handle it...
                    _ => {
@ -306,13 +297,25 @@ unsafe fn send_value<W>(writer: &mut W, tag: Tag, data: &mut *const ())
                    },
                    Tag::Int32 => {
                        let ptr1 = align_ptr::<i32>(data);
-                        let slice = core::slice::from_raw_parts(ptr1 as *const u8, length as usize * 4);
-                        writer.write_all(slice)?;
+                        let slice = core::slice::from_raw_parts(ptr1, length as usize);
+                        let mut v: alloc::vec::Vec<i32> = slice.to_vec();
+                        NetworkEndian::from_slice_i32(&mut v);
+                        let slice2 = core::slice::from_raw_parts(
+                            v.as_ptr() as usize as *const u8,
+                            length as usize * 4
+                        );
+                        writer.write_all(slice2)?;
                    },
                    Tag::Int64 | Tag::Float64 => {
                        let ptr1 = align_ptr::<i64>(data);
-                        let slice = core::slice::from_raw_parts(ptr1 as *const u8, length as usize * 8);
-                        writer.write_all(slice)?;
+                        let slice = core::slice::from_raw_parts(ptr1, length as usize);
+                        let mut v: alloc::vec::Vec<i64> = slice.to_vec();
+                        NetworkEndian::from_slice_i64(&mut v);
+                        let slice2 = core::slice::from_raw_parts(
+                            v.as_ptr() as usize as *const u8,
+                            length as usize * 8
+                        );
+                        writer.write_all(slice2)?;
                    },
                    // non-primitive types, not sure if this would happen but we can handle it...
                    _ => {
@ -333,7 +336,7 @@ unsafe fn send_value<W>(writer: &mut W, tag: Tag, data: &mut *const ())
        }
        Tag::Keyword(it) => {
            #[repr(C)]
-            struct Keyword<'a> { name: CSlice<'a, u8> }
+            struct Keyword<'a> { name: CSlice<'a, u8> };
            consume_value!(Keyword, |ptr| {
                writer.write_string(str::from_utf8((*ptr).name.as_ref()).unwrap())?;
                let tag = it.clone().next().expect("truncated tag");
@ -345,7 +348,7 @@ unsafe fn send_value<W>(writer: &mut W, tag: Tag, data: &mut *const ())
        }
        Tag::Object => {
            #[repr(C)]
-            struct Object { id: u32 }
+            struct Object { id: u32 };
            consume_value!(*const Object, |ptr|
                writer.write_u32((**ptr).id))
        }
@ -428,35 +431,7 @@ mod tag {
            }
        }

-        pub fn alignment(self) -> usize {
-            use cslice::CSlice;
-            match self {
-                Tag::None => 1,
-                Tag::Bool => core::mem::align_of::<u8>(),
-                Tag::Int32 => core::mem::align_of::<i32>(),
-                Tag::Int64 => core::mem::align_of::<i64>(),
-                Tag::Float64 => core::mem::align_of::<f64>(),
-                // struct type: align to largest element
-                Tag::Tuple(it, arity) => {
-                    let it = it.clone();
-                    it.take(arity.into()).map(|t| t.alignment()).max().unwrap()
-                },
-                Tag::Range(it) => {
-                    let it = it.clone();
-                    it.take(3).map(|t| t.alignment()).max().unwrap()
-                }
-                // CSlice basically
-                Tag::Bytes | Tag::String | Tag::ByteArray | Tag::List(_) =>
-                    core::mem::align_of::<CSlice<()>>(),
-                // array buffer is allocated, so no need for alignment first
-                Tag::Array(_, _) => 1,
-                // will not be sent from the host
-                _ => unreachable!("unexpected tag from host")
-            }
-        }
-
        pub fn size(self) -> usize {
-            use super::alignment_offset;
            match self {
                Tag::None => 0,
                Tag::Bool => 1,
@ -472,8 +447,6 @@ mod tag {
                    for _ in 0..arity {
                        let tag = it.next().expect("truncated tag");
                        size += tag.size();
-                        // includes padding
-                        size += alignment_offset(tag.alignment() as isize, size as isize) as usize;
                    }
                    size
                }
@ -496,23 +469,10 @@ mod tag {

    impl<'a> TagIterator<'a> {
        pub fn new(data: &'a [u8]) -> TagIterator<'a> {
-            TagIterator { data }
+            TagIterator { data: data }
        }

-
-        fn sub(&mut self, count: u8) -> TagIterator<'a> {
-            let data = self.data;
-            for _ in 0..count {
-                self.next().expect("truncated tag");
-            }
-            TagIterator { data: &data[..(data.len() - self.data.len())] }
-        }
-    }
-
-    impl<'a> core::iter::Iterator for TagIterator<'a> {
-        type Item = Tag<'a>;
-
-        fn next(&mut self) -> Option<Tag<'a>> {
+        pub fn next(&mut self) -> Option<Tag<'a>> {
            if self.data.len() == 0 {
                return None
            }
@ -545,6 +505,14 @@ mod tag {
                _    => unreachable!()
            })
        }
+
+        fn sub(&mut self, count: u8) -> TagIterator<'a> {
+            let data = self.data;
+            for _ in 0..count {
+                self.next().expect("truncated tag");
+            }
+            TagIterator { data: &data[..(data.len() - self.data.len())] }
+        }
    }

    impl<'a> fmt::Display for TagIterator<'a> {
--- a/src/runtime/src/rtio_acp.rs
+++ b/src/runtime/src/rtio_acp.rs
@ -1,8 +1,8 @@
 use cslice::CSlice;
 use vcell::VolatileCell;
 use libcortex_a9::asm;
+
 use crate::artiq_raise;
-use core::sync::atomic::{fence, Ordering};

 use crate::pl::csr;

@ -20,33 +20,33 @@ pub struct TimestampedData {
    data: i32,
 }

-#[repr(C, align(64))]
+#[repr(C, align(32))]
 struct Transaction {
    request_cmd: i8,
-    data_width: i8,
-    padding0: [i8; 2],
+    padding0: i8,
+    padding1: i8,
+    padding2: i8,
    request_target: i32,
    request_timestamp: i64,
-    request_data: [i32; 16],
-    padding1: [i64; 2],
+    request_data: i64,
+    padding: i64,
    reply_status: VolatileCell<i32>,
    reply_data: VolatileCell<i32>,
-    reply_timestamp: VolatileCell<i64>,
-    padding2: [i64; 2],
+    reply_timestamp: VolatileCell<i64>
 }

 static mut TRANSACTION_BUFFER: Transaction = Transaction {
    request_cmd: 0,
-    data_width: 0,
+    padding0: 0,
+    padding1: 0,
+    padding2: 0,
    request_target: 0,
    request_timestamp: 0,
-    request_data: [0; 16],
+    request_data: 0,
+    padding: 0,
    reply_status: VolatileCell::new(0),
    reply_data: VolatileCell::new(0),
-    reply_timestamp: VolatileCell::new(0),
-    padding0: [0; 2],
-    padding1: [0; 2],
-    padding2: [0; 2]
+    reply_timestamp: VolatileCell::new(0)
 };

 pub extern fn init() {
@ -108,41 +108,13 @@ pub extern fn output(target: i32, data: i32) {
        TRANSACTION_BUFFER.reply_status.set(0);

        TRANSACTION_BUFFER.request_cmd = 0;
-        TRANSACTION_BUFFER.data_width = 1;
        TRANSACTION_BUFFER.request_target = target;
        TRANSACTION_BUFFER.request_timestamp = NOW;
-        TRANSACTION_BUFFER.request_data[0] = data;
+        TRANSACTION_BUFFER.request_data = data as i64;

-        fence(Ordering::SeqCst);
+        asm::dmb();
        asm::sev();
-        let mut status;
-        loop {
-            status = TRANSACTION_BUFFER.reply_status.get();
-            if status != 0 {
-                break;
-            }
-        }

-        let status = status & !0x10000;
-        if status != 0 {
-            process_exceptional_status(target >> 8, status);
-        }
-    }
-}
-
-pub extern fn output_wide(target: i32, data: CSlice<i32>) {
-    unsafe {
-        // Clear status so we can observe response
-        TRANSACTION_BUFFER.reply_status.set(0);
-
-        TRANSACTION_BUFFER.request_cmd = 0;
-        TRANSACTION_BUFFER.data_width = data.len() as i8;
-        TRANSACTION_BUFFER.request_target = target;
-        TRANSACTION_BUFFER.request_timestamp = NOW;
-        TRANSACTION_BUFFER.request_data[..data.len()].copy_from_slice(data.as_ref());
-
-        fence(Ordering::SeqCst);
-        asm::sev();
        let mut status;
        loop {
            status = TRANSACTION_BUFFER.reply_status.get();
@ -158,17 +130,21 @@ pub extern fn output_wide(target: i32, data: CSlice<i32>) {
    }
 }

+pub extern fn output_wide(target: i32, data: CSlice<i32>) {
+    // TODO
+    unimplemented!();
+}
+
 pub extern fn input_timestamp(timeout: i64, channel: i32) -> i64 {
   unsafe {
        // Clear status so we can observe response
        TRANSACTION_BUFFER.reply_status.set(0);

        TRANSACTION_BUFFER.request_cmd = 1;
-        TRANSACTION_BUFFER.request_timestamp = timeout;
+        TRANSACTION_BUFFER.request_timestamp = NOW;
        TRANSACTION_BUFFER.request_target = channel << 8;
-        TRANSACTION_BUFFER.data_width = 0;

-        fence(Ordering::SeqCst);
+        asm::dmb();
        asm::sev();

        let mut status;
@ -204,9 +180,8 @@ pub extern fn input_data(channel: i32) -> i32 {
        TRANSACTION_BUFFER.request_cmd = 1;
        TRANSACTION_BUFFER.request_timestamp = -1;
        TRANSACTION_BUFFER.request_target = channel << 8;
-        TRANSACTION_BUFFER.data_width = 0;

-        fence(Ordering::SeqCst);
+        asm::dmb();
        asm::sev();

        let mut status;
@ -239,9 +214,8 @@ pub extern fn input_timestamped_data(timeout: i64, channel: i32) -> TimestampedD
        TRANSACTION_BUFFER.request_cmd = 1;
        TRANSACTION_BUFFER.request_timestamp = timeout;
        TRANSACTION_BUFFER.request_target = channel << 8;
-        TRANSACTION_BUFFER.data_width = 0;

-        fence(Ordering::SeqCst);
+        asm::dmb();
        asm::sev();

        let mut status;
@ -271,17 +245,6 @@ pub extern fn input_timestamped_data(timeout: i64, channel: i32) -> TimestampedD
 }

 pub fn write_log(data: &[i8]) {
-    let mut word: u32 = 0;
-    for i in 0..data.len() {
-        word <<= 8;
-        word |= data[i] as u32;
-        if i % 4 == 3 {
-            output((csr::CONFIG_RTIO_LOG_CHANNEL << 8) as i32, word as i32);
-            word = 0;
-        }
-    }
-
-    if word != 0 {
-        output((csr::CONFIG_RTIO_LOG_CHANNEL << 8) as i32, word as i32);
-    }
+    // TODO
+    unimplemented!();
 }
--- a/src/runtime/src/rtio_clocking.rs
+++ b/src/runtime/src/rtio_clocking.rs
@ -1,238 +0,0 @@
-use log::{info, warn};
-use libboard_zynq::timer::GlobalTimer;
-use embedded_hal::blocking::delay::DelayMs;
-use libconfig::Config;
-use libboard_artiq::pl;
-#[cfg(has_si5324)]
-use libboard_zynq::i2c::I2c;
-#[cfg(has_si5324)]
-use crate::i2c;
-#[cfg(has_si5324)]
-use libboard_artiq::si5324;
-
-#[derive(Debug, PartialEq, Copy, Clone)]
-#[allow(non_camel_case_types)]
-pub enum RtioClock {
-    Default,
-    Int_125,
-    Int_100,
-    Int_150,
-    Ext0_Bypass,
-    Ext0_Synth0_10to125,
-    Ext0_Synth0_100to125,
-    Ext0_Synth0_125to125,
-}
-
-#[allow(unreachable_code)]
-fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
-    let mut res = RtioClock::Default;
-    if let Ok(clk) = cfg.read_str("rtio_clock") {
-        res = match clk.as_ref() {
-            "int_125" => RtioClock::Int_125,
-            "int_100" => RtioClock::Int_100,
-            "int_150" => RtioClock::Int_150,
-            "ext0_bypass" => RtioClock::Ext0_Bypass,
-            "ext0_bypass_125" => RtioClock::Ext0_Bypass,
-            "ext0_bypass_100" => RtioClock::Ext0_Bypass,
-            "ext0_synth0_10to125" => RtioClock::Ext0_Synth0_10to125,
-            "ext0_synth0_100to125" => RtioClock::Ext0_Synth0_100to125,
-            "ext0_synth0_125to125" => RtioClock::Ext0_Synth0_125to125,
-            _ => { 
-                warn!("Unrecognised rtio_clock setting. Falling back to default.");
-                RtioClock::Default 
-            }
-        };
-    }
-    else {
-        warn!("error reading configuration. Falling back to default.");
-    }
-    if res == RtioClock::Default {
-        #[cfg(rtio_frequency="100.0")]
-        {
-            warn!("Using default configuration - internal 100MHz RTIO clock.");
-            return RtioClock::Int_100;
-        }
-        #[cfg(rtio_frequency="125.0")]
-        {
-            warn!("Using default configuration - internal 125MHz RTIO clock.");
-            return RtioClock::Int_125;
-        }
-        // anything else
-        {
-            warn!("Using default configuration - internal 125MHz RTIO clock.");
-            return RtioClock::Int_125;
-        }
-    }
-    res
-}
-
-
-fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) {
-    #[cfg(has_rtio_crg_clock_sel)]
-    let clock_sel = match _clk {
-        RtioClock::Ext0_Bypass => { 
-            info!("Using bypassed external clock");
-            1
-        },
-        RtioClock::Int_125 => {
-            info!("Using internal RTIO clock");
-            0
-        },
-        _ => {
-            warn!("rtio_clock setting '{:?}' is not supported. Using default internal RTIO clock instead", _clk);
-            0
-        }
-    };
-
-    loop {
-        unsafe {
-            pl::csr::rtio_crg::pll_reset_write(1);
-            #[cfg(has_rtio_crg_clock_sel)]
-            pl::csr::rtio_crg::clock_sel_write(clock_sel);
-            pl::csr::rtio_crg::pll_reset_write(0);
-        }
-        timer.delay_ms(1);
-        let locked = unsafe { pl::csr::rtio_crg::pll_locked_read() != 0 };
-        if locked {
-            info!("RTIO PLL locked");
-            break;
-        } else {
-            warn!("RTIO PLL failed to lock, retrying...");
-            timer.delay_ms(500);
-        }
-    }
-
-    unsafe {
-        pl::csr::rtio_core::reset_phy_write(1);
-    }
-}
-
-#[cfg(has_drtio)]
-fn init_drtio(timer: &mut GlobalTimer)
-{
-    unsafe {
-        pl::csr::drtio_transceiver::stable_clkin_write(1);
-    }
-    timer.delay_ms(2); // wait for CPLL/QPLL lock
-    unsafe {
-        pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
-    }
-}
-
-#[cfg(has_si5324)]
-fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
-    let si5324_settings = match clk {
-        RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
-            info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
-            si5324::FrequencySettings {
-                n1_hs  : 10,
-                nc1_ls : 4,
-                n2_hs  : 10,
-                n2_ls  : 300,
-                n31    : 6,
-                n32    : 6,
-                bwsel  : 4,
-                crystal_ref: false
-            }
-        },
-        RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
-            info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
-            si5324::FrequencySettings {
-                n1_hs  : 10,
-                nc1_ls : 4,
-                n2_hs  : 10,
-                n2_ls  : 260,
-                n31    : 52,
-                n32    : 52,
-                bwsel  : 4,
-                crystal_ref: false
-            }
-        },
-        RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
-            info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
-            si5324::FrequencySettings {
-                n1_hs  : 5,
-                nc1_ls : 8,
-                n2_hs  : 7,
-                n2_ls  : 360,
-                n31    : 63,
-                n32    : 63,
-                bwsel  : 4,
-                crystal_ref: false
-            }
-        },
-        RtioClock::Int_150 => { // 150MHz output, from crystal
-            info!("using internal 150MHz RTIO clock");
-            si5324::FrequencySettings {
-                n1_hs  : 9,
-                nc1_ls : 4,
-                n2_hs  : 10,
-                n2_ls  : 33732,
-                n31    : 7139,
-                n32    : 7139,
-                bwsel  : 3,
-                crystal_ref: true
-            }
-        },
-        RtioClock::Int_100 => { // 100MHz output, from crystal.
-            info!("using internal 100MHz RTIO clock");
-            si5324::FrequencySettings {
-                n1_hs  : 9,
-                nc1_ls : 6,
-                n2_hs  : 10,
-                n2_ls  : 33732,
-                n31    : 7139,
-                n32    : 7139,
-                bwsel  : 3,
-                crystal_ref: true
-            }
-        },
-        RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz
-            info!("using internal 125MHz RTIO clock");
-            si5324::FrequencySettings {
-                n1_hs  : 10,
-                nc1_ls : 4,
-                n2_hs  : 10,
-                n2_ls  : 19972,
-                n31    : 4565,
-                n32    : 4565,
-                bwsel  : 4,
-                crystal_ref: true
-            }
-        }
-        _ => { // same setting  as Int_125, but fallback to default
-            warn!("rtio_clock setting '{:?}' is unsupported. Falling back to default internal 125MHz RTIO clock.", clk);
-            si5324::FrequencySettings {
-                n1_hs  : 10,
-                nc1_ls : 4,
-                n2_hs  : 10,
-                n2_ls  : 19972,
-                n31    : 4565,
-                n32    : 4565,
-                bwsel  : 4,
-                crystal_ref: true
-            }
-        }
-    };
-    let si5324_ref_input = si5324::Input::Ckin2;
-    si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324");
-}
-
-pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
-
-    let clk = get_rtio_clock_cfg(cfg);
-    #[cfg(has_si5324)]
-    {
-        let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
-        let si5324_ext_input = si5324::Input::Ckin2;
-        match clk {
-            RtioClock::Ext0_Bypass => si5324::bypass(i2c, si5324_ext_input, timer).expect("cannot bypass Si5324"),
-            _ => setup_si5324(i2c, timer, clk),
-        }
-    }
-    #[cfg(has_drtio)]
-    init_drtio(timer);
-
-    init_rtio(timer, clk);
-
-}
--- a/src/runtime/src/rtio_mgt.rs
+++ b/src/runtime/src/rtio_mgt.rs
@ -1,352 +0,0 @@
-use core::cell::RefCell;
-use alloc::rc::Rc;
-use libboard_zynq::timer::GlobalTimer;
-use libboard_artiq::{pl::csr, drtio_routing};
-use libcortex_a9::mutex::Mutex;
-
-
-#[cfg(has_drtio)]
-pub mod drtio {
-    use super::*;
-    use libboard_artiq::drtioaux_async;
-    use libboard_artiq::drtioaux_async::Packet;
-    use libboard_artiq::drtioaux::Error;
-    use log::{warn, error, info};
-    use embedded_hal::blocking::delay::DelayMs;
-    use libasync::{task, delay};
-    use libboard_zynq::time::Milliseconds;
-
-    pub fn startup(aux_mutex: &Rc<Mutex<bool>>,
-            routing_table: &Rc<RefCell<drtio_routing::RoutingTable>>,
-            up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>,
-            timer: GlobalTimer) {
-        let aux_mutex = aux_mutex.clone();
-        let routing_table = routing_table.clone();
-        let up_destinations = up_destinations.clone();
-        task::spawn(async move {
-            let routing_table = routing_table.borrow();
-            link_task(&aux_mutex, &routing_table, &up_destinations, timer).await;
-        });
-    }
-
-    async fn link_rx_up(linkno: u8) -> bool {
-        let linkno = linkno as usize;
-        unsafe {
-            (csr::DRTIO[linkno].rx_up_read)() == 1
-        }
-    }
-
-    async fn recv_aux_timeout(linkno: u8, timeout: u64, timer: GlobalTimer) -> Result<Packet, &'static str> {
-        if !link_rx_up(linkno).await {
-            return Err("link went down");
-        }
-        match drtioaux_async::recv_timeout(linkno, Some(timeout), timer).await {
-            Ok(packet) => return Ok(packet),
-            Err(Error::TimedOut) => return Err("timed out"),
-            Err(_) => return Err("aux packet error"),
-        }
-    }
-
-    pub async fn aux_transact(aux_mutex: &Mutex<bool>, linkno: u8, request: &Packet,
-            timer: GlobalTimer) -> Result<Packet, &'static str> {
-        let _lock = aux_mutex.lock();
-        drtioaux_async::send(linkno, request).await.unwrap();
-        recv_aux_timeout(linkno, 200, timer).await
-    }
-
-    async fn drain_buffer(linkno: u8, draining_time: Milliseconds, timer: GlobalTimer) {
-        let max_time = timer.get_time() + draining_time;
-        loop {
-            if timer.get_time() > max_time {
-                return;
-            } //could this be cut short?
-            let _ = drtioaux_async::recv(linkno).await;
-        }
-    }
-
-    async fn ping_remote(aux_mutex: &Rc<Mutex<bool>>, linkno: u8, timer: GlobalTimer) -> u32 {
-        let mut count = 0;
-        loop {
-            if !link_rx_up(linkno).await {
-                return 0
-            }
-            count += 1;
-            if count > 100 {
-                return 0;
-            }
-            let reply = aux_transact(aux_mutex, linkno, &Packet::EchoRequest, timer).await;
-            match reply {
-                Ok(Packet::EchoReply) => {
-                    // make sure receive buffer is drained
-                    let draining_time = Milliseconds(200);
-                    drain_buffer(linkno, draining_time, timer).await;
-                    return count;
-                }
-                _ => {}
-            }
-        }
-    }
-
-    async fn sync_tsc(aux_mutex: &Rc<Mutex<bool>>, linkno: u8, timer: GlobalTimer) -> Result<(), &'static str> {
-        let _lock = aux_mutex.lock();
-
-        unsafe {
-            (csr::DRTIO[linkno as usize].set_time_write)(1);
-            while (csr::DRTIO[linkno as usize].set_time_read)() == 1 {}
-        }
-        // TSCAck is the only aux packet that is sent spontaneously
-        // by the satellite, in response to a TSC set on the RT link.
-        let reply = recv_aux_timeout(linkno, 10000, timer).await?;
-        if reply == Packet::TSCAck {
-            return Ok(());
-        } else {
-            return Err("unexpected reply");
-        }
-    }
-
-    async fn load_routing_table(aux_mutex: &Rc<Mutex<bool>>, linkno: u8, routing_table: &drtio_routing::RoutingTable,
-        timer: GlobalTimer) -> Result<(), &'static str> {
-        for i in 0..drtio_routing::DEST_COUNT {
-            let reply = aux_transact(aux_mutex, linkno, &Packet::RoutingSetPath {
-                destination: i as u8,
-                hops: routing_table.0[i]
-            }, timer).await?;
-            if reply != Packet::RoutingAck {
-                return Err("unexpected reply");
-            }
-        }
-        Ok(())
-    }
-
-    async fn set_rank(aux_mutex: &Rc<Mutex<bool>>, linkno: u8, rank: u8, timer: GlobalTimer) -> Result<(), &'static str> {
-        let reply = aux_transact(aux_mutex, linkno, &Packet::RoutingSetRank {
-            rank: rank
-        }, timer).await?;
-        if reply != Packet::RoutingAck {
-            return Err("unexpected reply");
-        }
-        Ok(())
-    }
-
-    async fn init_buffer_space(destination: u8, linkno: u8) {
-        let linkno = linkno as usize;
-        unsafe {
-            (csr::DRTIO[linkno].destination_write)(destination);
-            (csr::DRTIO[linkno].force_destination_write)(1);
-            (csr::DRTIO[linkno].o_get_buffer_space_write)(1);
-            while (csr::DRTIO[linkno].o_wait_read)() == 1 {}
-            info!("[DEST#{}] buffer space is {}",
-                destination, (csr::DRTIO[linkno].o_dbg_buffer_space_read)());
-            (csr::DRTIO[linkno].force_destination_write)(0);
-        }
-    }
-
-    async fn process_unsolicited_aux(aux_mutex: &Rc<Mutex<bool>>, linkno: u8) {
-        let _lock = aux_mutex.lock();
-        match drtioaux_async::recv(linkno).await {
-            Ok(Some(packet)) => warn!("[LINK#{}] unsolicited aux packet: {:?}", linkno, packet),
-            Ok(None) => (),
-            Err(_) => warn!("[LINK#{}] aux packet error", linkno)
-        }
-    }
-
-    async fn process_local_errors(linkno: u8) {
-        let errors;
-        let linkidx = linkno as usize;
-        unsafe {
-            errors = (csr::DRTIO[linkidx].protocol_error_read)();
-            (csr::DRTIO[linkidx].protocol_error_write)(errors);
-        }
-        if errors != 0 {
-            error!("[LINK#{}] error(s) found (0x{:02x}):", linkno, errors);
-            if errors & 1 != 0 {
-                error!("[LINK#{}] received packet of an unknown type", linkno);
-            }
-            if errors & 2 != 0 {
-                error!("[LINK#{}] received truncated packet", linkno);
-            }
-            if errors & 4 != 0 {
-                error!("[LINK#{}] timeout attempting to get remote buffer space", linkno);
-            }
-        }
-    }
-
-    async fn destination_set_up(routing_table: &drtio_routing::RoutingTable,
-            up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>,
-            destination: u8, up: bool) {
-        let mut up_destinations = up_destinations.borrow_mut();
-        up_destinations[destination as usize] = up;
-        if up {
-            drtio_routing::interconnect_enable(routing_table, 0, destination);
-            info!("[DEST#{}] destination is up", destination);
-        } else {
-            drtio_routing::interconnect_disable(destination);
-            info!("[DEST#{}] destination is down", destination);
-        }
-    }
-
-    async fn destination_up(up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>, destination: u8) -> bool {
-        let up_destinations = up_destinations.borrow();
-        up_destinations[destination as usize]
-    }
-
-    async fn destination_survey(aux_mutex: &Rc<Mutex<bool>>, routing_table: &drtio_routing::RoutingTable,
-            up_links: &[bool],
-            up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>,
-            timer: GlobalTimer) {
-        for destination in 0..drtio_routing::DEST_COUNT {
-            let hop = routing_table.0[destination][0];
-            let destination = destination as u8;
-
-            if hop == 0 {
-                /* local RTIO */
-                if !destination_up(up_destinations, destination).await {
-                    destination_set_up(routing_table, up_destinations, destination, true).await;
-                }
-            } else if hop as usize <= csr::DRTIO.len() {
-                let linkno = hop - 1;
-                if destination_up(up_destinations, destination).await {
-                    if up_links[linkno as usize] {
-                        let reply = aux_transact(aux_mutex, linkno, &Packet::DestinationStatusRequest {
-                            destination: destination
-                        }, timer).await;
-                        match reply {
-                            Ok(Packet::DestinationDownReply) =>
-                                destination_set_up(routing_table, up_destinations, destination, false).await,
-                            Ok(Packet::DestinationOkReply) => (),
-                            Ok(Packet::DestinationSequenceErrorReply { channel }) =>
-                                error!("[DEST#{}] RTIO sequence error involving channel 0x{:04x}", destination, channel),
-                            Ok(Packet::DestinationCollisionReply { channel }) =>
-                                error!("[DEST#{}] RTIO collision involving channel 0x{:04x}", destination, channel),
-                            Ok(Packet::DestinationBusyReply { channel }) =>
-                                error!("[DEST#{}] RTIO busy error involving channel 0x{:04x}", destination, channel),
-                            Ok(packet) => error!("[DEST#{}] received unexpected aux packet: {:?}", destination, packet),
-                            Err(e) => error!("[DEST#{}] communication failed ({})", destination, e)
-                        }
-                    } else {
-                        destination_set_up(routing_table, up_destinations, destination, false).await;
-                    }
-                } else {
-                    if up_links[linkno as usize] {
-                        let reply = aux_transact(aux_mutex, linkno, &Packet::DestinationStatusRequest {
-                            destination: destination
-                        }, timer).await;
-                        match reply {
-                            Ok(Packet::DestinationDownReply) => (),
-                            Ok(Packet::DestinationOkReply) => {
-                                destination_set_up(routing_table, up_destinations, destination, true).await;
-                                init_buffer_space(destination as u8, linkno).await;
-                            },
-                            Ok(packet) => error!("[DEST#{}] received unexpected aux packet: {:?}", destination, packet),
-                            Err(e) => error!("[DEST#{}] communication failed ({})", destination, e)
-                        }
-                    }
-                }
-            }
-        }
-    }
-
-    pub async fn link_task(aux_mutex: &Rc<Mutex<bool>>,
-            routing_table: &drtio_routing::RoutingTable,
-            up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>,
-            timer: GlobalTimer) {
-        let mut up_links = [false; csr::DRTIO.len()];
-        loop {
-            for linkno in 0..csr::DRTIO.len() {
-                let linkno = linkno as u8;
-                if up_links[linkno as usize] {
-                    /* link was previously up */
-                    if link_rx_up(linkno).await {
-                        process_unsolicited_aux(aux_mutex, linkno).await;
-                        process_local_errors(linkno).await;
-                    } else {
-                        info!("[LINK#{}] link is down", linkno);
-                        up_links[linkno as usize] = false;
-                    }
-                } else {
-                    /* link was previously down */
-                    if link_rx_up(linkno).await {
-                        info!("[LINK#{}] link RX became up, pinging", linkno);
-                        let ping_count = ping_remote(aux_mutex, linkno, timer).await;
-                        if ping_count > 0 {
-                            info!("[LINK#{}] remote replied after {} packets", linkno, ping_count);
-                            up_links[linkno as usize] = true;
-                            if let Err(e) = sync_tsc(aux_mutex, linkno, timer).await {
-                                error!("[LINK#{}] failed to sync TSC ({})", linkno, e);
-                            }
-                            if let Err(e) = load_routing_table(aux_mutex, linkno, routing_table, timer).await {
-                                error!("[LINK#{}] failed to load routing table ({})", linkno, e);
-                            }
-                            if let Err(e) = set_rank(aux_mutex, linkno, 1 as u8, timer).await {
-                                error!("[LINK#{}] failed to set rank ({})", linkno, e);
-                            }
-                            info!("[LINK#{}] link initialization completed", linkno);
-                        } else {
-                            error!("[LINK#{}] ping failed", linkno);
-                        }
-                    }
-                }
-            }
-            destination_survey(aux_mutex, routing_table, &up_links, up_destinations, timer).await;
-            let mut countdown = timer.countdown();
-            delay(&mut countdown, Milliseconds(200)).await;
-        }
-    }
-
-    #[allow(dead_code)]
-    pub fn reset(aux_mutex: Rc<Mutex<bool>>, mut timer: GlobalTimer) {
-        for linkno in 0..csr::DRTIO.len() {
-            unsafe {
-                (csr::DRTIO[linkno].reset_write)(1);
-            }
-        }
-        timer.delay_ms(1);
-        for linkno in 0..csr::DRTIO.len() {
-            unsafe {
-                (csr::DRTIO[linkno].reset_write)(0);
-            }
-        }
-
-        for linkno in 0..csr::DRTIO.len() {
-            let linkno = linkno as u8;
-            if task::block_on(link_rx_up(linkno)) {
-                let reply = task::block_on(aux_transact(&aux_mutex, linkno,
-                    &Packet::ResetRequest, timer));
-                match reply {
-                    Ok(Packet::ResetAck) => (),
-                    Ok(_) => error!("[LINK#{}] reset failed, received unexpected aux packet", linkno),
-                    Err(e) => error!("[LINK#{}] reset failed, aux packet error ({})", linkno, e)
-                }
-            }
-        }
-    }
-}
-
-#[cfg(not(has_drtio))]
-pub mod drtio {
-    use super::*;
-
-    pub fn startup(_aux_mutex: &Rc<Mutex<bool>>, _routing_table: &Rc<RefCell<drtio_routing::RoutingTable>>,
-        _up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>, _timer: GlobalTimer) {}
-    
-    #[allow(dead_code)]
-    pub fn reset(_aux_mutex: Rc<Mutex<bool>>, mut _timer: GlobalTimer) {}
-}
-
-pub fn startup(aux_mutex: &Rc<Mutex<bool>>,
-        routing_table: &Rc<RefCell<drtio_routing::RoutingTable>>,
-        up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>, 
-        timer: GlobalTimer) {
-    drtio::startup(aux_mutex, routing_table, up_destinations, timer);
-    unsafe {
-        csr::rtio_core::reset_phy_write(1);
-    }
-}
-
-#[allow(dead_code)]
-pub fn reset(aux_mutex: Rc<Mutex<bool>>, timer: GlobalTimer) {
-    unsafe {
-        csr::rtio_core::reset_write(1);
-    }
-    drtio::reset(aux_mutex, timer)
-}
--- a/src/satman/Cargo.toml
+++ b/src/satman/Cargo.toml
@ -1,28 +0,0 @@
-[package]
-authors = ["M-Labs"]
-name = "satman"
-version = "0.0.0"
-build = "build.rs"
-
-[features]
-target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706", "libboard_artiq/target_zc706"]
-target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc", "libboard_artiq/target_kasli_soc"]
-default = ["target_zc706", ]
-
-[build-dependencies]
-build_zynq = { path = "../libbuild_zynq" }
-
-[dependencies]
-log = { version = "0.4", default-features = false }
-embedded-hal = "0.2"
-
-libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["ipv6"]}
-libsupport_zynq = { default-features = false, features = ["alloc_core"], git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
-libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
-libasync = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
-libregister = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
-libconfig = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["ipv6"] }
-
-libboard_artiq = { path = "../libboard_artiq" }
-unwind = { path = "../libunwind" }
-libc = { path = "../libc" }
--- a/src/satman/build.rs
+++ b/src/satman/build.rs
@ -1,6 +0,0 @@
-extern crate build_zynq;
-
-fn main() {
-    build_zynq::add_linker_script();
-    build_zynq::cfg();
-}
--- a/src/satman/src/main.rs
+++ b/src/satman/src/main.rs
@ -1,639 +0,0 @@
-#![no_std]
-#![no_main]
-#![feature(never_type, panic_info_message, asm, naked_functions)]
-#![feature(alloc_error_handler)]
-
-#[macro_use]
-extern crate log;
-
-extern crate embedded_hal;
-
-extern crate libboard_zynq;
-extern crate libboard_artiq;
-extern crate libsupport_zynq;
-extern crate libcortex_a9;
-extern crate libregister;
-
-extern crate unwind;
-
-extern crate alloc;
-
-use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic, stdio};
-use libsupport_zynq::ram;
-#[cfg(has_si5324)]
-use libboard_artiq::si5324;
-use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read, init_gateware};
-use libcortex_a9::{spin_lock_yield, interrupt_handler, regs::{MPIDR, SP}, notify_spin_lock, asm, l2c::enable_l2_cache};
-use libregister::{RegisterW, RegisterR};
-
-use embedded_hal::blocking::delay::DelayUs;
-use core::sync::atomic::{AtomicBool, Ordering};
-
-mod repeater;
-
-fn drtiosat_reset(reset: bool) {
-    unsafe {
-        csr::drtiosat::reset_write(if reset { 1 } else { 0 });
-    }
-}
-
-fn drtiosat_reset_phy(reset: bool) {
-    unsafe {
-        csr::drtiosat::reset_phy_write(if reset { 1 } else { 0 });
-    }
-}
-
-fn drtiosat_link_rx_up() -> bool {
-    unsafe {
-        csr::drtiosat::rx_up_read() == 1
-    }
-}
-
-fn drtiosat_tsc_loaded() -> bool {
-    unsafe {
-        let tsc_loaded = csr::drtiosat::tsc_loaded_read() == 1;
-        if tsc_loaded {
-            csr::drtiosat::tsc_loaded_write(1);
-        }
-        tsc_loaded
-    }
-}
-
-
-#[cfg(has_drtio_routing)]
-macro_rules! forward {
-    ($routing_table:expr, $destination:expr, $rank:expr, $repeaters:expr, $packet:expr, $timer:expr) => {{
-        let hop = $routing_table.0[$destination as usize][$rank as usize];
-        if hop != 0 {
-            let repno = (hop - 1) as usize;
-            if repno < $repeaters.len() {
-                return $repeaters[repno].aux_forward($packet, $timer);
-            } else {
-                return Err(drtioaux::Error::RoutingError);
-            }
-        }
-    }}
-}
-
-#[cfg(not(has_drtio_routing))]
-macro_rules! forward {
-    ($routing_table:expr, $destination:expr, $rank:expr, $repeaters:expr, $packet:expr, $timer:expr) => {}
-}
-
-fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
-        _routing_table: &mut drtio_routing::RoutingTable, _rank: &mut u8,
-        packet: drtioaux::Packet, timer: &mut GlobalTimer, i2c: &mut I2c) -> Result<(), drtioaux::Error> {
-    // In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
-    // and u16 otherwise; hence the `as _` conversion.
-    match packet {
-        drtioaux::Packet::EchoRequest =>
-            drtioaux::send(0, &drtioaux::Packet::EchoReply),
-        drtioaux::Packet::ResetRequest => {
-            info!("resetting RTIO");
-            drtiosat_reset(true);
-            timer.delay_us(100);
-            drtiosat_reset(false);
-            for rep in _repeaters.iter() {
-                if let Err(e) = rep.rtio_reset(timer) {
-                    error!("failed to issue RTIO reset ({:?})", e);
-                }
-            }
-            drtioaux::send(0, &drtioaux::Packet::ResetAck)
-        },
-
-        drtioaux::Packet::DestinationStatusRequest { destination: _destination } => {
-            #[cfg(has_drtio_routing)]
-            let hop = _routing_table.0[_destination as usize][*_rank as usize];
-            #[cfg(not(has_drtio_routing))]
-            let hop = 0;
-
-            if hop == 0 {
-                let errors;
-                unsafe {
-                    errors = csr::drtiosat::rtio_error_read();
-                }
-                if errors & 1 != 0 {
-                    let channel;
-                    unsafe {
-                        channel = csr::drtiosat::sequence_error_channel_read();
-                        csr::drtiosat::rtio_error_write(1);
-                    }
-                    drtioaux::send(0,
-                        &drtioaux::Packet::DestinationSequenceErrorReply { channel })?;
-                } else if errors & 2 != 0 {
-                    let channel;
-                    unsafe {
-                        channel = csr::drtiosat::collision_channel_read();
-                        csr::drtiosat::rtio_error_write(2);
-                    }
-                    drtioaux::send(0,
-                        &drtioaux::Packet::DestinationCollisionReply { channel })?;
-                } else if errors & 4 != 0 {
-                    let channel;
-                    unsafe {
-                        channel = csr::drtiosat::busy_channel_read();
-                        csr::drtiosat::rtio_error_write(4);
-                    }
-                    drtioaux::send(0,
-                        &drtioaux::Packet::DestinationBusyReply { channel })?;
-                }
-                else {
-                    drtioaux::send(0, &drtioaux::Packet::DestinationOkReply)?;
-                }
-            }
-
-            #[cfg(has_drtio_routing)]
-            {
-                if hop != 0 {
-                    let hop = hop as usize;
-                    if hop <= csr::DRTIOREP.len() {
-                        let repno = hop - 1;
-                        match _repeaters[repno].aux_forward(&drtioaux::Packet::DestinationStatusRequest {
-                            destination: _destination
-                        }, timer) {
-                            Ok(()) => (),
-                            Err(drtioaux::Error::LinkDown) => drtioaux::send(0, &drtioaux::Packet::DestinationDownReply)?,
-                            Err(e) => {
-                                drtioaux::send(0, &drtioaux::Packet::DestinationDownReply)?;
-                                error!("aux error when handling destination status request: {:?}", e);
-                            },
-                        }
-                    } else {
-                        drtioaux::send(0, &drtioaux::Packet::DestinationDownReply)?;
-                    }
-                }
-            }
-
-            Ok(())
-        }
-
-        #[cfg(has_drtio_routing)]
-        drtioaux::Packet::RoutingSetPath { destination, hops } => {
-            _routing_table.0[destination as usize] = hops;
-            for rep in _repeaters.iter() {
-                if let Err(e) = rep.set_path(destination, &hops, timer) {
-                    error!("failed to set path ({:?})", e);
-                }
-            }
-            drtioaux::send(0, &drtioaux::Packet::RoutingAck)
-        }
-        #[cfg(has_drtio_routing)]
-        drtioaux::Packet::RoutingSetRank { rank } => {
-            *_rank = rank;
-            drtio_routing::interconnect_enable_all(_routing_table, rank);
-
-            let rep_rank = rank + 1;
-            for rep in _repeaters.iter() {
-                if let Err(e) = rep.set_rank(rep_rank, timer) {
-                    error!("failed to set rank ({:?})", e);
-                }
-            }
-
-            info!("rank: {}", rank);
-            info!("routing table: {}", _routing_table);
-
-            drtioaux::send(0, &drtioaux::Packet::RoutingAck)
-        }
-
-        #[cfg(not(has_drtio_routing))]
-        drtioaux::Packet::RoutingSetPath { destination: _, hops: _ } => {
-            drtioaux::send(0, &drtioaux::Packet::RoutingAck)
-        }
-        #[cfg(not(has_drtio_routing))]
-        drtioaux::Packet::RoutingSetRank { rank: _ } => {
-            drtioaux::send(0, &drtioaux::Packet::RoutingAck)
-        }
-
-        drtioaux::Packet::MonitorRequest { destination: _destination, channel: _channel, probe: _probe } => {
-            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
-            let value;
-            #[cfg(has_rtio_moninj)]
-            unsafe {
-                csr::rtio_moninj::mon_chan_sel_write(channel as _);
-                csr::rtio_moninj::mon_probe_sel_write(probe);
-                csr::rtio_moninj::mon_value_update_write(1);
-                value = csr::rtio_moninj::mon_value_read();
-            }
-            #[cfg(not(has_rtio_moninj))]
-            {
-                value = 0;
-            }
-            let reply = drtioaux::Packet::MonitorReply { value: value as u32 };
-            drtioaux::send(0, &reply)
-        },
-        drtioaux::Packet::InjectionRequest { destination: _destination, channel: _channel, 
-                                             overrd: _overrd, value: _value } => {
-            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
-            #[cfg(has_rtio_moninj)]
-            unsafe {
-                csr::rtio_moninj::inj_chan_sel_write(channel as _);
-                csr::rtio_moninj::inj_override_sel_write(overrd);
-                csr::rtio_moninj::inj_value_write(value);
-            }
-            Ok(())
-        },
-        drtioaux::Packet::InjectionStatusRequest { destination: _destination, 
-                                                   channel: _channel, overrd: _overrd } => {
-            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
-            let value;
-            #[cfg(has_rtio_moninj)]
-            unsafe {
-                csr::rtio_moninj::inj_chan_sel_write(channel as _);
-                csr::rtio_moninj::inj_override_sel_write(overrd);
-                value = csr::rtio_moninj::inj_value_read();
-            }
-            #[cfg(not(has_rtio_moninj))]
-            {
-                value = 0;
-            }
-            drtioaux::send(0, &drtioaux::Packet::InjectionStatusReply { value: value })
-        },
-
-        drtioaux::Packet::I2cStartRequest { destination: _destination, busno: _busno } => {
-            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
-            let succeeded = i2c.start().is_ok();
-            drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
-        }
-        drtioaux::Packet::I2cRestartRequest { destination: _destination, busno: _busno } => {
-            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
-            let succeeded = i2c.restart().is_ok();
-            drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
-        }
-        drtioaux::Packet::I2cStopRequest { destination: _destination, busno: _busno } => {
-            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
-            let succeeded = i2c.stop().is_ok();
-            drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
-        }
-        drtioaux::Packet::I2cWriteRequest { destination: _destination, busno: _busno, data } => {
-            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
-            match i2c.write(data) {
-                Ok(ack) => drtioaux::send(0,
-                    &drtioaux::Packet::I2cWriteReply { succeeded: true, ack: ack }),
-                Err(_) => drtioaux::send(0,
-                    &drtioaux::Packet::I2cWriteReply { succeeded: false, ack: false })
-            }
-        }
-        drtioaux::Packet::I2cReadRequest { destination: _destination, busno: _busno, ack } => {
-            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
-            match i2c.read(ack) {
-                Ok(data) => drtioaux::send(0,
-                    &drtioaux::Packet::I2cReadReply { succeeded: true, data: data }),
-                Err(_) => drtioaux::send(0,
-                    &drtioaux::Packet::I2cReadReply { succeeded: false, data: 0xff })
-            }
-        }
-
-        drtioaux::Packet::SpiSetConfigRequest { destination: _destination, busno: _busno, 
-                                                flags: _flags, length: _length, div: _div, cs: _cs } => {
-            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
-            // todo: reimplement when/if SPI is available
-            //let succeeded = spi::set_config(busno, flags, length, div, cs).is_ok();
-            drtioaux::send(0,
-                &drtioaux::Packet::SpiBasicReply { succeeded: false })
-        },
-        drtioaux::Packet::SpiWriteRequest { destination: _destination, busno: _busno, data: _data } => {
-            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
-            // todo: reimplement when/if SPI is available
-            //let succeeded = spi::write(busno, data).is_ok();
-            drtioaux::send(0,
-                &drtioaux::Packet::SpiBasicReply { succeeded: false })
-        }
-        drtioaux::Packet::SpiReadRequest { destination: _destination, busno: _busno } => {
-            forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
-            // todo: reimplement when/if SPI is available
-            // match spi::read(busno) {
-            //     Ok(data) => drtioaux::send(0,
-            //         &drtioaux::Packet::SpiReadReply { succeeded: true, data: data }),
-            //     Err(_) => drtioaux::send(0,
-            //         &drtioaux::Packet::SpiReadReply { succeeded: false, data: 0 })
-            // }
-            drtioaux::send(0,
-                &drtioaux::Packet::SpiReadReply { succeeded: false, data: 0 })
-        }
-
-        _ => {
-            warn!("received unexpected aux packet");
-            Ok(())
-        }
-    }
-}
-
-fn process_aux_packets(repeaters: &mut [repeater::Repeater],
-        routing_table: &mut drtio_routing::RoutingTable, rank: &mut u8, 
-        timer: &mut GlobalTimer, i2c: &mut I2c) {
-    let result =
-        drtioaux::recv(0).and_then(|packet| {
-            if let Some(packet) = packet {
-                process_aux_packet(repeaters, routing_table, rank, packet, timer, i2c)
-            } else {
-                Ok(())
-            }
-        });
-    match result {
-        Ok(()) => (),
-        Err(e) => warn!("aux packet error ({:?})", e)
-    }
-}
-
-fn drtiosat_process_errors() {
-    let errors;
-    unsafe {
-        errors = csr::drtiosat::protocol_error_read();
-    }
-    if errors & 1 != 0 {
-        error!("received packet of an unknown type");
-    }
-    if errors & 2 != 0 {
-        error!("received truncated packet");
-    }
-    if errors & 4 != 0 {
-        let destination;
-        unsafe {
-            destination = csr::drtiosat::buffer_space_timeout_dest_read();
-        }
-        error!("timeout attempting to get buffer space from CRI, destination=0x{:02x}", destination)
-    }
-    if errors & 8 != 0 {
-        let channel;
-        let timestamp_event;
-        let timestamp_counter;
-        unsafe {
-            channel = csr::drtiosat::underflow_channel_read();
-            timestamp_event = csr::drtiosat::underflow_timestamp_event_read() as i64;
-            timestamp_counter = csr::drtiosat::underflow_timestamp_counter_read() as i64;
-        }
-        error!("write underflow, channel={}, timestamp={}, counter={}, slack={}",
-               channel, timestamp_event, timestamp_counter, timestamp_event-timestamp_counter);
-    }
-    if errors & 16 != 0 {
-        error!("write overflow");
-    }
-    unsafe {
-        csr::drtiosat::protocol_error_write(errors);
-    }
-}
-
-
-#[cfg(has_rtio_crg)]
-fn init_rtio_crg(timer: GlobalTimer) {
-    unsafe {
-        csr::rtio_crg::pll_reset_write(0);
-    }
-    timer.delay_us(150);
-    let locked = unsafe { csr::rtio_crg::pll_locked_read() != 0 };
-    if !locked {
-        error!("RTIO clock failed");
-    }
-}
-
-#[cfg(not(has_rtio_crg))]
-fn init_rtio_crg(_timer: GlobalTimer) { }
-
-fn hardware_tick(ts: &mut u64, timer: &mut GlobalTimer) {
-    let now = timer.get_time();
-    let mut ts_ms = Milliseconds(*ts);
-    if now > ts_ms {
-        ts_ms = now + Milliseconds(200);
-        *ts = ts_ms.0;
-    }
-}
-
-#[cfg(all(has_si5324, rtio_frequency = "125.0"))]
-const SI5324_SETTINGS: si5324::FrequencySettings
-    = si5324::FrequencySettings {
-    n1_hs  : 5,
-    nc1_ls : 8,
-    n2_hs  : 7,
-    n2_ls  : 360,
-    n31    : 63,
-    n32    : 63,
-    bwsel  : 4,
-    crystal_ref: true
-};
-
-#[cfg(all(has_si5324, rtio_frequency = "100.0"))]
-const SI5324_SETTINGS: si5324::FrequencySettings
-    = si5324::FrequencySettings {
-    n1_hs  : 5,
-    nc1_ls : 10,
-    n2_hs  : 10,
-    n2_ls  : 250,
-    n31    : 50,
-    n32    : 50,
-    bwsel  : 4,
-    crystal_ref: true
-};
-
-static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17];
-
-#[no_mangle]
-pub extern fn main_core0() -> i32 {
-    enable_l2_cache(0x8);
-
-    let mut timer = GlobalTimer::start();
-
-    let buffer_logger = unsafe {
-        logger::BufferLogger::new(&mut LOG_BUFFER[..])
-    };
-    buffer_logger.set_uart_log_level(log::LevelFilter::Info);
-    buffer_logger.register();
-    log::set_max_level(log::LevelFilter::Info);
-    
-    init_gateware();
-
-    info!("ARTIQ satellite manager starting...");
-    info!("gateware ident {}", identifier_read(&mut [0; 64]));
-
-    ram::init_alloc_core0();
-
-    let mut i2c = I2c::i2c0();
-    i2c.init().expect("I2C initialization failed");
-
-    #[cfg(has_si5324)]
-    si5324::setup(&mut i2c, &SI5324_SETTINGS, si5324::Input::Ckin1, &mut timer).expect("cannot initialize Si5324");
-
-    unsafe {
-        csr::drtio_transceiver::stable_clkin_write(1);
-    }
-    timer.delay_us(1500); // wait for CPLL/QPLL lock
-
-    unsafe {
-        csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
-    }
-    init_rtio_crg(timer);
-
-    #[cfg(has_drtio_routing)]
-    let mut repeaters = [repeater::Repeater::default(); csr::DRTIOREP.len()];
-    #[cfg(not(has_drtio_routing))]
-    let mut repeaters = [repeater::Repeater::default(); 0];
-    for i in 0..repeaters.len() {
-        repeaters[i] = repeater::Repeater::new(i as u8);
-    } 
-    let mut routing_table = drtio_routing::RoutingTable::default_empty();
-    let mut rank = 1;
-
-    let mut hardware_tick_ts = 0;
-
-    loop {
-        while !drtiosat_link_rx_up() {
-            drtiosat_process_errors();
-            #[allow(unused_mut)]
-            for mut rep in repeaters.iter_mut() {
-                rep.service(&routing_table, rank, &mut timer);
-            }
-            hardware_tick(&mut hardware_tick_ts, &mut timer);
-        }
-
-        info!("uplink is up, switching to recovered clock");
-        #[cfg(has_siphaser)]
-        {
-            si5324::siphaser::select_recovered_clock(&mut i2c, true, &mut timer).expect("failed to switch clocks");
-            si5324::siphaser::calibrate_skew(&mut timer).expect("failed to calibrate skew");
-        }
-
-        drtioaux::reset(0);
-        drtiosat_reset(false);
-        drtiosat_reset_phy(false);
-
-        while drtiosat_link_rx_up() {
-            drtiosat_process_errors();
-            process_aux_packets(&mut repeaters, &mut routing_table, &mut rank, &mut timer, &mut i2c);
-            #[allow(unused_mut)]
-            for mut rep in repeaters.iter_mut() {
-                rep.service(&routing_table, rank, &mut timer);
-            }
-            hardware_tick(&mut hardware_tick_ts, &mut timer);
-            if drtiosat_tsc_loaded() {
-                info!("TSC loaded from uplink");
-                for rep in repeaters.iter() {
-                    if let Err(e) = rep.sync_tsc(&mut timer) {
-                        error!("failed to sync TSC ({:?})", e);
-                    }
-                }
-                if let Err(e) = drtioaux::send(0, &drtioaux::Packet::TSCAck) {
-                    error!("aux packet error: {:?}", e);
-                }
-            }
-        }
-
-        drtiosat_reset_phy(true);
-        drtiosat_reset(true);
-        drtiosat_tsc_loaded();
-        info!("uplink is down, switching to local oscillator clock");
-        #[cfg(has_siphaser)]
-        si5324::siphaser::select_recovered_clock(&mut i2c, false, &mut timer).expect("failed to switch clocks");
-    }
-}
-
-extern "C" {
-    static mut __stack1_start: u32;
-}
-
-interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
-    if MPIDR.read().cpu_id() == 1{
-        let mpcore = mpcore::RegisterBlock::mpcore();
-        let mut gic = gic::InterruptController::gic(mpcore);
-        let id = gic.get_interrupt_id();
-        if id.0 == 0 {
-            gic.end_interrupt(id);
-            asm::exit_irq();
-            SP.write(&mut __stack1_start as *mut _ as u32);
-            asm::enable_irq();
-            CORE1_RESTART.store(false, Ordering::Relaxed);
-            notify_spin_lock();
-            main_core1();
-        }
-    stdio::drop_uart();
-    }
-    loop {}
-});
-
-static mut PANICKED: [bool; 2] = [false; 2];
-
-static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
-
-pub fn restart_core1() {
-    let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
-    CORE1_RESTART.store(true, Ordering::Relaxed);
-    interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
-    while CORE1_RESTART.load(Ordering::Relaxed) {
-        spin_lock_yield();
-    }
-}
-
-#[no_mangle]
-pub fn main_core1() {
-    let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
-    interrupt_controller.enable_interrupts();
-
-    loop {}
-}
-
-#[no_mangle]
-pub extern fn exception(_vect: u32, _regs: *const u32, pc: u32, ea: u32) {
-
-    fn hexdump(addr: u32) {
-        let addr = (addr - addr % 4) as *const u32;
-        let mut ptr  = addr;
-        println!("@ {:08p}", ptr);
-        for _ in 0..4 {
-            print!("+{:04x}: ", ptr as usize - addr as usize);
-            print!("{:08x} ",   unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
-            print!("{:08x} ",   unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
-            print!("{:08x} ",   unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
-            print!("{:08x}\n",  unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
-        }
-    }
-
-    hexdump(pc);
-    hexdump(ea);
-    panic!("exception at PC 0x{:x}, EA 0x{:x}", pc, ea)
-}
-
-#[no_mangle] // https://github.com/rust-lang/rust/issues/{38281,51647}
-#[panic_handler]
-pub fn panic_fmt(info: &core::panic::PanicInfo) -> ! {
-    let id = MPIDR.read().cpu_id() as usize;
-    print!("Core {} ", id);
-    unsafe {
-        if PANICKED[id] {
-            println!("nested panic!");
-            loop {}
-        }
-        PANICKED[id] = true;
-    }
-    print!("panic at ");
-    if let Some(location) = info.location() {
-        print!("{}:{}:{}", location.file(), location.line(), location.column());
-    } else {
-        print!("unknown location");
-    }
-    if let Some(message) = info.message() {
-        println!(": {}", message);
-    } else {
-        println!("");
-    }
-
-
-    loop {}
-}
-
-// linker symbols
-extern "C" {
-    static __text_start: u32;
-    static __text_end: u32;
-    static __exidx_start: u32;
-    static __exidx_end: u32;
-}
-
-#[no_mangle]
-extern fn dl_unwind_find_exidx(_pc: *const u32, len_ptr: *mut u32) -> *const u32 {
-    let length;
-    let start: *const u32;
-    unsafe {
-        length = (&__exidx_end as *const u32).offset_from(&__exidx_start) as u32;
-        start = &__exidx_start;
-        *len_ptr = length;
-    }
-    start
-}
--- a/src/satman/src/repeater.rs
+++ b/src/satman/src/repeater.rs
@ -1,290 +0,0 @@
-use libboard_artiq::{drtioaux, drtio_routing};
-use libboard_zynq::timer::GlobalTimer;
-
-#[cfg(has_drtio_routing)]
-use libboard_artiq::{pl::csr};
-#[cfg(has_drtio_routing)]
-use libboard_zynq::time::Milliseconds;
-#[cfg(has_drtio_routing)]
-use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
-
-#[cfg(has_drtio_routing)]
-fn rep_link_rx_up(repno: u8) -> bool {
-    let repno = repno as usize;
-    unsafe {
-        (csr::DRTIOREP[repno].rx_up_read)() == 1
-    }
-}
-
-#[cfg(has_drtio_routing)]
-#[derive(Clone, Copy, PartialEq)]
-enum RepeaterState {
-    Down,
-    SendPing { ping_count: u16 },
-    WaitPingReply { ping_count: u16, timeout: Milliseconds },
-    Up,
-    Failed
-}
-
-#[cfg(has_drtio_routing)]
-impl Default for RepeaterState {
-    fn default() -> RepeaterState { RepeaterState::Down }
-}
-
-#[cfg(has_drtio_routing)]
-#[derive(Clone, Copy, Default)]
-pub struct Repeater {
-    repno: u8,
-    auxno: u8,
-    state: RepeaterState
-}
-
-#[cfg(has_drtio_routing)]
-impl Repeater {
-    pub fn new(repno: u8) -> Repeater {
-        Repeater {
-            repno: repno,
-            auxno: repno + 1,
-            state: RepeaterState::Down
-        }
-    }
-
-    #[allow(dead_code)]
-    pub fn is_up(&self) -> bool {
-        self.state == RepeaterState::Up
-    }
-
-    pub fn service(&mut self, routing_table: &drtio_routing::RoutingTable, rank: u8,
-        timer: &mut GlobalTimer) {
-        self.process_local_errors();
-
-        match self.state {
-            RepeaterState::Down => {
-                if rep_link_rx_up(self.repno) {
-                    info!("[REP#{}] link RX became up, pinging", self.repno);
-                    self.state = RepeaterState::SendPing { ping_count: 0 };
-                }
-            }
-            RepeaterState::SendPing { ping_count } => {
-                if rep_link_rx_up(self.repno) {
-                    drtioaux::send(self.auxno, &drtioaux::Packet::EchoRequest).unwrap();
-                    self.state = RepeaterState::WaitPingReply {
-                        ping_count: ping_count + 1,
-                        timeout: timer.get_time() + Milliseconds(100)
-                    }
-                } else {
-                    error!("[REP#{}] link RX went down during ping", self.repno);
-                    self.state = RepeaterState::Down;
-                }
-            }
-            RepeaterState::WaitPingReply { ping_count, timeout } => {
-                if rep_link_rx_up(self.repno) {
-                    if let Ok(Some(drtioaux::Packet::EchoReply)) = drtioaux::recv(self.auxno) {
-                        info!("[REP#{}] remote replied after {} packets", self.repno, ping_count);
-                        self.state = RepeaterState::Up;
-                        if let Err(e) = self.sync_tsc(timer) {
-                            error!("[REP#{}] failed to sync TSC ({:?})", self.repno, e);
-                            self.state = RepeaterState::Failed;
-                            return;
-                        }
-                        if let Err(e) = self.load_routing_table(routing_table, timer) {
-                            error!("[REP#{}] failed to load routing table ({:?})", self.repno, e);
-                            self.state = RepeaterState::Failed;
-                            return;
-                        }
-                        if let Err(e) = self.set_rank(rank + 1, timer) {
-                            error!("[REP#{}] failed to set rank ({:?})", self.repno, e);
-                            self.state = RepeaterState::Failed;
-                            return;
-                        }
-                    } else {
-                        if timer.get_time() > timeout {
-                            if ping_count > 200 {
-                                error!("[REP#{}] ping failed", self.repno);
-                                self.state = RepeaterState::Failed;
-                            } else {
-                                self.state = RepeaterState::SendPing { ping_count: ping_count };
-                            }
-                        }
-                    }
-                } else {
-                    error!("[REP#{}] link RX went down during ping", self.repno);
-                    self.state = RepeaterState::Down;
-                }
-            }
-            RepeaterState::Up => {
-                self.process_unsolicited_aux();
-                if !rep_link_rx_up(self.repno) {
-                    info!("[REP#{}] link is down", self.repno);
-                    self.state = RepeaterState::Down;
-                }
-            }
-            RepeaterState::Failed => {
-                if !rep_link_rx_up(self.repno) {
-                    info!("[REP#{}] link is down", self.repno);
-                    self.state = RepeaterState::Down;
-                }
-            }
-        }
-    }
-
-    fn process_unsolicited_aux(&self) {
-        match drtioaux::recv(self.auxno) {
-            Ok(Some(packet)) => warn!("[REP#{}] unsolicited aux packet: {:?}", self.repno, packet),
-            Ok(None) => (),
-            Err(_) => warn!("[REP#{}] aux packet error", self.repno)
-        }
-    }
-
-    fn process_local_errors(&self) {
-        let repno = self.repno as usize;
-        let errors;
-        unsafe {
-            errors = (csr::DRTIOREP[repno].protocol_error_read)();
-        }
-        if errors & 1 != 0 {
-            error!("[REP#{}] received packet of an unknown type", repno);
-        }
-        if errors & 2 != 0 {
-            error!("[REP#{}] received truncated packet", repno);
-        }
-        if errors & 4 != 0 {
-            let cmd;
-            let chan_sel;
-            unsafe {
-                cmd = (csr::DRTIOREP[repno].command_missed_cmd_read)();
-                chan_sel = (csr::DRTIOREP[repno].command_missed_chan_sel_read)();
-            }
-            error!("[REP#{}] CRI command missed, cmd={}, chan_sel=0x{:06x}", repno, cmd, chan_sel)
-        }
-        if errors & 8 != 0 {
-            let destination;
-            unsafe {
-                destination = (csr::DRTIOREP[repno].buffer_space_timeout_dest_read)();
-            }
-            error!("[REP#{}] timeout attempting to get remote buffer space, destination=0x{:02x}", repno, destination);
-        }
-        unsafe {
-            (csr::DRTIOREP[repno].protocol_error_write)(errors);
-        }
-    }
-
-    fn recv_aux_timeout(&self, timeout: u32, timer: &mut GlobalTimer) -> Result<drtioaux::Packet, drtioaux::Error> {
-        let max_time = timer.get_time() + Milliseconds(timeout.into());
-        loop {
-            if !rep_link_rx_up(self.repno) {
-                return Err(drtioaux::Error::LinkDown);
-            }
-            if timer.get_time() > max_time {
-                return Err(drtioaux::Error::TimedOut);
-            }
-            match drtioaux::recv(self.auxno) {
-                Ok(Some(packet)) => return Ok(packet),
-                Ok(None) => (),
-                Err(e) => return Err(e)
-            }
-        }
-    }
-
-    pub fn aux_forward(&self, request: &drtioaux::Packet, timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> {
-        if self.state != RepeaterState::Up {
-            return Err(drtioaux::Error::LinkDown);
-        }
-        drtioaux::send(self.auxno, request).unwrap();
-        let reply = self.recv_aux_timeout(200, timer)?;
-        drtioaux::send(0, &reply).unwrap();
-        Ok(())
-    }
-
-    pub fn sync_tsc(&self, timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> {
-        if self.state != RepeaterState::Up {
-            return Ok(());
-        }
-
-        let repno = self.repno as usize;
-        unsafe {
-            (csr::DRTIOREP[repno].set_time_write)(1);
-            while (csr::DRTIOREP[repno].set_time_read)() == 1 {}
-        }
-
-        // TSCAck is the only aux packet that is sent spontaneously
-        // by the satellite, in response to a TSC set on the RT link.
-        let reply = self.recv_aux_timeout(10000, timer)?;
-        if reply == drtioaux::Packet::TSCAck {
-            return Ok(());
-        } else {
-            return Err(drtioaux::Error::UnexpectedReply);
-        }
-    }
-
-    pub fn set_path(&self, destination: u8, hops: &[u8; drtio_routing::MAX_HOPS], timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> {
-        if self.state != RepeaterState::Up {
-            return Ok(());
-        }
-
-        drtioaux::send(self.auxno, &drtioaux::Packet::RoutingSetPath {
-            destination: destination,
-            hops: *hops
-        }).unwrap();
-        let reply = self.recv_aux_timeout(200, timer)?;
-        if reply != drtioaux::Packet::RoutingAck {
-            return Err(drtioaux::Error::UnexpectedReply);
-        }
-        Ok(())
-    }
-
-    pub fn load_routing_table(&self, routing_table: &drtio_routing::RoutingTable, timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> {
-        for i in 0..drtio_routing::DEST_COUNT {
-            self.set_path(i as u8, &routing_table.0[i], timer)?;
-        }
-        Ok(())
-    }
-
-    pub fn set_rank(&self, rank: u8, timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> {
-        if self.state != RepeaterState::Up {
-            return Ok(());
-        }
-        drtioaux::send(self.auxno, &drtioaux::Packet::RoutingSetRank {
-            rank: rank
-        }).unwrap();
-        let reply = self.recv_aux_timeout(200, timer)?;
-        if reply != drtioaux::Packet::RoutingAck {
-            return Err(drtioaux::Error::UnexpectedReply);
-        }
-        Ok(())
-    }
-
-    pub fn rtio_reset(&self, timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> {
-        let repno = self.repno as usize;
-        unsafe { (csr::DRTIOREP[repno].reset_write)(1); }
-        timer.delay_us(100);
-        unsafe { (csr::DRTIOREP[repno].reset_write)(0); }
-
-        if self.state != RepeaterState::Up {
-            return Ok(());
-        }
-
-        drtioaux::send(self.auxno, &drtioaux::Packet::ResetRequest).unwrap();
-        let reply = self.recv_aux_timeout(200, timer)?;
-        if reply != drtioaux::Packet::ResetAck {
-            return Err(drtioaux::Error::UnexpectedReply);
-        }
-        Ok(())
-    }
-}
-
-#[cfg(not(has_drtio_routing))]
-#[derive(Clone, Copy, Default)]
-pub struct Repeater {
-}
-
-#[cfg(not(has_drtio_routing))]
-impl Repeater {
-    pub fn new(_repno: u8) -> Repeater { Repeater::default() }
-
-    pub fn service(&self, _routing_table: &drtio_routing::RoutingTable, _rank: u8, _timer: &mut GlobalTimer) { }
-
-    pub fn sync_tsc(&self, _timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> { Ok(()) }
-
-    pub fn rtio_reset(&self, _timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> { Ok(()) }
-}
--- a/src/szl/Cargo.toml
+++ b/src/szl/Cargo.toml
@ -0,0 +1,22 @@
+[package]
+name = "szl"
+description = "Simple Zynq Loader"
+version = "0.1.0"
+authors = ["M-Labs"]
+edition = "2018"
+
+[features]
+target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
+default = ["target_zc706"]
+
+[dependencies]
+log = "0.4"
+byteorder = { version = "1.3", default-features = false }
+core_io = { version = "0.1", features = ["collections"] }
+
+libconfig = { path = "../libconfig" }
+libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libsupport_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libregister = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+
--- a/src/szl/build.rs
+++ b/src/szl/build.rs
@ -0,0 +1,22 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    println!("cargo:rerun-if-changed=build.rs");
+    let out = env::var("OUT_DIR").unwrap();
+    let out_dir = &PathBuf::from(&out);
+
+    // Put the linker script somewhere the linker can find it
+    File::create(out_dir.join("link.x"))
+        .unwrap()
+        .write_all(include_bytes!("link.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out_dir.display());
+
+    // Only re-run the build script when link.x is changed,
+    // instead of when any part of the source code changes.
+    println!("cargo:rerun-if-changed=link.x");
+}
+
--- a/src/szl/link.x
+++ b/src/szl/link.x
@ -0,0 +1,69 @@
+ENTRY(Reset);
+
+MEMORY
+{
+    /* 256 kB On-Chip Memory */
+    OCM : ORIGIN = 0, LENGTH = 0x30000
+    SDRAM : ORIGIN = 0x00100000, LENGTH = 0x1FF00000
+    OCM3 : ORIGIN = 0xFFFF0000, LENGTH = 0x10000
+}
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.text.exceptions));
+        *(.text.boot);
+        *(.text .text.*);
+    } > OCM
+ 
+    .rodata : ALIGN(4)
+    {
+        *(.rodata .rodata.*);
+    } > OCM
+ 
+    .data : ALIGN(4)
+    {
+        *(.data .data.*);
+    } > OCM
+
+    .heap (NOLOAD) : ALIGN(8)
+    {
+        __runtime_start = .;
+        . += 0x8000000;
+        __runtime_end = .;
+        __heap0_start = .;
+        . += 0x8000000;
+        __heap0_end = .;
+    } > SDRAM
+ 
+    .bss (NOLOAD) : ALIGN(4)
+    {
+        __bss_start = .;
+        *(.bss .bss.*);
+        . = ALIGN(4);
+        __bss_end = .;
+    } > OCM3
+
+    .stack1 (NOLOAD) : ALIGN(8)
+    {
+        __stack1_end = .;
+        . += 0x100;
+        __stack1_start = .;
+    } > OCM3
+
+    .stack0 (NOLOAD) : ALIGN(8)
+    {
+        __stack0_end = .;
+        . += 0x4000;
+        __stack0_start = .;
+    } > OCM3
+
+    /DISCARD/ :
+    {
+        /* Unused exception related info that only wastes space */
+        *(.ARM.exidx);
+        *(.ARM.exidx.*);
+        *(.ARM.extab.*);
+    }
+}
--- a/src/szl/src/main.rs
+++ b/src/szl/src/main.rs
@ -0,0 +1,169 @@
+#![no_std]
+#![no_main]
+
+extern crate alloc;
+extern crate log;
+
+mod netboot;
+
+use alloc::rc::Rc;
+use core::mem;
+use core_io::{Read, Seek};
+use libboard_zynq::{
+    self as zynq,
+    clocks::source::{ArmPll, ClockSource, IoPll},
+    clocks::Clocks,
+    logger, println, sdio, slcr,
+    timer::GlobalTimer,
+};
+use libconfig::{bootgen, sd_reader, Config};
+use libcortex_a9::{
+    asm::{dsb, isb},
+    cache::{bpiall, dcciall, iciallu},
+    enable_fpu,
+    l2c::enable_l2_cache,
+};
+use libregister::RegisterR;
+use libsupport_zynq::ram;
+use log::info;
+
+extern "C" {
+    static mut __runtime_start: usize;
+    static mut __runtime_end: usize;
+}
+
+fn boot_sd<File: Read + Seek>(
+    file: &mut Option<File>,
+    runtime_start: *mut u8,
+    runtime_max: usize,
+) -> Result<(), ()> {
+    if file.is_none() {
+        log::error!("No bootgen file");
+        return Err(());
+    }
+    let mut file = file.as_mut().unwrap();
+    info!("Loading gateware");
+    bootgen::load_bitstream(&mut file).map_err(|e| log::error!("Cannot load gateware: {:?}", e))?;
+
+    info!("Loading runtime");
+    let runtime =
+        bootgen::get_runtime(&mut file).map_err(|e| log::error!("Cannot load runtime: {:?}", e))?;
+
+    if runtime.len() > runtime_max {
+        log::error!(
+            "Runtime binary too large, max {} but got {}",
+            runtime_max,
+            runtime.len()
+        );
+    }
+    unsafe {
+        let target = core::slice::from_raw_parts_mut(runtime_start, runtime.len());
+        target.copy_from_slice(&runtime);
+    }
+    Ok(())
+}
+
+#[no_mangle]
+pub fn main_core0() {
+    GlobalTimer::start();
+    enable_fpu();
+    logger::init().unwrap();
+    log::set_max_level(log::LevelFilter::Debug);
+    println!(
+        r#"
+
+                     __________   __
+                    / ___/__  /  / /
+                    \__ \  / /  / /
+                   ___/ / / /__/ /___
+                  /____/ /____/_____/
+
+                   (C) 2020 M-Labs
+"#
+    );
+    info!("Simple Zynq Loader starting...");
+    enable_l2_cache();
+
+    const CPU_FREQ: u32 = 800_000_000;
+
+    ArmPll::setup(2 * CPU_FREQ);
+    Clocks::set_cpu_freq(CPU_FREQ);
+    IoPll::setup(1_000_000_000);
+    libboard_zynq::stdio::drop_uart(); // reinitialize UART after clocking change
+    let mut ddr = zynq::ddr::DdrRam::ddrram();
+    ram::init_alloc_core0();
+
+    let sdio0 = sdio::Sdio::sdio0(true);
+    let fs = if sdio0.is_card_inserted() {
+        info!("Card inserted. Mounting file system.");
+        let sd = sdio::sd_card::SdCard::from_sdio(sdio0).unwrap();
+        let reader = sd_reader::SdReader::new(sd);
+        reader
+            .mount_fatfs(sd_reader::PartitionEntry::Entry1)
+            .map(|v| Rc::new(v))
+            .ok()
+    } else {
+        info!("No SD card inserted.");
+        None
+    };
+    let fs_ref = fs.as_ref();
+    let root_dir = fs_ref.map(|fs| fs.root_dir());
+    let mut bootgen_file = root_dir.and_then(|root_dir| root_dir.open_file("/BOOT.BIN").ok());
+    let config = Config::from_fs(fs.clone());
+
+    unsafe {
+        let max_len =
+            &__runtime_end as *const usize as usize - &__runtime_start as *const usize as usize;
+        match slcr::RegisterBlock::unlocked(|slcr| slcr.boot_mode.read().boot_mode_pins()) {
+            slcr::BootModePins::Jtag => netboot::netboot(
+                &mut bootgen_file,
+                config,
+                &mut __runtime_start as *mut usize as *mut u8,
+                max_len,
+            ),
+            slcr::BootModePins::SdCard => {
+                if boot_sd(
+                    &mut bootgen_file,
+                    &mut __runtime_start as *mut usize as *mut u8,
+                    max_len,
+                )
+                .is_err()
+                {
+                    log::error!("Error booting from SD card");
+                    log::info!("Fall back on netboot");
+                    netboot::netboot(
+                        &mut bootgen_file,
+                        config,
+                        &mut __runtime_start as *mut usize as *mut u8,
+                        max_len,
+                    )
+                }
+            }
+            v => {
+                panic!("Boot mode {:?} not supported", v);
+            }
+        };
+    }
+
+    info!("Preparing for runtime execution");
+    // Flush data cache entries for all of L1 cache, including
+    // Memory/Instruction Synchronization Barriers
+    dcciall();
+    iciallu();
+    bpiall();
+    dsb();
+    isb();
+
+    // Start core0 only, for compatibility with FSBL.
+    info!("executing payload");
+    unsafe {
+        (mem::transmute::<*mut u8, fn()>(ddr.ptr::<u8>()))();
+    }
+
+    loop {}
+}
+
+#[no_mangle]
+pub fn main_core1() {
+    panic!("core1 started but should not have");
+}
--- a/src/szl/src/netboot.rs
+++ b/src/szl/src/netboot.rs
@ -0,0 +1,399 @@
+use alloc::vec;
+use alloc::vec::Vec;
+use byteorder::{ByteOrder, NetworkEndian};
+use core_io::{Read, Seek};
+use libboard_zynq::{
+    devc,
+    eth::Eth,
+    smoltcp::{
+        self,
+        iface::{EthernetInterfaceBuilder, NeighborCache},
+        time::Instant,
+        wire::IpCidr,
+    },
+    timer::GlobalTimer,
+};
+use libconfig::{bootgen, net_settings, Config};
+
+enum NetConnState {
+    WaitCommand,
+    FirmwareLength(usize, u8),
+    FirmwareDownload(usize, usize),
+    FirmwareWaitO,
+    FirmwareWaitK,
+    GatewareLength(usize, u8),
+    GatewareDownload(usize, usize),
+    GatewareWaitO,
+    GatewareWaitK,
+}
+
+struct NetConn {
+    state: NetConnState,
+    firmware_downloaded: bool,
+    gateware_downloaded: bool,
+}
+
+impl NetConn {
+    pub fn new() -> NetConn {
+        NetConn {
+            state: NetConnState::WaitCommand,
+            firmware_downloaded: false,
+            gateware_downloaded: false,
+        }
+    }
+
+    pub fn reset(&mut self) {
+        self.state = NetConnState::WaitCommand;
+        self.firmware_downloaded = false;
+        self.gateware_downloaded = false;
+    }
+
+    fn input_partial<File: Read + Seek>(
+        &mut self,
+        bootgen_file: &mut Option<File>,
+        runtime_start: *mut u8,
+        runtime_max_len: usize,
+        buf: &[u8],
+        storage: &mut Vec<u8>,
+        mut boot_callback: impl FnMut(),
+    ) -> Result<usize, ()> {
+        match self.state {
+            NetConnState::WaitCommand => match buf[0] {
+                b'F' => {
+                    log::info!("Received firmware load command");
+                    self.state = NetConnState::FirmwareLength(0, 0);
+                    Ok(1)
+                }
+                b'G' => {
+                    log::info!("Received gateware load command");
+                    self.state = NetConnState::GatewareLength(0, 0);
+                    storage.clear();
+                    Ok(1)
+                }
+                b'B' => {
+                    if !self.gateware_downloaded {
+                        log::info!("Gateware not loaded via netboot");
+                        if bootgen_file.is_none() {
+                            log::error!("No bootgen file to load gateware");
+                            return Err(());
+                        }
+                        log::info!("Attempting to load from SD card");
+                        if let Err(e) = bootgen::load_bitstream(bootgen_file.as_mut().unwrap()) {
+                            log::error!("Gateware load failed: {:?}", e);
+                            return Err(());
+                        }
+                    }
+                    if self.firmware_downloaded {
+                        log::info!("Received boot command");
+                        boot_callback();
+                        self.state = NetConnState::WaitCommand;
+                        Ok(1)
+                    } else {
+                        log::error!("Received boot command, but no firmware downloaded");
+                        Err(())
+                    }
+                }
+                _ => {
+                    log::error!("Received unknown netboot command: 0x{:02x}", buf[0]);
+                    Err(())
+                }
+            },
+            NetConnState::FirmwareLength(firmware_length, recv_bytes) => {
+                let firmware_length = (firmware_length << 8) | (buf[0] as usize);
+                let recv_bytes = recv_bytes + 1;
+                if recv_bytes == 4 {
+                    if firmware_length > runtime_max_len {
+                        log::error!(
+                            "Runtime too large, maximum {} but requested {}",
+                            runtime_max_len,
+                            firmware_length
+                        );
+                        return Err(());
+                    }
+                    self.state = NetConnState::FirmwareDownload(firmware_length, 0);
+                    storage.clear();
+                    storage.reserve(firmware_length);
+                } else {
+                    self.state = NetConnState::FirmwareLength(firmware_length, recv_bytes);
+                }
+                Ok(1)
+            }
+            NetConnState::FirmwareDownload(firmware_length, recv_bytes) => {
+                let max_length = firmware_length - recv_bytes;
+                let buf = if buf.len() > max_length {
+                    &buf[..max_length]
+                } else {
+                    &buf[..]
+                };
+                let length = buf.len();
+
+                storage.extend_from_slice(buf);
+
+                let recv_bytes = recv_bytes + length;
+                if recv_bytes == firmware_length {
+                    self.state = NetConnState::FirmwareWaitO;
+                    Ok(length)
+                } else {
+                    self.state = NetConnState::FirmwareDownload(firmware_length, recv_bytes);
+                    Ok(length)
+                }
+            }
+            NetConnState::FirmwareWaitO => {
+                if buf[0] == b'O' {
+                    self.state = NetConnState::FirmwareWaitK;
+                    Ok(1)
+                } else {
+                    log::error!("End-of-firmware confirmation failed");
+                    Err(())
+                }
+            }
+            NetConnState::FirmwareWaitK => {
+                if buf[0] == b'K' {
+                    log::info!("Firmware successfully downloaded");
+                    self.state = NetConnState::WaitCommand;
+                    self.firmware_downloaded = true;
+                    {
+                        let dest = unsafe {
+                            core::slice::from_raw_parts_mut(runtime_start, storage.len())
+                        };
+                        dest.copy_from_slice(storage);
+                    }
+                    Ok(1)
+                } else {
+                    log::error!("End-of-firmware confirmation failed");
+                    Err(())
+                }
+            }
+
+            NetConnState::GatewareLength(gateware_length, recv_bytes) => {
+                let gateware_length = (gateware_length << 8) | (buf[0] as usize);
+                let recv_bytes = recv_bytes + 1;
+                if recv_bytes == 4 {
+                    self.state = NetConnState::GatewareDownload(gateware_length, 0);
+                    storage.clear();
+                    storage.reserve_exact(gateware_length);
+                } else {
+                    self.state = NetConnState::GatewareLength(gateware_length, recv_bytes);
+                }
+                Ok(1)
+            }
+            NetConnState::GatewareDownload(gateware_length, recv_bytes) => {
+                let max_length = gateware_length - recv_bytes;
+                let buf = if buf.len() > max_length {
+                    &buf[..max_length]
+                } else {
+                    &buf[..]
+                };
+                let length = buf.len();
+
+                storage.extend_from_slice(buf);
+
+                let recv_bytes = recv_bytes + length;
+                if recv_bytes == gateware_length {
+                    self.state = NetConnState::GatewareWaitO;
+                    Ok(length)
+                } else {
+                    self.state = NetConnState::GatewareDownload(gateware_length, recv_bytes);
+                    Ok(length)
+                }
+            }
+            NetConnState::GatewareWaitO => {
+                if buf[0] == b'O' {
+                    self.state = NetConnState::GatewareWaitK;
+                    Ok(1)
+                } else {
+                    log::error!("End-of-gateware confirmation failed");
+                    Err(())
+                }
+            }
+            NetConnState::GatewareWaitK => {
+                if buf[0] == b'K' {
+                    log::info!("Preprocessing bitstream...");
+                    // find sync word 0xFFFFFFFF AA995566
+                    let sync_word: [u8; 8] = [0xFF, 0xFF, 0xFF, 0xFF, 0xAA, 0x99, 0x55, 0x66];
+                    let mut i = 0;
+                    let mut state = 0;
+                    while i < storage.len() {
+                        if storage[i] == sync_word[state] {
+                            state += 1;
+                            if state == sync_word.len() {
+                                break;
+                            }
+                        } else {
+                            // backtrack
+                            // not very efficient but we only have 8 elements
+                            'outer: while state > 0 {
+                                state -= 1;
+                                for j in 0..state {
+                                    if storage[i - j] != sync_word[state - j] {
+                                        continue 'outer;
+                                    }
+                                }
+                                break;
+                            }
+                        }
+                        i += 1;
+                    }
+                    if state != sync_word.len() {
+                        log::error!("Sync word not found in bitstream (corrupted?)");
+                        return Err(());
+                    }
+                    // we need the sync word
+                    // i was pointing to the last element in the sync sequence
+                    i -= sync_word.len() - 1;
+                    // // append no-op
+                    // storage.extend_from_slice(&[0x20, 0, 0, 0]);
+                    let bitstream = &mut storage[i..];
+                    {
+                        // swap endian
+                        let swap = unsafe {
+                            core::slice::from_raw_parts_mut(
+                                bitstream.as_mut_ptr() as usize as *mut u32,
+                                bitstream.len() / 4,
+                            )
+                        };
+                        NetworkEndian::from_slice_u32(swap);
+                    }
+                    unsafe {
+                        // align to 64 bytes
+                        let ptr = alloc::alloc::alloc(
+                            alloc::alloc::Layout::from_size_align(bitstream.len(), 64).unwrap(),
+                        );
+                        let buffer = core::slice::from_raw_parts_mut(ptr, bitstream.len());
+                        buffer.copy_from_slice(bitstream);
+
+                        let mut devcfg = devc::DevC::new();
+                        devcfg.enable();
+                        let result = devcfg.program(&buffer);
+                        core::ptr::drop_in_place(ptr);
+                        if let Err(e) = result {
+                            log::error!("Error during FPGA startup: {}", e);
+                            return Err(());
+                        }
+                    }
+
+                    log::info!("Gateware successfully downloaded");
+                    self.state = NetConnState::WaitCommand;
+                    self.gateware_downloaded = true;
+                    Ok(1)
+                } else {
+                    log::info!("End-of-gateware confirmation failed");
+                    Err(())
+                }
+            }
+        }
+    }
+
+    fn input<File: Read + Seek>(
+        &mut self,
+        bootgen_file: &mut Option<File>,
+        runtime_start: *mut u8,
+        runtime_max_len: usize,
+        buf: &[u8],
+        storage: &mut Vec<u8>,
+        mut boot_callback: impl FnMut(),
+    ) -> Result<(), ()> {
+        let mut remaining = &buf[..];
+        while !remaining.is_empty() {
+            let read_cnt = self.input_partial(
+                bootgen_file,
+                runtime_start,
+                runtime_max_len,
+                remaining,
+                storage,
+                &mut boot_callback,
+            )?;
+            remaining = &remaining[read_cnt..];
+        }
+        Ok(())
+    }
+}
+
+pub fn netboot<File: Read + Seek>(
+    bootgen_file: &mut Option<File>,
+    cfg: Config,
+    runtime_start: *mut u8,
+    runtime_max_len: usize,
+) {
+    log::info!("Preparing network for netboot");
+    let net_addresses = net_settings::get_adresses(&cfg);
+    log::info!("Network addresses: {}", net_addresses);
+    let eth = Eth::eth0(net_addresses.hardware_addr.0.clone());
+    let eth = eth.start_rx(8);
+    let mut eth = eth.start_tx(8);
+
+    let mut neighbor_map = [None; 2];
+    let neighbor_cache = NeighborCache::new(&mut neighbor_map[..]);
+    let mut ip_addrs = [IpCidr::new(net_addresses.ipv4_addr, 0)];
+    let mut interface = EthernetInterfaceBuilder::new(&mut eth)
+        .ethernet_addr(net_addresses.hardware_addr)
+        .ip_addrs(&mut ip_addrs[..])
+        .neighbor_cache(neighbor_cache)
+        .finalize();
+
+    let mut rx_storage = vec![0; 4096];
+    let mut tx_storage = vec![0; 128];
+
+    let mut socket_set_entries: [_; 1] = Default::default();
+    let mut sockets = smoltcp::socket::SocketSet::new(&mut socket_set_entries[..]);
+
+    let tcp_rx_buffer = smoltcp::socket::TcpSocketBuffer::new(&mut rx_storage[..]);
+    let tcp_tx_buffer = smoltcp::socket::TcpSocketBuffer::new(&mut tx_storage[..]);
+    let tcp_socket = smoltcp::socket::TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer);
+    let tcp_handle = sockets.add(tcp_socket);
+
+    let mut net_conn = NetConn::new();
+    let mut storage = Vec::new();
+    let mut boot_flag = false;
+    let timer = unsafe { GlobalTimer::get() };
+
+    log::info!("Waiting for connections...");
+    loop {
+        let timestamp = Instant::from_millis(timer.get_time().0 as i64);
+        {
+            let socket = &mut *sockets.get::<smoltcp::socket::TcpSocket>(tcp_handle);
+
+            if boot_flag {
+                return;
+            }
+            if !socket.is_open() {
+                socket.listen(4269).unwrap() // 0x10ad
+            }
+
+            if socket.may_recv() {
+                if socket
+                    .recv(|data| {
+                        (
+                            data.len(),
+                            net_conn
+                                .input(
+                                    bootgen_file,
+                                    runtime_start,
+                                    runtime_max_len,
+                                    data,
+                                    &mut storage,
+                                    || {
+                                        boot_flag = true;
+                                    },
+                                )
+                                .is_err(),
+                        )
+                    })
+                    .unwrap()
+                {
+                    net_conn.reset();
+                    socket.close();
+                }
+            } else if socket.may_send() {
+                net_conn.reset();
+                socket.close();
+            }
+        }
+
+        match interface.poll(&mut sockets, timestamp) {
+            Ok(_) => (),
+            Err(smoltcp::Error::Unrecognized) => (),
+            Err(err) => log::error!("Network error: {}", err),
+        }
+    }
+}
Author	SHA1	Message	Date
pca006132	b09f981c84	test compiler-builtins changes	2020-10-13 19:21:22 +08:00
pca006132	02b386dee6	runtime/kernel/dma: reduced replay overhead We can just flush the cache once when we get the handle, instead of everytime before replay.	2020-09-09 21:18:26 +08:00