makefile: automate runtime dependencies

src/Cargo.lock

@@ -390,6 +390,7 @@ dependencies = [
  "cslice",
  "dwarf",
  "dyld",
+ "embedded-hal",
  "fatfs",
  "futures",
  "libasync",
@@ -399,6 +400,7 @@ dependencies = [
  "libregister",
  "libsupport_zynq",
  "log",
+ "nb",
  "num-derive",
  "num-traits",
  "unwind",

src/Makefile

@@ -9,7 +9,7 @@ all: ../build/firmware/armv7-none-eabihf/release/szl
 	mkdir -p ../build
 	python zc706.py -r ../build/pl.rs -V $(VARIANT)
 
-../build/firmware/armv7-none-eabihf/release/runtime: .cargo/* armv7-none-eabihf.json Cargo.lock Cargo.toml libdyld/* libdyld/src/* libcoreio/* libcoreio/src/* libcoreio/src/io/* runtime/* runtime/src/* ../build/pl.rs libc/* libc/src/* libdwarf/* libdwarf/src/* libunwind/* llvm_libunwind/src/*
+../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs $(shell find . -path ./szl -prune -o -print)
 	XBUILD_SYSROOT_PATH=`pwd`/../build/sysroot cargo xbuild --release -p runtime --target-dir ../build/firmware
 
 ../build/szl-payload.bin.lzma: ../build/firmware/armv7-none-eabihf/release/runtime

src/runtime/Cargo.toml

@@ -14,18 +14,22 @@ num-traits = { version = "0.2", default-features = false }
 num-derive = "0.3"
 cslice = "0.3"
 log = "0.4"
+nb = "0.1"
+embedded-hal = "0.2"
 core_io = { version = "0.1", features = ["collections"] }
 byteorder = { version = "1.3", default-features = false }
 void = { version = "1", default-features = false }
 futures = { version = "0.3", default-features = false, features = ["async-await"] }
 async-recursion = "0.3"
+fatfs = { version = "0.3", features = ["core_io"], default-features = false }
+
 libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
 libsupport_zynq = { default-features = false, git = "https://git.m-labs.hk/M-Labs/zc706.git" }
 libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
 libasync = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
 libregister = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
+
 dyld = { path = "../libdyld" }
 dwarf = { path = "../libdwarf" }
 unwind = { path = "../libunwind" }
 libc = { path = "../libc" }
-fatfs = { version = "0.3", features = ["core_io"], default-features = false }

src/runtime/src/comms.rs

@@ -290,8 +290,8 @@ async fn handle_connection(stream: &TcpStream, control: Rc<RefCell<kernel::Contr
     }
 }
 
-pub fn main(timer: GlobalTimer) {
+pub fn main(timer: GlobalTimer, cfg: &config::Config) {
-    let net_addresses = net_settings::get_adresses();
+    let net_addresses = net_settings::get_adresses(cfg);
     info!("network addresses: {}", net_addresses);
 
     let eth = zynq::eth::Eth::default(net_addresses.hardware_addr.0.clone());
@@ -329,14 +329,10 @@ pub fn main(timer: GlobalTimer) {
         }
     };
 
-    let startup_kernel: Option<Vec<u8>>;
-    let cfg = config::Config::new();
-    startup_kernel = cfg.as_ref().ok().and_then(|cfg| cfg.read("startup").ok());
-
     Sockets::init(32);
 
     let control: Rc<RefCell<kernel::Control>> = Rc::new(RefCell::new(kernel::Control::start()));
-    if let Some(buffer) = startup_kernel {
+    if let Ok(buffer) = cfg.read("startup") {
         info!("Loading startup kernel...");
         if let Ok(()) = task::block_on(load_kernel(buffer, &control, None)) {
             info!("Starting startup kernel...");

src/runtime/src/config.rs

@@ -11,6 +11,7 @@ pub enum Error<'a> {
     IoError(io::Error),
     Utf8Error(FromUtf8Error),
     KeyNotFoundError(&'a str),
+    NoConfig,
 }
 
 pub type Result<'a, T> = core::result::Result<T, Error<'a>>;
@@ -22,6 +23,7 @@ impl<'a> fmt::Display for Error<'a> {
             Error::IoError(error) => write!(f, "I/O error: {}", error),
             Error::Utf8Error(error) => write!(f, "UTF-8 error: {}", error),
             Error::KeyNotFoundError(name) => write!(f, "Configuration key `{}` not found", name),
+            Error::NoConfig => write!(f, "Configuration not present"),
         }
     }
 }
@@ -61,7 +63,7 @@ fn parse_config<'a>(
 }
 
 pub struct Config {
-    fs: fatfs::FileSystem<sd_reader::SdReader>,
+    fs: Option<fatfs::FileSystem<sd_reader::SdReader>>,
 }
 
 impl Config {
@@ -74,20 +76,28 @@ impl Config {
         let reader = sd_reader::SdReader::new(sd);
 
         let fs = reader.mount_fatfs(sd_reader::PartitionEntry::Entry1)?;
-        Ok(Config { fs })
+        Ok(Config { fs: Some(fs) })
+    }
+
+    pub fn new_dummy() -> Self {
+        Config { fs: None }
     }
 
     pub fn read<'b>(&self, key: &'b str) -> Result<'b, Vec<u8>> {
-        let root_dir = self.fs.root_dir();
+        if let Some(fs) = &self.fs {
-        let mut buffer: Vec<u8> = Vec::new();
+            let root_dir = fs.root_dir();
-        match root_dir.open_file(&["/CONFIG/", key, ".BIN"].concat()) {
+            let mut buffer: Vec<u8> = Vec::new();
-            Ok(mut f) => f.read_to_end(&mut buffer).map(|_| ())?,
+            match root_dir.open_file(&["/CONFIG/", key, ".BIN"].concat()) {
-            Err(_) => match root_dir.open_file("/CONFIG.TXT") {
+                Ok(mut f) => f.read_to_end(&mut buffer).map(|_| ())?,
-                Ok(f) => parse_config(key, &mut buffer, f)?,
+                Err(_) => match root_dir.open_file("/CONFIG.TXT") {
-                Err(_) => return Err(Error::KeyNotFoundError(key)),
+                    Ok(f) => parse_config(key, &mut buffer, f)?,
-            },
+                    Err(_) => return Err(Error::KeyNotFoundError(key)),
-        };
+                },
-        Ok(buffer)
+            };
+            Ok(buffer)
+        } else {
+            Err(Error::NoConfig)
+        }
     }
 
     pub fn read_str<'b>(&self, key: &'b str) -> Result<'b, String> {

src/runtime/src/eh_artiq.rs

@@ -213,7 +213,7 @@ pub unsafe extern fn raise(exception: *const Exception) -> ! {
             INFLIGHT.backtrace_size += 1;
         }
     });
-    crate::kernel::terminate(INFLIGHT.exception.as_ref().unwrap(), INFLIGHT.backtrace[..INFLIGHT.backtrace_size].as_mut());
+    crate::kernel::core1::terminate(INFLIGHT.exception.as_ref().unwrap(), INFLIGHT.backtrace[..INFLIGHT.backtrace_size].as_mut());
 }
 
 pub unsafe extern fn reraise() -> ! {

src/runtime/src/kernel.rs

@@ -1,384 +0,0 @@
-use core::{ptr, mem};
-use log::{debug, info, error};
-use alloc::{vec::Vec, sync::Arc, string::String};
-use cslice::{CSlice, AsCSlice};
-
-use libcortex_a9::{enable_fpu, cache::dcci_slice, mutex::Mutex, sync_channel::{self, sync_channel}};
-use libsupport_zynq::boot::Core1;
-
-use dyld;
-use crate::eh_artiq;
-use crate::rpc;
-use crate::rtio;
-
-#[derive(Debug)]
-pub struct RPCException {
-    pub name: String,
-    pub message: String,
-    pub param: [i64; 3],
-    pub file: String,
-    pub line: i32,
-    pub column: i32,
-    pub function: String
-}
-
-#[derive(Debug)]
-pub enum Message {
-    LoadRequest(Arc<Vec<u8>>),
-    LoadCompleted,
-    LoadFailed,
-    StartRequest,
-    KernelFinished,
-    KernelException(&'static eh_artiq::Exception<'static>, &'static [usize]),
-    RpcSend { is_async: bool, data: Arc<Vec<u8>> },
-    RpcRecvRequest(*mut ()),
-    RpcRecvReply(Result<usize, RPCException>),
-}
-
-static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<Message>>> = Mutex::new(None);
-static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<Message>>> = Mutex::new(None);
-
-pub struct Control {
-    core1: Core1,
-    pub tx: sync_channel::Sender<Message>,
-    pub rx: sync_channel::Receiver<Message>,
-}
-
-impl Control {
-    pub fn start() -> Self {
-        let core1 = Core1::start(true);
-
-        let (core0_tx, core1_rx) = sync_channel(4);
-        let (core1_tx, core0_rx) = sync_channel(4);
-        *CHANNEL_0TO1.lock() = Some(core1_rx);
-        *CHANNEL_1TO0.lock() = Some(core1_tx);
-
-        Control {
-            core1,
-            tx: core0_tx,
-            rx: core0_rx,
-        }
-    }
-
-    pub fn restart(&mut self) {
-        *CHANNEL_0TO1.lock() = None;
-        *CHANNEL_1TO0.lock() = None;
-
-        self.core1.restart();
-
-        let (core0_tx, core1_rx) = sync_channel(4);
-        let (core1_tx, core0_rx) = sync_channel(4);
-        *CHANNEL_0TO1.lock() = Some(core1_rx);
-        *CHANNEL_1TO0.lock() = Some(core1_tx);
-        self.tx = core0_tx;
-        self.rx = core0_rx;
-    }
-}
-
-static mut KERNEL_CHANNEL_0TO1: *mut () = ptr::null_mut();
-static mut KERNEL_CHANNEL_1TO0: *mut () = ptr::null_mut();
-
-fn rpc_send_common(is_async: bool, service: u32, tag: &CSlice<u8>, data: *const *const ()) {
-    let core1_tx: &mut sync_channel::Sender<Message> = unsafe { mem::transmute(KERNEL_CHANNEL_1TO0) };
-    let mut buffer = Vec::<u8>::new();
-    rpc::send_args(&mut buffer, service, tag.as_ref(), data).expect("RPC encoding failed");
-    core1_tx.send(Message::RpcSend { is_async: is_async, data: Arc::new(buffer) });
-}
-
-extern fn rpc_send(service: u32, tag: &CSlice<u8>, data: *const *const ()) {
-    rpc_send_common(false, service, tag, data);
-}
-
-extern fn rpc_send_async(service: u32, tag: &CSlice<u8>, data: *const *const ()) {
-    rpc_send_common(true, service, tag, data);
-}
-
-static mut KERNEL_LOAD_ADDR: usize = 0;
-
-pub fn terminate(exception: &'static eh_artiq::Exception<'static>, backtrace: &'static mut [usize]) -> ! {
-    let load_addr = unsafe {
-        KERNEL_LOAD_ADDR
-    };
-    let mut cursor = 0;
-    // The address in the backtrace is relocated, so we have to convert it back to the address in
-    // the original python script, and remove those Rust function backtrace.
-    for i in 0..backtrace.len() {
-        if backtrace[i] >= load_addr {
-            backtrace[cursor] = backtrace[i] - load_addr;
-            cursor += 1;
-        }
-    }
-
-    let core1_tx: &mut sync_channel::Sender<Message> = unsafe { mem::transmute(KERNEL_CHANNEL_1TO0) };
-    core1_tx.send(Message::KernelException(exception, &backtrace[..cursor]));
-    loop {}
-}
-
-unsafe fn attribute_writeback(typeinfo: *const ()) {
-    struct Attr {
-        offset: usize,
-        tag:    CSlice<'static, u8>,
-        name:   CSlice<'static, u8>
-    }
-
-    struct Type {
-        attributes: *const *const Attr,
-        objects:    *const *const ()
-    }
-
-    let mut tys = typeinfo as *const *const Type;
-    while !(*tys).is_null() {
-        let ty = *tys;
-        tys = tys.offset(1);
-
-        let mut objects = (*ty).objects;
-        while !(*objects).is_null() {
-            let object = *objects;
-            objects = objects.offset(1);
-
-            let mut attributes = (*ty).attributes;
-            while !(*attributes).is_null() {
-                let attribute = *attributes;
-                attributes = attributes.offset(1);
-
-                if (*attribute).tag.len() > 0 {
-                    rpc_send_async(0, &(*attribute).tag, [
-                        &object as *const _ as *const (),
-                        &(*attribute).name as *const _ as *const (),
-                        (object as usize + (*attribute).offset) as *const ()
-                    ].as_ptr());
-                }
-            }
-        }
-    }
-}
-
-extern fn rpc_recv(slot: *mut ()) -> usize {
-    let core1_rx: &mut sync_channel::Receiver<Message> = unsafe { mem::transmute(KERNEL_CHANNEL_0TO1) };
-    let core1_tx: &mut sync_channel::Sender<Message> = unsafe { mem::transmute(KERNEL_CHANNEL_1TO0) };
-    core1_tx.send(Message::RpcRecvRequest(slot));
-    let reply = core1_rx.recv();
-    match *reply {
-        Message::RpcRecvReply(Ok(alloc_size)) => alloc_size,
-        Message::RpcRecvReply(Err(exception)) => unsafe {
-            eh_artiq::raise(&eh_artiq::Exception {
-                name:     exception.name.as_bytes().as_c_slice(),
-                file:     exception.file.as_bytes().as_c_slice(),
-                line:     exception.line as u32,
-                column:   exception.column as u32,
-                function: exception.function.as_bytes().as_c_slice(),
-                message:  exception.message.as_bytes().as_c_slice(),
-                param:    exception.param
-            })
-        },
-        _ => panic!("received unexpected reply to RpcRecvRequest: {:?}", reply)
-    }
-}
-
-macro_rules! api {
-    ($i:ident) => ({
-        extern { static $i: u8; }
-        unsafe { api!($i = &$i as *const _) }
-    });
-    ($i:ident, $d:item) => ({
-        $d
-        api!($i = $i)
-    });
-    ($i:ident = $e:expr) => {
-        (stringify!($i), $e as *const ())
-    }
-}
-
-fn resolve(required: &[u8]) -> Option<u32> {
-    let api = &[
-        // timing
-        api!(now_mu = rtio::now_mu),
-        api!(at_mu = rtio::at_mu),
-        api!(delay_mu = rtio::delay_mu),
-
-        // rpc
-        api!(rpc_send = rpc_send),
-        api!(rpc_send_async = rpc_send_async),
-        api!(rpc_recv = rpc_recv),
-
-        // rtio
-        api!(rtio_init = rtio::init),
-        api!(rtio_get_destination_status = rtio::get_destination_status),
-        api!(rtio_get_counter = rtio::get_counter),
-        api!(rtio_output = rtio::output),
-        api!(rtio_output_wide = rtio::output_wide),
-        api!(rtio_input_timestamp = rtio::input_timestamp),
-        api!(rtio_input_data = rtio::input_data),
-        api!(rtio_input_timestamped_data = rtio::input_timestamped_data),
-
-        // Double-precision floating-point arithmetic helper functions
-        // RTABI chapter 4.1.2, Table 2
-        api!(__aeabi_dadd),
-        api!(__aeabi_ddiv),
-        api!(__aeabi_dmul),
-        api!(__aeabi_dsub),
-        // Double-precision floating-point comparison helper functions
-        // RTABI chapter 4.1.2, Table 3
-        api!(__aeabi_dcmpeq),
-        api!(__aeabi_dcmpeq),
-        api!(__aeabi_dcmplt),
-        api!(__aeabi_dcmple),
-        api!(__aeabi_dcmpge),
-        api!(__aeabi_dcmpgt),
-        api!(__aeabi_dcmpun),
-        // Single-precision floating-point arithmetic helper functions
-        // RTABI chapter 4.1.2, Table 4
-        api!(__aeabi_fadd),
-        api!(__aeabi_fdiv),
-        api!(__aeabi_fmul),
-        api!(__aeabi_fsub),
-        // Single-precision floating-point comparison helper functions
-        // RTABI chapter 4.1.2, Table 5
-        api!(__aeabi_fcmpeq),
-        api!(__aeabi_fcmpeq),
-        api!(__aeabi_fcmplt),
-        api!(__aeabi_fcmple),
-        api!(__aeabi_fcmpge),
-        api!(__aeabi_fcmpgt),
-        api!(__aeabi_fcmpun),
-        // Floating-point to integer conversions.
-        // RTABI chapter 4.1.2, Table 6
-        api!(__aeabi_d2iz),
-        api!(__aeabi_d2uiz),
-        api!(__aeabi_d2lz),
-        api!(__aeabi_d2ulz),
-        api!(__aeabi_f2iz),
-        api!(__aeabi_f2uiz),
-        api!(__aeabi_f2lz),
-        api!(__aeabi_f2ulz),
-        // Conversions between floating types.
-        // RTABI chapter 4.1.2, Table 7
-        api!(__aeabi_f2d),
-        // Integer to floating-point conversions.
-        // RTABI chapter 4.1.2, Table 8
-        api!(__aeabi_i2d),
-        api!(__aeabi_ui2d),
-        api!(__aeabi_l2d),
-        api!(__aeabi_ul2d),
-        api!(__aeabi_i2f),
-        api!(__aeabi_ui2f),
-        api!(__aeabi_l2f),
-        api!(__aeabi_ul2f),
-        // Long long helper functions
-        // RTABI chapter 4.2, Table 9
-        api!(__aeabi_lmul),
-        api!(__aeabi_llsl),
-        api!(__aeabi_llsr),
-        api!(__aeabi_lasr),
-        // Integer division functions
-        // RTABI chapter 4.3.1
-        api!(__aeabi_idiv),
-        api!(__aeabi_ldivmod),
-        api!(__aeabi_uidiv),
-        api!(__aeabi_uldivmod),
-        // 4.3.4 Memory copying, clearing, and setting
-        api!(__aeabi_memcpy8),
-        api!(__aeabi_memcpy4),
-        api!(__aeabi_memcpy),
-        api!(__aeabi_memmove8),
-        api!(__aeabi_memmove4),
-        api!(__aeabi_memmove),
-        api!(__aeabi_memset8),
-        api!(__aeabi_memset4),
-        api!(__aeabi_memset),
-        api!(__aeabi_memclr8),
-        api!(__aeabi_memclr4),
-        api!(__aeabi_memclr),
-        // libc
-        api!(memcmp, extern { fn memcmp(a: *const u8, b: *mut u8, size: usize); }),
-        // exceptions
-        api!(_Unwind_Resume = unwind::_Unwind_Resume),
-        api!(__artiq_personality = eh_artiq::artiq_personality),
-        api!(__artiq_raise = eh_artiq::raise),
-        api!(__artiq_reraise = eh_artiq::reraise),
-
-    ];
-    api.iter()
-       .find(|&&(exported, _)| exported.as_bytes() == required)
-       .map(|&(_, ptr)| ptr as u32)
-}
-
-
-#[no_mangle]
-pub fn main_core1() {
-    debug!("Core1 started");
-
-    enable_fpu();
-    debug!("FPU enabled on Core1");
-
-    let mut core1_tx = None;
-    while core1_tx.is_none() {
-        core1_tx = CHANNEL_1TO0.lock().take();
-    }
-    let mut core1_tx = core1_tx.unwrap();
-
-    let mut core1_rx = None;
-    while core1_rx.is_none() {
-        core1_rx = CHANNEL_0TO1.lock().take();
-    }
-    let mut core1_rx = core1_rx.unwrap();
-
-    let mut current_modinit: Option<u32> = None;
-    let mut current_typeinfo: Option<u32> = None;
-    let mut library_handle: Option<dyld::Library> = None;
-    loop {
-        let message = core1_rx.recv();
-        match *message {
-            Message::LoadRequest(data) => {
-                match dyld::load(&data, &resolve) {
-                    Ok(library) => {
-                        unsafe {
-                            KERNEL_LOAD_ADDR = library.image.as_ptr() as usize;
-                        }
-                        let bss_start = library.lookup(b"__bss_start");
-                        let end = library.lookup(b"_end");
-                        if let Some(bss_start) = bss_start {
-                            let end = end.unwrap();
-                            unsafe {
-                                ptr::write_bytes(bss_start as *mut u8, 0, (end - bss_start) as usize);
-                            }
-                        }
-                        let __modinit__ = library.lookup(b"__modinit__").unwrap();
-                        current_modinit = Some(__modinit__);
-                        current_typeinfo = library.lookup(b"typeinfo");
-                        debug!("kernel loaded");
-                        // Flush data cache entries for the image in DDR, including
-                        // Memory/Instruction Symchronization Barriers
-                        dcci_slice(library.image.data);
-
-                        core1_tx.send(Message::LoadCompleted);
-                        library_handle = Some(library);
-                    },
-                    Err(error) => {
-                        error!("failed to load shared library: {}", error);
-                        core1_tx.send(Message::LoadFailed);
-                    }
-                }
-            },
-            Message::StartRequest => {
-                info!("kernel starting");
-                if let Some(__modinit__) = current_modinit {
-                    unsafe {
-                        KERNEL_CHANNEL_0TO1 = mem::transmute(&mut core1_rx);
-                        KERNEL_CHANNEL_1TO0 = mem::transmute(&mut core1_tx);
-                        (mem::transmute::<u32, fn()>(__modinit__))();
-                        if let Some(typeinfo) = current_typeinfo {
-                            attribute_writeback(typeinfo as *const ());
-                        }
-                        KERNEL_CHANNEL_0TO1 = ptr::null_mut();
-                        KERNEL_CHANNEL_1TO0 = ptr::null_mut();
-                    }
-                }
-                library_handle = None;
-                info!("kernel finished");
-                core1_tx.send(Message::KernelFinished);
-            }
-            _ => error!("Core1 received unexpected message: {:?}", message),
-        }
-    }
-}

src/runtime/src/kernel/api.rs

@@ -0,0 +1,131 @@
+use crate::eh_artiq;
+use crate::rtio;
+use super::rpc::{rpc_send, rpc_send_async, rpc_recv};
+
+macro_rules! api {
+    ($i:ident) => ({
+        extern { static $i: u8; }
+        unsafe { api!($i = &$i as *const _) }
+    });
+    ($i:ident, $d:item) => ({
+        $d
+        api!($i = $i)
+    });
+    ($i:ident = $e:expr) => {
+        (stringify!($i), $e as *const ())
+    }
+}
+
+pub fn resolve(required: &[u8]) -> Option<u32> {
+    let api = &[
+        // timing
+        api!(now_mu = rtio::now_mu),
+        api!(at_mu = rtio::at_mu),
+        api!(delay_mu = rtio::delay_mu),
+
+        // rpc
+        api!(rpc_send = rpc_send),
+        api!(rpc_send_async = rpc_send_async),
+        api!(rpc_recv = rpc_recv),
+
+        // rtio
+        api!(rtio_init = rtio::init),
+        api!(rtio_get_destination_status = rtio::get_destination_status),
+        api!(rtio_get_counter = rtio::get_counter),
+        api!(rtio_output = rtio::output),
+        api!(rtio_output_wide = rtio::output_wide),
+        api!(rtio_input_timestamp = rtio::input_timestamp),
+        api!(rtio_input_data = rtio::input_data),
+        api!(rtio_input_timestamped_data = rtio::input_timestamped_data),
+
+        // Double-precision floating-point arithmetic helper functions
+        // RTABI chapter 4.1.2, Table 2
+        api!(__aeabi_dadd),
+        api!(__aeabi_ddiv),
+        api!(__aeabi_dmul),
+        api!(__aeabi_dsub),
+        // Double-precision floating-point comparison helper functions
+        // RTABI chapter 4.1.2, Table 3
+        api!(__aeabi_dcmpeq),
+        api!(__aeabi_dcmpeq),
+        api!(__aeabi_dcmplt),
+        api!(__aeabi_dcmple),
+        api!(__aeabi_dcmpge),
+        api!(__aeabi_dcmpgt),
+        api!(__aeabi_dcmpun),
+        // Single-precision floating-point arithmetic helper functions
+        // RTABI chapter 4.1.2, Table 4
+        api!(__aeabi_fadd),
+        api!(__aeabi_fdiv),
+        api!(__aeabi_fmul),
+        api!(__aeabi_fsub),
+        // Single-precision floating-point comparison helper functions
+        // RTABI chapter 4.1.2, Table 5
+        api!(__aeabi_fcmpeq),
+        api!(__aeabi_fcmpeq),
+        api!(__aeabi_fcmplt),
+        api!(__aeabi_fcmple),
+        api!(__aeabi_fcmpge),
+        api!(__aeabi_fcmpgt),
+        api!(__aeabi_fcmpun),
+        // Floating-point to integer conversions.
+        // RTABI chapter 4.1.2, Table 6
+        api!(__aeabi_d2iz),
+        api!(__aeabi_d2uiz),
+        api!(__aeabi_d2lz),
+        api!(__aeabi_d2ulz),
+        api!(__aeabi_f2iz),
+        api!(__aeabi_f2uiz),
+        api!(__aeabi_f2lz),
+        api!(__aeabi_f2ulz),
+        // Conversions between floating types.
+        // RTABI chapter 4.1.2, Table 7
+        api!(__aeabi_f2d),
+        // Integer to floating-point conversions.
+        // RTABI chapter 4.1.2, Table 8
+        api!(__aeabi_i2d),
+        api!(__aeabi_ui2d),
+        api!(__aeabi_l2d),
+        api!(__aeabi_ul2d),
+        api!(__aeabi_i2f),
+        api!(__aeabi_ui2f),
+        api!(__aeabi_l2f),
+        api!(__aeabi_ul2f),
+        // Long long helper functions
+        // RTABI chapter 4.2, Table 9
+        api!(__aeabi_lmul),
+        api!(__aeabi_llsl),
+        api!(__aeabi_llsr),
+        api!(__aeabi_lasr),
+        // Integer division functions
+        // RTABI chapter 4.3.1
+        api!(__aeabi_idiv),
+        api!(__aeabi_ldivmod),
+        api!(__aeabi_uidiv),
+        api!(__aeabi_uldivmod),
+        // 4.3.4 Memory copying, clearing, and setting
+        api!(__aeabi_memcpy8),
+        api!(__aeabi_memcpy4),
+        api!(__aeabi_memcpy),
+        api!(__aeabi_memmove8),
+        api!(__aeabi_memmove4),
+        api!(__aeabi_memmove),
+        api!(__aeabi_memset8),
+        api!(__aeabi_memset4),
+        api!(__aeabi_memset),
+        api!(__aeabi_memclr8),
+        api!(__aeabi_memclr4),
+        api!(__aeabi_memclr),
+        // libc
+        api!(memcmp, extern { fn memcmp(a: *const u8, b: *mut u8, size: usize); }),
+        // exceptions
+        api!(_Unwind_Resume = unwind::_Unwind_Resume),
+        api!(__artiq_personality = eh_artiq::artiq_personality),
+        api!(__artiq_raise = eh_artiq::raise),
+        api!(__artiq_reraise = eh_artiq::reraise),
+
+    ];
+    api.iter()
+       .find(|&&(exported, _)| exported.as_bytes() == required)
+       .map(|&(_, ptr)| ptr as u32)
+}

src/runtime/src/kernel/control.rs

@@ -0,0 +1,41 @@
+use libcortex_a9::sync_channel::{self, sync_channel};
+use libsupport_zynq::boot::Core1;
+
+use super::{CHANNEL_0TO1, CHANNEL_1TO0, Message};
+
+pub struct Control {
+    core1: Core1,
+    pub tx: sync_channel::Sender<Message>,
+    pub rx: sync_channel::Receiver<Message>,
+}
+
+impl Control {
+    pub fn start() -> Self {
+        let core1 = Core1::start(true);
+
+        let (core0_tx, core1_rx) = sync_channel(4);
+        let (core1_tx, core0_rx) = sync_channel(4);
+        *CHANNEL_0TO1.lock() = Some(core1_rx);
+        *CHANNEL_1TO0.lock() = Some(core1_tx);
+
+        Control {
+            core1,
+            tx: core0_tx,
+            rx: core0_rx,
+        }
+    }
+
+    pub fn restart(&mut self) {
+        *CHANNEL_0TO1.lock() = None;
+        *CHANNEL_1TO0.lock() = None;
+
+        self.core1.restart();
+
+        let (core0_tx, core1_rx) = sync_channel(4);
+        let (core1_tx, core0_rx) = sync_channel(4);
+        *CHANNEL_0TO1.lock() = Some(core1_rx);
+        *CHANNEL_1TO0.lock() = Some(core1_tx);
+        self.tx = core0_tx;
+        self.rx = core0_rx;
+    }
+}

src/runtime/src/kernel/core1.rs

@@ -0,0 +1,183 @@
+//! Kernel prologue/epilogue that runs on the 2nd CPU core
+
+use core::{mem, ptr};
+use alloc::borrow::ToOwned;
+use log::{debug, info, error};
+use cslice::CSlice;
+
+use libcortex_a9::{enable_fpu, cache::dcci_slice, sync_channel};
+use dyld::{self, Library};
+use crate::eh_artiq;
+use super::{
+    api::resolve,
+    rpc::rpc_send_async,
+    CHANNEL_0TO1, CHANNEL_1TO0,
+    KERNEL_CHANNEL_0TO1, KERNEL_CHANNEL_1TO0,
+    Message,
+};
+
+/// will contain the kernel image address on the heap
+static mut KERNEL_LOAD_ADDR: usize = 0;
+
+unsafe fn attribute_writeback(typeinfo: *const ()) {
+    struct Attr {
+        offset: usize,
+        tag:    CSlice<'static, u8>,
+        name:   CSlice<'static, u8>
+    }
+
+    struct Type {
+        attributes: *const *const Attr,
+        objects:    *const *const ()
+    }
+
+    let mut tys = typeinfo as *const *const Type;
+    while !(*tys).is_null() {
+        let ty = *tys;
+        tys = tys.offset(1);
+
+        let mut objects = (*ty).objects;
+        while !(*objects).is_null() {
+            let object = *objects;
+            objects = objects.offset(1);
+
+            let mut attributes = (*ty).attributes;
+            while !(*attributes).is_null() {
+                let attribute = *attributes;
+                attributes = attributes.offset(1);
+
+                if (*attribute).tag.len() > 0 {
+                    rpc_send_async(0, &(*attribute).tag, [
+                        &object as *const _ as *const (),
+                        &(*attribute).name as *const _ as *const (),
+                        (object as usize + (*attribute).offset) as *const ()
+                    ].as_ptr());
+                }
+            }
+        }
+    }
+}
+
+struct KernelImage {
+    library: Library,
+    __modinit__: u32,
+    typeinfo: Option<u32>,
+}
+
+impl KernelImage {
+    pub fn new(library: Library) -> Result<Self, dyld::Error> {
+        let __modinit__ = library.lookup(b"__modinit__")
+            .ok_or(dyld::Error::Lookup("__modinit__".to_owned()))?;
+        let typeinfo = library.lookup(b"typeinfo");
+
+        // clear .bss
+        let bss_start = library.lookup(b"__bss_start");
+        let end = library.lookup(b"_end");
+        if let Some(bss_start) = bss_start {
+            let end = end
+                .ok_or(dyld::Error::Lookup("_end".to_owned()))?;
+            unsafe {
+                ptr::write_bytes(bss_start as *mut u8, 0, (end - bss_start) as usize);
+            }
+        }
+
+        Ok(KernelImage {
+            library,
+            __modinit__,
+            typeinfo,
+        })
+    }
+
+    pub unsafe fn exec(&mut self) {
+        // Flush data cache entries for the image in DDR, including
+        // Memory/Instruction Symchronization Barriers
+        dcci_slice(self.library.image.data);
+
+        (mem::transmute::<u32, fn()>(self.__modinit__))();
+
+        if let Some(typeinfo) = self.typeinfo {
+            attribute_writeback(typeinfo as *const ());
+        }
+    }
+}
+
+#[no_mangle]
+pub fn main_core1() {
+    debug!("Core1 started");
+
+    enable_fpu();
+    debug!("FPU enabled on Core1");
+
+    let mut core1_tx = None;
+    while core1_tx.is_none() {
+        core1_tx = CHANNEL_1TO0.lock().take();
+    }
+    let mut core1_tx = core1_tx.unwrap();
+
+    let mut core1_rx = None;
+    while core1_rx.is_none() {
+        core1_rx = CHANNEL_0TO1.lock().take();
+    }
+    let mut core1_rx = core1_rx.unwrap();
+
+    // set on load, cleared on start
+    let mut loaded_kernel = None;
+    loop {
+        let message = core1_rx.recv();
+        match *message {
+            Message::LoadRequest(data) => {
+                let result = dyld::load(&data, &resolve)
+                    .and_then(KernelImage::new);
+                match result {
+                    Ok(kernel) => {
+                        unsafe {
+                            KERNEL_LOAD_ADDR = kernel.library.image.as_ptr() as usize;
+                        }
+                        loaded_kernel = Some(kernel);
+                        debug!("kernel loaded");
+                        core1_tx.send(Message::LoadCompleted);
+                    },
+                    Err(error) => {
+                        error!("failed to load shared library: {}", error);
+                        core1_tx.send(Message::LoadFailed);
+                    }
+                }
+            },
+            Message::StartRequest => {
+                info!("kernel starting");
+                if let Some(mut kernel) = loaded_kernel.take() {
+                    unsafe {
+                        KERNEL_CHANNEL_0TO1 = mem::transmute(&mut core1_rx);
+                        KERNEL_CHANNEL_1TO0 = mem::transmute(&mut core1_tx);
+                        kernel.exec();
+                        KERNEL_CHANNEL_0TO1 = ptr::null_mut();
+                        KERNEL_CHANNEL_1TO0 = ptr::null_mut();
+                    }
+                }
+                info!("kernel finished");
+                core1_tx.send(Message::KernelFinished);
+            }
+            _ => error!("Core1 received unexpected message: {:?}", message),
+        }
+    }
+}
+
+/// Called by eh_artiq
+pub fn terminate(exception: &'static eh_artiq::Exception<'static>, backtrace: &'static mut [usize]) -> ! {
+    let load_addr = unsafe {
+        KERNEL_LOAD_ADDR
+    };
+    let mut cursor = 0;
+    // The address in the backtrace is relocated, so we have to convert it back to the address in
+    // the original python script, and remove those Rust function backtrace.
+    for i in 0..backtrace.len() {
+        if backtrace[i] >= load_addr {
+            backtrace[cursor] = backtrace[i] - load_addr;
+            cursor += 1;
+        }
+    }
+
+    let core1_tx: &mut sync_channel::Sender<Message> = unsafe { mem::transmute(KERNEL_CHANNEL_1TO0) };
+    core1_tx.send(Message::KernelException(exception, &backtrace[..cursor]));
+    loop {}
+}

src/runtime/src/kernel/mod.rs

@@ -0,0 +1,41 @@
+use core::ptr;
+use alloc::{vec::Vec, sync::Arc, string::String};
+
+use libcortex_a9::{mutex::Mutex, sync_channel};
+use crate::eh_artiq;
+
+mod control;
+pub use control::Control;
+pub mod core1;
+mod api;
+mod rpc;
+
+#[derive(Debug)]
+pub struct RPCException {
+    pub name: String,
+    pub message: String,
+    pub param: [i64; 3],
+    pub file: String,
+    pub line: i32,
+    pub column: i32,
+    pub function: String
+}
+
+#[derive(Debug)]
+pub enum Message {
+    LoadRequest(Arc<Vec<u8>>),
+    LoadCompleted,
+    LoadFailed,
+    StartRequest,
+    KernelFinished,
+    KernelException(&'static eh_artiq::Exception<'static>, &'static [usize]),
+    RpcSend { is_async: bool, data: Arc<Vec<u8>> },
+    RpcRecvRequest(*mut ()),
+    RpcRecvReply(Result<usize, RPCException>),
+}
+
+static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<Message>>> = Mutex::new(None);
+static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<Message>>> = Mutex::new(None);
+
+static mut KERNEL_CHANNEL_0TO1: *mut () = ptr::null_mut();
+static mut KERNEL_CHANNEL_1TO0: *mut () = ptr::null_mut();

src/runtime/src/kernel/rpc.rs

@@ -0,0 +1,50 @@
+//! Kernel-side RPC API
+
+use core::mem;
+use alloc::{vec::Vec, sync::Arc};
+use cslice::{CSlice, AsCSlice};
+
+use libcortex_a9::sync_channel;
+use crate::eh_artiq;
+use crate::rpc::send_args;
+use super::{
+    KERNEL_CHANNEL_0TO1, KERNEL_CHANNEL_1TO0,
+    Message,
+};
+
+fn rpc_send_common(is_async: bool, service: u32, tag: &CSlice<u8>, data: *const *const ()) {
+    let core1_tx: &mut sync_channel::Sender<Message> = unsafe { mem::transmute(KERNEL_CHANNEL_1TO0) };
+    let mut buffer = Vec::<u8>::new();
+    send_args(&mut buffer, service, tag.as_ref(), data).expect("RPC encoding failed");
+    core1_tx.send(Message::RpcSend { is_async: is_async, data: Arc::new(buffer) });
+}
+
+pub extern fn rpc_send(service: u32, tag: &CSlice<u8>, data: *const *const ()) {
+    rpc_send_common(false, service, tag, data);
+}
+
+pub extern fn rpc_send_async(service: u32, tag: &CSlice<u8>, data: *const *const ()) {
+    rpc_send_common(true, service, tag, data);
+}
+
+pub extern fn rpc_recv(slot: *mut ()) -> usize {
+    let core1_rx: &mut sync_channel::Receiver<Message> = unsafe { mem::transmute(KERNEL_CHANNEL_0TO1) };
+    let core1_tx: &mut sync_channel::Sender<Message> = unsafe { mem::transmute(KERNEL_CHANNEL_1TO0) };
+    core1_tx.send(Message::RpcRecvRequest(slot));
+    let reply = core1_rx.recv();
+    match *reply {
+        Message::RpcRecvReply(Ok(alloc_size)) => alloc_size,
+        Message::RpcRecvReply(Err(exception)) => unsafe {
+            eh_artiq::raise(&eh_artiq::Exception {
+                name:     exception.name.as_bytes().as_c_slice(),
+                file:     exception.file.as_bytes().as_c_slice(),
+                line:     exception.line as u32,
+                column:   exception.column as u32,
+                function: exception.function.as_bytes().as_c_slice(),
+                message:  exception.message.as_bytes().as_c_slice(),
+                param:    exception.param
+            })
+        },
+        _ => panic!("received unexpected reply to RpcRecvRequest: {:?}", reply)
+    }
+}

src/runtime/src/main.rs

@@ -7,11 +7,13 @@
 extern crate alloc;
 
 use core::{cmp, str};
-use log::info;
+use log::{info, warn};
 
-use libboard_zynq::{timer::GlobalTimer, logger, devc, slcr};
+use libboard_zynq::{timer::GlobalTimer, time::Milliseconds, logger, devc, slcr};
 use libsupport_zynq::ram;
 use libregister::RegisterW;
+use nb::block;
+use embedded_hal::timer::CountDown;
 
 mod sd_reader;
 mod config;
@@ -29,28 +31,7 @@ mod load_pl;
 mod eh_artiq;
 mod panic;
 
-fn identifier_read(buf: &mut [u8]) -> &str {
+fn init_gateware() {
-    unsafe {
-        pl::csr::identifier::address_write(0);
-        let len = pl::csr::identifier::data_read();
-        let len = cmp::min(len, buf.len() as u8);
-        for i in 0..len {
-            pl::csr::identifier::address_write(1 + i);
-            buf[i as usize] = pl::csr::identifier::data_read();
-        }
-        str::from_utf8_unchecked(&buf[..len as usize])
-    }
-}
-
-#[no_mangle]
-pub fn main_core0() {
-    let timer = GlobalTimer::start();
-    let _ = logger::init();
-    log::set_max_level(log::LevelFilter::Debug);
-    info!("NAR3/Zynq7000 starting...");
-
-    ram::init_alloc_linker();
-
     // Set up PS->PL clocks
     slcr::RegisterBlock::unlocked(|slcr| {
         // As we are touching the mux, the clock may glitch, so reset the PL.
@@ -87,11 +68,83 @@ pub fn main_core0() {
             Err(e) => info!("Failure loading bitstream: {}", e),
         }
     }
-    info!("detected gateware: {}", identifier_read(&mut [0; 64]));
+}
+
+fn identifier_read(buf: &mut [u8]) -> &str {
+    unsafe {
+        pl::csr::identifier::address_write(0);
+        let len = pl::csr::identifier::data_read();
+        let len = cmp::min(len, buf.len() as u8);
+        for i in 0..len {
+            pl::csr::identifier::address_write(1 + i);
+            buf[i as usize] = pl::csr::identifier::data_read();
+        }
+        str::from_utf8_unchecked(&buf[..len as usize])
+    }
+}
+
+fn init_rtio(timer: GlobalTimer, cfg: &config::Config) {
+    let clock_sel =
+        if let Ok(rtioclk) = cfg.read_str("rtioclk") {
+            match rtioclk.as_ref() {
+                "internal" => {
+                    info!("using internal RTIO clock");
+                    0
+                },
+                "external" => {
+                    info!("using external RTIO clock");
+                    1
+                },
+                other => {
+                    warn!("RTIO clock specification '{}' not recognized", other);
+                    info!("using internal RTIO clock");
+                    0
+                },
+            }
+        } else {
+            info!("using internal RTIO clock (default)");
+            0
+        };
+
+    unsafe {
+        pl::csr::rtio_crg::pll_reset_write(1);
+        pl::csr::rtio_crg::clock_sel_write(clock_sel);
+        pl::csr::rtio_crg::pll_reset_write(0);
+    }
+    let mut countdown = timer.countdown();
+    countdown.start(Milliseconds(1));
+    block!(countdown.wait()).unwrap();
+    let locked = unsafe { pl::csr::rtio_crg::pll_locked_read() != 0 };
+    if !locked {
+        panic!("RTIO PLL failed to lock");
+    }
 
     unsafe {
         pl::csr::rtio_core::reset_phy_write(1);
     }
-
+}
-    comms::main(timer);
+
+#[no_mangle]
+pub fn main_core0() {
+    let timer = GlobalTimer::start();
+    let _ = logger::init();
+    log::set_max_level(log::LevelFilter::Debug);
+    info!("NAR3/Zynq7000 starting...");
+
+    ram::init_alloc_linker();
+
+    init_gateware();
+    info!("detected gateware: {}", identifier_read(&mut [0; 64]));
+
+    let cfg = match config::Config::new() {
+        Ok(cfg) => cfg,
+        Err(err) => {
+            warn!("config initialization failed: {}", err);
+            config::Config::new_dummy()
+        }
+    };
+
+    init_rtio(timer, &cfg);
+
+    comms::main(timer, &cfg);
 }

src/runtime/src/net_settings.rs

@@ -23,21 +23,19 @@ impl fmt::Display for NetAddresses {
     }
 }
 
-pub fn get_adresses() -> NetAddresses {
+pub fn get_adresses(cfg: &config::Config) -> NetAddresses {
     let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x52]);
     let mut ipv4_addr = IpAddress::v4(192, 168, 1, 52);
     let mut ipv6_addr = None;
 
-    if let Ok(cfg) = config::Config::new() {
+    if let Ok(Ok(addr)) = cfg.read_str("mac").map(|s| s.parse()) {
-        if let Ok(Ok(addr)) = cfg.read_str("mac").map(|s| s.parse()) {
+        hardware_addr = addr;
-            hardware_addr = addr;
+    }
-        }
+    if let Ok(Ok(addr)) = cfg.read_str("ip").map(|s| s.parse()) {
-        if let Ok(Ok(addr)) = cfg.read_str("ip").map(|s| s.parse()) {
+        ipv4_addr = addr;
-            ipv4_addr = addr;
+    }
-        }
+    if let Ok(Ok(addr)) = cfg.read_str("ip6").map(|s| s.parse()) {
-        if let Ok(Ok(addr)) = cfg.read_str("ip6").map(|s| s.parse()) {
+        ipv6_addr = Some(addr);
-            ipv6_addr = Some(addr);
-        }
     }
 
     let ipv6_ll_addr = IpAddress::v6(

src/zc706.py

@@ -3,15 +3,61 @@
 import argparse
 
 from migen import *
-
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.cdc import MultiReg
 from migen_axi.integration.soc_core import SoCCore
 from migen_axi.platforms import zc706
+from misoc.interconnect.csr import *
 from misoc.integration import cpu_interface
 
 from artiq.gateware import rtio, nist_clock, nist_qc2
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
 
 
+class RTIOCRG(Module, AutoCSR):
+    def __init__(self, platform, rtio_internal_clk):
+        self.clock_sel = CSRStorage()
+        self.pll_reset = CSRStorage(reset=1)
+        self.pll_locked = CSRStatus()
+        self.clock_domains.cd_rtio = ClockDomain()
+        self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
+
+        rtio_external_clk = Signal()
+        user_sma_clock = platform.request("user_sma_clock")
+        platform.add_period_constraint(user_sma_clock.p, 8.0)
+        self.specials += Instance("IBUFDS",
+                                  i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
+                                  o_O=rtio_external_clk)
+
+        pll_locked = Signal()
+        rtio_clk = Signal()
+        rtiox4_clk = Signal()
+        self.specials += [
+            Instance("PLLE2_ADV",
+                     p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
+
+                     p_REF_JITTER1=0.01,
+                     p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
+                     i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
+                     # Warning: CLKINSEL=0 means CLKIN2 is selected
+                     i_CLKINSEL=~self.clock_sel.storage,
+
+                     # VCO @ 1GHz when using 125MHz input
+                     p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
+                     i_CLKFBIN=self.cd_rtio.clk,
+                     i_RST=self.pll_reset.storage,
+
+                     o_CLKFBOUT=rtio_clk,
+
+                     p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
+                     o_CLKOUT0=rtiox4_clk),
+            Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
+            Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
+            AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
+            MultiReg(pll_locked, self.pll_locked.status)
+        ]
+
+
 class ZC706(SoCCore):
     def __init__(self):
         platform = zc706.Platform()
@@ -22,11 +68,13 @@ class ZC706(SoCCore):
 
         platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
         platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
-        self.clock_domains.cd_rtio = ClockDomain()
+
-        self.comb += [
+        self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
-            self.cd_rtio.clk.eq(self.ps7.cd_sys.clk),
+        self.csr_devices.append("rtio_crg")
-            self.cd_rtio.rst.eq(self.ps7.cd_sys.rst)
+        self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
-        ]
+        self.platform.add_false_path_constraints(
+            self.ps7.cd_sys.clk,
+            self.rtio_crg.cd_rtio.clk)
 
     def add_rtio(self, rtio_channels):
         self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
@@ -69,16 +117,16 @@ class NIST_CLOCK(ZC706):
         rtio_channels = []
         for i in range(16):
             if i % 4 == 3:
-                phy = ttl_simple.InOut(platform.request("ttl", i))
+                phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
                 self.submodules += phy
                 rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
             else:
-                phy = ttl_simple.Output(platform.request("ttl", i))
+                phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
                 self.submodules += phy
                 rtio_channels.append(rtio.Channel.from_phy(phy))
 
         for i in range(2):
-            phy = ttl_simple.InOut(platform.request("pmt", i))
+            phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i))
             self.submodules += phy
             rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
 
@@ -119,8 +167,7 @@ class NIST_QC2(ZC706):
 
         # All TTL channels are In+Out capable
         for i in range(40):
-            phy = ttl_simple.InOut(
+            phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
-                platform.request("ttl", i))
             self.submodules += phy
             rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))