forked from M-Labs/artiq-zynq
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No commits in common. "56e7cc822c4d094029e5bb87e7e5fc5fc29e6dc4" and "b388b529ada7897da9c7ea095918e5207cf23e6c" have entirely different histories.
56e7cc822c
...
b388b529ad
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@ -8,12 +8,11 @@ class DMAPulses(EnvExperiment):
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@kernel
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def record(self):
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with self.core_dma.record("pulse"):
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delay(200*ms)
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# all RTIO operations now go to the "pulse"
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with self.core_dma.record("pulses"):
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# all RTIO operations now go to the "pulses"
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# DMA buffer, instead of being executed immediately.
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self.led0.pulse(500*ms)
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self.led0.pulse(100*ns)
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delay(100*ns)
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@kernel
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def run(self):
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@ -21,6 +20,7 @@ class DMAPulses(EnvExperiment):
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self.record()
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# prefetch the address of the DMA buffer
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# for faster playback trigger
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pulse_handle = self.core_dma.get_handle("pulse")
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pulses_handle = self.core_dma.get_handle("pulses")
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self.core.break_realtime()
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self.core_dma.playback_handle(pulse_handle)
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self.core_dma.playback_handle(pulses_handle)
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@ -201,7 +201,7 @@ dependencies = [
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[[package]]
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name = "libasync"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#0aa75d3544a2092a0ba6ce689c3f025f22ec30e4"
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dependencies = [
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"embedded-hal",
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"libcortex_a9",
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@ -213,7 +213,7 @@ dependencies = [
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[[package]]
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name = "libboard_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#0aa75d3544a2092a0ba6ce689c3f025f22ec30e4"
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dependencies = [
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"bit_field",
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"embedded-hal",
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@ -237,7 +237,7 @@ dependencies = [
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[[package]]
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name = "libcortex_a9"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#0aa75d3544a2092a0ba6ce689c3f025f22ec30e4"
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dependencies = [
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"bit_field",
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"libregister",
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@ -252,7 +252,7 @@ checksum = "c7d73b3f436185384286bd8098d17ec07c9a7d2388a6599f824d8502b529702a"
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[[package]]
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name = "libregister"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#0aa75d3544a2092a0ba6ce689c3f025f22ec30e4"
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dependencies = [
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"bit_field",
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"vcell",
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@ -262,7 +262,7 @@ dependencies = [
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[[package]]
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name = "libsupport_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#0aa75d3544a2092a0ba6ce689c3f025f22ec30e4"
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dependencies = [
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"compiler_builtins",
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"libboard_zynq",
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@ -26,7 +26,7 @@ log_buffer = { version = "1.2" }
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libm = { version = "0.2", features = ["unstable"] }
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libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libsupport_zynq = { default-features = false, features = ["alloc_core"], git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libsupport_zynq = { default-features = false, git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libasync = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libregister = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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@ -48,12 +48,9 @@ SECTIONS
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.heap (NOLOAD) : ALIGN(8)
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{
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__heap0_start = .;
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. += 0x800000;
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__heap0_end = .;
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__heap1_start = .;
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. += 0x800000;
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__heap1_end = .;
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__heap_start = .;
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. += 0x1000000;
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__heap_end = .;
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} > SDRAM
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.stack1 (NOLOAD) : ALIGN(8)
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@ -2,6 +2,7 @@ use core::fmt;
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use core::cell::RefCell;
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use core::str::Utf8Error;
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use alloc::rc::Rc;
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use alloc::sync::Arc;
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use alloc::{vec, vec::Vec, string::String};
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use log::{info, warn, error};
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@ -18,8 +19,6 @@ use libboard_zynq::{
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},
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timer::GlobalTimer,
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};
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use libcortex_a9::sync_channel;
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use futures::{select_biased, future::FutureExt};
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use libasync::{smoltcp::{Sockets, TcpStream}, task};
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use crate::config;
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@ -127,7 +126,7 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
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control.borrow_mut().tx.async_send(kernel::Message::StartRequest).await;
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loop {
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let reply = control.borrow_mut().rx.async_recv().await;
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match reply {
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match *reply {
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kernel::Message::RpcSend { is_async, data } => {
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if stream.is_none() {
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error!("Unexpected RPC from startup/idle kernel!");
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@ -142,7 +141,7 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
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match host_request {
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Request::RPCReply => {
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let tag = read_bytes(stream, 512).await?;
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let slot = match control.borrow_mut().rx.async_recv().await {
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let slot = match *control.borrow_mut().rx.async_recv().await {
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kernel::Message::RpcRecvRequest(slot) => slot,
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other => panic!("expected root value slot from core1, not {:?}", other),
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};
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@ -156,7 +155,7 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
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} else {
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let mut control = control.borrow_mut();
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control.tx.async_send(kernel::Message::RpcRecvReply(Ok(size))).await;
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match control.rx.async_recv().await {
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match *control.rx.async_recv().await {
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kernel::Message::RpcRecvRequest(slot) => slot,
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other => panic!("expected nested value slot from kernel CPU, not {:?}", other),
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}
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@ -167,7 +166,7 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
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},
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Request::RPCException => {
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let mut control = control.borrow_mut();
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match control.rx.async_recv().await {
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match *control.rx.async_recv().await {
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kernel::Message::RpcRecvRequest(_) => (),
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other => panic!("expected (ignored) root value slot from kernel CPU, not {:?}", other),
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}
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@ -232,12 +231,11 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
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}
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async fn load_kernel(buffer: &Vec<u8>, control: &Rc<RefCell<kernel::Control>>, stream: Option<&TcpStream>) -> Result<()> {
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async fn load_kernel(buffer: Vec<u8>, control: &Rc<RefCell<kernel::Control>>, stream: Option<&TcpStream>) -> Result<()> {
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let mut control = control.borrow_mut();
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control.restart();
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control.tx.async_send(kernel::Message::LoadRequest(buffer.to_vec())).await;
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control.tx.async_send(kernel::Message::LoadRequest(Arc::new(buffer))).await;
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let reply = control.rx.async_recv().await;
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match reply {
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match *reply {
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kernel::Message::LoadCompleted => {
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if let Some(stream) = stream {
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write_header(stream, Reply::LoadCompleted).await?;
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@ -281,7 +279,7 @@ async fn handle_connection(stream: &TcpStream, control: Rc<RefCell<kernel::Contr
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},
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Request::LoadKernel => {
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let buffer = read_bytes(stream, 1024*1024).await?;
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load_kernel(&buffer, &control, Some(stream)).await?;
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load_kernel(buffer, &control, Some(stream)).await?;
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},
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Request::RunKernel => {
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handle_run_kernel(Some(stream), &control).await?;
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@ -340,10 +338,9 @@ pub fn main(timer: GlobalTimer, cfg: &config::Config) {
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moninj::start(timer);
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let control: Rc<RefCell<kernel::Control>> = Rc::new(RefCell::new(kernel::Control::start()));
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let idle_kernel = Rc::new(cfg.read("idle").ok());
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if let Ok(buffer) = cfg.read("startup") {
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info!("Loading startup kernel...");
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if let Ok(()) = task::block_on(load_kernel(&buffer, &control, None)) {
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if let Ok(()) = task::block_on(load_kernel(buffer, &control, None)) {
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info!("Starting startup kernel...");
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let _ = task::block_on(handle_run_kernel(None, &control));
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info!("Startup kernel finished!");
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@ -353,53 +350,14 @@ pub fn main(timer: GlobalTimer, cfg: &config::Config) {
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}
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task::spawn(async move {
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let (tx, rx) = sync_channel!(u32, 1);
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let tx = RefCell::new(tx);
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let rx = Rc::new(RefCell::new(rx));
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let has_connection = Rc::new(RefCell::new(false));
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loop {
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let stream = TcpStream::accept(1381, 2048, 2048).await.unwrap();
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let has_connection = has_connection.clone();
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if *has_connection.borrow() {
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let mut tx = tx.borrow_mut();
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tx.async_send(42).await;
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// the second send is used to block until another connection received the abort
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// request.
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tx.async_send(42).await;
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}
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*has_connection.borrow_mut() = true;
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let control = control.clone();
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let idle_kernel = idle_kernel.clone();
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let _ = rx.borrow_mut().try_recv();
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let new_rx = rx.clone();
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task::spawn(async move {
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let mut new_rx = new_rx.borrow_mut();
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select_biased! {
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_ = (async {
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let _ = handle_connection(&stream, control.clone())
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.await
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.map_err(|e| warn!("connection terminated: {}", e));
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if let Some(buffer) = &*idle_kernel {
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info!("Loading idle kernel");
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let _ = load_kernel(&buffer, &control, None)
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.await.map_err(|e| warn!("error loading idle kernel"));
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info!("Running idle kernel");
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let _ = handle_run_kernel(None, &control)
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.await.map_err(|e| warn!("error running idle kernel"));
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info!("Idle kernel terminated");
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}
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}).fuse() => (),
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_ = new_rx.async_recv().fuse() => ()
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}
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*has_connection.borrow_mut() = false;
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// it is possible that when `handle_connection` is terminating,
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// another connection sent an abort request and get blocked,
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// so we try_recv here to unblock in that case.
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let _ = new_rx.try_recv();
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core::mem::drop(new_rx);
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task::spawn(async {
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info!("received connection");
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let _ = handle_connection(&stream, control)
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.await
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.map_err(|e| warn!("connection terminated: {}", e));
|
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let _ = stream.flush().await;
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let _ = stream.abort().await;
|
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});
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|
|
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@ -1,46 +0,0 @@
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use libboard_zynq::{gic, mpcore, println, stdio};
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use libcortex_a9::{
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asm,
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regs::{MPIDR, SP},
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};
|
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use libregister::{RegisterR, RegisterW};
|
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use core::sync::atomic::{AtomicBool, Ordering};
|
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|
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extern "C" {
|
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static mut __stack1_start: u32;
|
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fn main_core1() -> !;
|
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}
|
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|
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static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
|
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|
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#[link_section = ".text.boot"]
|
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#[no_mangle]
|
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#[naked]
|
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pub unsafe extern "C" fn IRQ() {
|
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if MPIDR.read().cpu_id() == 1 {
|
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let mpcore = mpcore::RegisterBlock::new();
|
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let mut gic = gic::InterruptController::new(mpcore);
|
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let id = gic.get_interrupt_id();
|
||||
if id.0 == 0 {
|
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gic.end_interrupt(id);
|
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asm::exit_irq();
|
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SP.write(&mut __stack1_start as *mut _ as u32);
|
||||
asm::enable_irq();
|
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CORE1_RESTART.store(false, Ordering::Relaxed);
|
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asm::sev();
|
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main_core1();
|
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}
|
||||
}
|
||||
stdio::drop_uart();
|
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println!("IRQ");
|
||||
loop {}
|
||||
}
|
||||
|
||||
pub fn restart_core1() {
|
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let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new());
|
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CORE1_RESTART.store(true, Ordering::Relaxed);
|
||||
interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
|
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while CORE1_RESTART.load(Ordering::Relaxed) {
|
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asm::wfe();
|
||||
}
|
||||
}
|
|
@ -3,6 +3,7 @@ use libcortex_a9::mutex::Mutex;
|
|||
use cslice::{CSlice, AsCSlice};
|
||||
use core::mem::transmute;
|
||||
use core::str;
|
||||
use log::debug;
|
||||
|
||||
use crate::artiq_raise;
|
||||
|
||||
|
|
|
@ -1,49 +1,25 @@
|
|||
use libcortex_a9::sync_channel::{Sender, Receiver};
|
||||
use libcortex_a9::sync_channel::{self, sync_channel};
|
||||
use libsupport_zynq::boot::Core1;
|
||||
|
||||
use super::{CHANNEL_0TO1, CHANNEL_1TO0, Message};
|
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use crate::irq::restart_core1;
|
||||
|
||||
use core::mem::{forget, replace};
|
||||
|
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pub struct Control {
|
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pub tx: Sender<'static, Message>,
|
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pub rx: Receiver<'static, Message>,
|
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}
|
||||
|
||||
fn get_channels() -> (Sender<'static, Message>, Receiver<'static, Message>) {
|
||||
let mut core0_tx = None;
|
||||
while core0_tx.is_none() {
|
||||
core0_tx = CHANNEL_0TO1.lock().take();
|
||||
}
|
||||
let core0_tx = core0_tx.unwrap();
|
||||
|
||||
let mut core0_rx = None;
|
||||
while core0_rx.is_none() {
|
||||
core0_rx = CHANNEL_1TO0.lock().take();
|
||||
}
|
||||
let core0_rx = core0_rx.unwrap();
|
||||
|
||||
(core0_tx, core0_rx)
|
||||
pub tx: sync_channel::Sender<Message>,
|
||||
pub rx: sync_channel::Receiver<Message>,
|
||||
}
|
||||
|
||||
impl Control {
|
||||
pub fn start() -> Self {
|
||||
Core1::start(true);
|
||||
let (core0_tx, core0_rx) = get_channels();
|
||||
|
||||
let (core0_tx, core1_rx) = sync_channel(4);
|
||||
let (core1_tx, core0_rx) = sync_channel(4);
|
||||
*CHANNEL_0TO1.lock() = Some(core1_rx);
|
||||
*CHANNEL_1TO0.lock() = Some(core1_tx);
|
||||
|
||||
Control {
|
||||
tx: core0_tx,
|
||||
rx: core0_rx,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn restart(&mut self) {
|
||||
restart_core1();
|
||||
let (core0_tx, core0_rx) = get_channels();
|
||||
// dangling pointer here, so we forget it
|
||||
forget(replace(&mut self.tx, core0_tx));
|
||||
forget(replace(&mut self.rx, core0_rx));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -9,10 +9,7 @@ use libcortex_a9::{
|
|||
enable_fpu,
|
||||
cache::{dcci_slice, iciallu, bpiall},
|
||||
asm::{dsb, isb},
|
||||
sync_channel,
|
||||
};
|
||||
use libboard_zynq::{mpcore, gic};
|
||||
use libsupport_zynq::ram;
|
||||
use dyld::{self, Library};
|
||||
use crate::eh_artiq;
|
||||
use super::{
|
||||
|
@ -141,23 +138,23 @@ pub fn main_core1() {
|
|||
enable_fpu();
|
||||
debug!("FPU enabled on Core1");
|
||||
|
||||
ram::init_alloc_core1();
|
||||
gic::InterruptController::new(mpcore::RegisterBlock::new()).enable_interrupts();
|
||||
|
||||
let (mut core0_tx, mut core1_rx) = sync_channel!(Message, 4);
|
||||
let (mut core1_tx, core0_rx) = sync_channel!(Message, 4);
|
||||
unsafe {
|
||||
core0_tx.reset();
|
||||
core1_tx.reset();
|
||||
let mut core1_tx = None;
|
||||
while core1_tx.is_none() {
|
||||
core1_tx = CHANNEL_1TO0.lock().take();
|
||||
}
|
||||
*CHANNEL_0TO1.lock() = Some(core0_tx);
|
||||
*CHANNEL_1TO0.lock() = Some(core0_rx);
|
||||
let mut core1_tx = core1_tx.unwrap();
|
||||
|
||||
let mut core1_rx = None;
|
||||
while core1_rx.is_none() {
|
||||
core1_rx = CHANNEL_0TO1.lock().take();
|
||||
}
|
||||
let mut core1_rx = core1_rx.unwrap();
|
||||
|
||||
// set on load, cleared on start
|
||||
let mut loaded_kernel = None;
|
||||
loop {
|
||||
let message = core1_rx.recv();
|
||||
match message {
|
||||
match *message {
|
||||
Message::LoadRequest(data) => {
|
||||
let result = dyld::load(&data, &resolve)
|
||||
.and_then(KernelImage::new);
|
||||
|
@ -216,6 +213,8 @@ pub fn terminate(exception: &'static eh_artiq::Exception<'static>, backtrace: &'
|
|||
let mut core1_tx = KERNEL_CHANNEL_1TO0.lock();
|
||||
core1_tx.as_mut().unwrap().send(Message::KernelException(exception, &backtrace[..cursor]));
|
||||
}
|
||||
// TODO: remove after implementing graceful kernel termination.
|
||||
error!("Core1 uncaught exception");
|
||||
loop {}
|
||||
}
|
||||
|
||||
|
|
|
@ -258,7 +258,7 @@ pub extern fn dma_retrieve(name: CSlice<u8>) -> DmaTrace {
|
|||
pub extern fn dma_playback(timestamp: i64, ptr: i32) {
|
||||
assert!(ptr % ALIGNMENT as i32 == 0);
|
||||
|
||||
debug!("DMA playback started");
|
||||
debug!("DMA Playback");
|
||||
unsafe {
|
||||
csr::rtio_dma::base_address_write(ptr as u32);
|
||||
csr::rtio_dma::time_offset_write(timestamp as u64);
|
||||
|
@ -268,8 +268,6 @@ pub extern fn dma_playback(timestamp: i64, ptr: i32) {
|
|||
while csr::rtio_dma::enable_read() != 0 {}
|
||||
csr::cri_con::selected_write(0);
|
||||
|
||||
debug!("DMA playback finished");
|
||||
|
||||
let error = csr::rtio_dma::error_read();
|
||||
if error != 0 {
|
||||
let timestamp = csr::rtio_dma::error_timestamp_read();
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
use core::ptr;
|
||||
use alloc::{vec::Vec, string::String};
|
||||
use alloc::{vec::Vec, sync::Arc, string::String};
|
||||
|
||||
use libcortex_a9::{mutex::Mutex, sync_channel};
|
||||
use crate::eh_artiq;
|
||||
|
@ -12,7 +12,7 @@ mod rpc;
|
|||
mod dma;
|
||||
mod cache;
|
||||
|
||||
#[derive(Debug, Clone)]
|
||||
#[derive(Debug)]
|
||||
pub struct RPCException {
|
||||
pub name: String,
|
||||
pub message: String,
|
||||
|
@ -23,24 +23,24 @@ pub struct RPCException {
|
|||
pub function: String
|
||||
}
|
||||
|
||||
#[derive(Debug, Clone)]
|
||||
#[derive(Debug)]
|
||||
pub enum Message {
|
||||
LoadRequest(Vec<u8>),
|
||||
LoadRequest(Arc<Vec<u8>>),
|
||||
LoadCompleted,
|
||||
LoadFailed,
|
||||
StartRequest,
|
||||
KernelFinished,
|
||||
KernelException(&'static eh_artiq::Exception<'static>, &'static [usize]),
|
||||
RpcSend { is_async: bool, data: Vec<u8> },
|
||||
RpcSend { is_async: bool, data: Arc<Vec<u8>> },
|
||||
RpcRecvRequest(*mut ()),
|
||||
RpcRecvReply(Result<usize, RPCException>),
|
||||
}
|
||||
|
||||
static CHANNEL_0TO1: Mutex<Option<sync_channel::Sender<'static, Message>>> = Mutex::new(None);
|
||||
static CHANNEL_1TO0: Mutex<Option<sync_channel::Receiver<'static, Message>>> = Mutex::new(None);
|
||||
static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<Message>>> = Mutex::new(None);
|
||||
static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<Message>>> = Mutex::new(None);
|
||||
|
||||
static KERNEL_CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<'static, Message>>> = Mutex::new(None);
|
||||
static KERNEL_CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<'static, Message>>> = Mutex::new(None);
|
||||
static KERNEL_CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<Message>>> = Mutex::new(None);
|
||||
static KERNEL_CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<Message>>> = Mutex::new(None);
|
||||
|
||||
static mut KERNEL_IMAGE: *const core1::KernelImage = ptr::null();
|
||||
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
//! Kernel-side RPC API
|
||||
|
||||
use alloc::vec::Vec;
|
||||
use alloc::{vec::Vec, sync::Arc};
|
||||
use cslice::{CSlice, AsCSlice};
|
||||
|
||||
use crate::eh_artiq;
|
||||
|
@ -14,7 +14,7 @@ fn rpc_send_common(is_async: bool, service: u32, tag: &CSlice<u8>, data: *const
|
|||
let mut core1_tx = KERNEL_CHANNEL_1TO0.lock();
|
||||
let mut buffer = Vec::<u8>::new();
|
||||
send_args(&mut buffer, service, tag.as_ref(), data).expect("RPC encoding failed");
|
||||
core1_tx.as_mut().unwrap().send(Message::RpcSend { is_async, data: buffer });
|
||||
core1_tx.as_mut().unwrap().send(Message::RpcSend { is_async, data: Arc::new(buffer) });
|
||||
}
|
||||
|
||||
pub extern fn rpc_send(service: u32, tag: &CSlice<u8>, data: *const *const ()) {
|
||||
|
@ -32,7 +32,7 @@ pub extern fn rpc_recv(slot: *mut ()) -> usize {
|
|||
core1_tx.as_mut().unwrap().send(Message::RpcRecvRequest(slot));
|
||||
core1_rx.as_mut().unwrap().recv()
|
||||
};
|
||||
match reply {
|
||||
match *reply {
|
||||
Message::RpcRecvReply(Ok(alloc_size)) => alloc_size,
|
||||
Message::RpcRecvReply(Err(exception)) => unsafe {
|
||||
eh_artiq::raise(&eh_artiq::Exception {
|
||||
|
|
|
@ -6,15 +6,13 @@
|
|||
#![feature(c_variadic)]
|
||||
#![feature(const_btree_new)]
|
||||
#![feature(ptr_offset_from)]
|
||||
#![feature(const_in_array_repeat_expressions)]
|
||||
#![feature(naked_functions)]
|
||||
|
||||
extern crate alloc;
|
||||
|
||||
use core::{cmp, str};
|
||||
use log::{info, warn, error};
|
||||
|
||||
use libboard_zynq::{timer::GlobalTimer, devc, slcr, mpcore, gic};
|
||||
use libboard_zynq::{timer::GlobalTimer, devc, slcr};
|
||||
use libasync::{task, block_async};
|
||||
use libsupport_zynq::ram;
|
||||
use libregister::RegisterW;
|
||||
|
@ -40,7 +38,6 @@ mod panic;
|
|||
mod logger;
|
||||
mod mgmt;
|
||||
mod analyzer;
|
||||
mod irq;
|
||||
|
||||
fn init_gateware() {
|
||||
// Set up PS->PL clocks
|
||||
|
@ -186,8 +183,7 @@ pub fn main_core0() {
|
|||
|
||||
info!("NAR3/Zynq7000 starting...");
|
||||
|
||||
ram::init_alloc_core0();
|
||||
gic::InterruptController::new(mpcore::RegisterBlock::new()).enable_interrupts();
|
||||
ram::init_alloc_linker();
|
||||
|
||||
init_gateware();
|
||||
info!("detected gateware: {}", identifier_read(&mut [0; 64]));
|
||||
|
|
|
@ -34,12 +34,6 @@ SECTIONS
|
|||
__bss_end = .;
|
||||
} > OCM3
|
||||
|
||||
.heap (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
__heap0_start = .;
|
||||
__heap0_end = .;
|
||||
} > OCM3
|
||||
|
||||
.stack1 (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
__stack1_end = .;
|
||||
|
|
Loading…
Reference in New Issue