From f1fd55dee5b45bf478f27bedff5067c5c058ecee Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 29 May 2021 17:13:41 +0800 Subject: [PATCH] kasli-soc: work around I2C breakage (#130) --- src/gateware/kasli_soc.py | 11 +---------- src/runtime/src/main.rs | 4 ++-- 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 6d6897a9..3169eaed 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -27,15 +27,6 @@ class RTIOCRG(Module, AutoCSR): self.clock_domains.cd_rtio = ClockDomain() self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True) - clk_synth = platform.request("cdr_clk_clean_fabric") - clk_synth_se = Signal() - platform.add_period_constraint(clk_synth.p, 8.0) - self.specials += [ - Instance("IBUFGDS", - p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", - i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se), - ] - pll_locked = Signal() rtio_clk = Signal() rtiox4_clk = Signal() @@ -46,7 +37,7 @@ class RTIOCRG(Module, AutoCSR): p_BANDWIDTH="HIGH", p_REF_JITTER1=0.001, p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0, - i_CLKIN2=clk_synth_se, + i_CLKIN2=ClockSignal(), # Warning: CLKINSEL=0 means CLKIN2 is selected i_CLKINSEL=0, diff --git a/src/runtime/src/main.rs b/src/runtime/src/main.rs index 57a2503c..f4b41a19 100644 --- a/src/runtime/src/main.rs +++ b/src/runtime/src/main.rs @@ -199,9 +199,9 @@ pub fn main_core0() { info!("detected gateware: {}", identifier_read(&mut [0; 64])); i2c::init(); - #[cfg(feature = "target_kasli_soc")] + /*#[cfg(feature = "target_kasli_soc")] si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() }, - &SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324"); + &SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");*/ let cfg = match Config::new() { Ok(cfg) => cfg,