enabled L2 cache and optimized ethernet

libconfig
pca006132 2 years ago
parent 2faf74f708
commit e592efb2b8
  1. 3
      shell.nix
  2. 17
      src/Cargo.lock
  3. 10
      src/Cargo.toml
  4. 12
      src/runtime/src/comms.rs
  5. 14
      src/runtime/src/proto_async.rs
  6. 2
      src/szl/link.x
  7. 13
      src/szl/src/main.rs
  8. 26
      xbuild.nix
  9. 13
      xbuild.patch

@ -5,6 +5,7 @@ let
rustPlatform = (import ./rustPlatform.nix { inherit pkgs; });
artiqpkgs = import "${artiq-fast}/default.nix" { inherit pkgs; };
vivado = import "${artiq-fast}/vivado.nix" { inherit pkgs; };
xbuild = (import ./xbuild.nix );
in
pkgs.stdenv.mkDerivation {
name = "artiq-zynq-env";
@ -15,7 +16,7 @@ in
pkgs.llvmPackages_9.llvm
pkgs.llvmPackages_9.clang-unwrapped
pkgs.cacert
pkgs.cargo-xbuild
xbuild
pkgs.openocd
pkgs.openssh pkgs.rsync

17
src/Cargo.lock generated

@ -50,8 +50,10 @@ checksum = "4785bdd1c96b2a846b2bd7cc02e86b6b3dbf14e7e53446c4f54c92a361040822"
[[package]]
name = "compiler_builtins"
version = "0.1.32"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "7bc4ac2c824d2bfc612cba57708198547e9a26943af0632aff033e0693074d5c"
source = "git+https://git.m-labs.hk/pca006132/compiler-builtins-zynq.git#6dd42338c6731941614cdf979280fdffd96d532e"
dependencies = [
"cc",
]
[[package]]
name = "core_io"
@ -201,7 +203,7 @@ dependencies = [
[[package]]
name = "libasync"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#671968bac32ad4e98b1cbd6a117f41461cd44971"
dependencies = [
"embedded-hal",
"libcortex_a9",
@ -213,7 +215,7 @@ dependencies = [
[[package]]
name = "libboard_zynq"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#671968bac32ad4e98b1cbd6a117f41461cd44971"
dependencies = [
"bit_field",
"embedded-hal",
@ -237,10 +239,11 @@ dependencies = [
[[package]]
name = "libcortex_a9"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#671968bac32ad4e98b1cbd6a117f41461cd44971"
dependencies = [
"bit_field",
"libregister",
"volatile-register",
]
[[package]]
@ -252,7 +255,7 @@ checksum = "c7d73b3f436185384286bd8098d17ec07c9a7d2388a6599f824d8502b529702a"
[[package]]
name = "libregister"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#671968bac32ad4e98b1cbd6a117f41461cd44971"
dependencies = [
"bit_field",
"vcell",
@ -262,7 +265,7 @@ dependencies = [
[[package]]
name = "libsupport_zynq"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#671968bac32ad4e98b1cbd6a117f41461cd44971"
dependencies = [
"compiler_builtins",
"libboard_zynq",

@ -13,8 +13,16 @@ members = [
panic = "abort"
debug = true
codegen-units = 1
opt-level = 'z'
opt-level = 's'
lto = true
[profile.release.package.smoltcp]
opt-level = 2
[profile.release.package.libasync]
opt-level = 2
[profile.release.package.libboard_zynq]
opt-level = 2
[patch.crates-io]
core_io = { path = "./libcoreio" }
compiler_builtins = { git = "https://git.m-labs.hk/pca006132/compiler-builtins-zynq.git"}

@ -86,7 +86,7 @@ static CACHE_STORE: Mutex<BTreeMap<String, Vec<i32>>> = Mutex::new(BTreeMap::new
static DMA_RECORD_STORE: Mutex<BTreeMap<String, (Vec<u8>, i64)>> = Mutex::new(BTreeMap::new());
async fn write_header(stream: &TcpStream, reply: Reply) -> Result<()> {
stream.send([0x5a, 0x5a, 0x5a, 0x5a, reply.to_u8().unwrap()].iter().copied()).await?;
stream.send_slice(&[0x5a, 0x5a, 0x5a, 0x5a, reply.to_u8().unwrap()]).await?;
Ok(())
}
@ -138,7 +138,7 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
let stream = stream.unwrap();
write_header(stream, Reply::RPCRequest).await?;
write_bool(stream, is_async).await?;
stream.send(data.iter().copied()).await?;
stream.send_slice(&data).await?;
if !is_async {
let host_request = read_request(stream, false).await?.unwrap();
match host_request {
@ -298,7 +298,7 @@ async fn handle_connection(stream: &TcpStream, control: Rc<RefCell<kernel::Contr
match request {
Request::SystemInfo => {
write_header(stream, Reply::SystemInfo).await?;
stream.send("ARZQ".bytes()).await?;
stream.send_slice("ARZQ".as_bytes()).await?;
},
Request::LoadKernel => {
let buffer = read_bytes(stream, 1024*1024).await?;
@ -320,10 +320,10 @@ pub fn main(timer: GlobalTimer, cfg: &config::Config) {
info!("network addresses: {}", net_addresses);
let eth = zynq::eth::Eth::eth0(net_addresses.hardware_addr.0.clone());
const RX_LEN: usize = 8;
const RX_LEN: usize = 64;
// Number of transmission buffers (minimum is two because with
// one, duplicate packet transmission occurs)
const TX_LEN: usize = 8;
const TX_LEN: usize = 64;
let eth = eth.start_rx(RX_LEN);
let mut eth = eth.start_tx(TX_LEN);
@ -377,7 +377,7 @@ pub fn main(timer: GlobalTimer, cfg: &config::Config) {
let connection = Rc::new(Semaphore::new(1, 1));
let terminate = Rc::new(Semaphore::new(0, 1));
loop {
let stream = TcpStream::accept(1381, 2048, 2048).await.unwrap();
let stream = TcpStream::accept(1381, 0x10_000, 0x10_000).await.unwrap();
if connection.try_wait().is_none() {
// there is an existing connection

@ -120,26 +120,26 @@ pub async fn read_chunk(stream: &TcpStream, destination: &mut [u8]) -> Result<()
}
pub async fn write_i8(stream: &TcpStream, value: i8) -> Result<()> {
stream.send([value as u8].iter().copied()).await?;
stream.send_slice(&[value as u8]).await?;
Ok(())
}
pub async fn write_bool(stream: &TcpStream, value: bool) -> Result<()> {
stream.send([value as u8].iter().copied()).await?;
stream.send_slice(&[value as u8]).await?;
Ok(())
}
pub async fn write_i32(stream: &TcpStream, value: i32) -> Result<()> {
stream.send([
stream.send_slice(&[
(value >> 24) as u8,
(value >> 16) as u8,
(value >> 8) as u8,
value as u8].iter().copied()).await?;
value as u8]).await?;
Ok(())
}
pub async fn write_i64(stream: &TcpStream, value: i64) -> Result<()> {
stream.send([
stream.send_slice(&[
(value >> 56) as u8,
(value >> 48) as u8,
(value >> 40) as u8,
@ -147,12 +147,12 @@ pub async fn write_i64(stream: &TcpStream, value: i64) -> Result<()> {
(value >> 24) as u8,
(value >> 16) as u8,
(value >> 8) as u8,
value as u8].iter().copied()).await?;
value as u8]).await?;
Ok(())
}
pub async fn write_chunk(stream: &TcpStream, value: &[u8]) -> Result<()> {
write_i32(stream, value.len() as i32).await?;
stream.send(value.iter().copied()).await?;
stream.send_slice(value).await?;
Ok(())
}

@ -43,7 +43,7 @@ SECTIONS
.stack1 (NOLOAD) : ALIGN(8)
{
__stack1_end = .;
. += 0x4000;
. += 0x100;
__stack1_start = .;
} > OCM3

@ -10,7 +10,8 @@ use cstr_core::CStr;
use libcortex_a9::{
enable_fpu,
cache::{dcci_slice, iciallu, bpiall},
l2c::enable_l2_cache,
cache::{dcciall, iciallu, bpiall},
asm::{dsb, isb},
};
use libboard_zynq::{
@ -46,6 +47,7 @@ fn panic(_: &core::panic::PanicInfo) -> ! {
#[no_mangle]
pub fn main_core0() {
GlobalTimer::start();
enable_fpu();
logger::init().unwrap();
log::set_max_level(log::LevelFilter::Debug);
println!(r#"
@ -59,8 +61,8 @@ pub fn main_core0() {
(C) 2020 M-Labs
"#);
info!("Simple Zynq Loader starting...");
enable_l2_cache();
enable_fpu();
debug!("FPU enabled on Core0");
const CPU_FREQ: u32 = 800_000_000;
@ -79,12 +81,9 @@ pub fn main_core0() {
if result < 0 {
error!("decompression failed");
} else {
// Flush data cache entries for all of DDR, including
// Flush data cache entries for all of L1 cache, including
// Memory/Instruction Synchronization Barriers
dcci_slice(unsafe {
core::slice::from_raw_parts(ddr.ptr::<u8>(), ddr.size())
});
dsb();
dcciall();
iciallu();
bpiall();
dsb();

@ -0,0 +1,26 @@
let
pkgs = import <nixpkgs> {};
in
with pkgs;
pkgs.rustPlatform.buildRustPackage rec {
pname = "cargo-xbuild";
version = "0.5.21";
src = fetchFromGitHub {
owner = "rust-osdev";
repo = pname;
rev = "v${version}";
sha256 = "08mpnj3l6bcm1jg22lw1gcs0lkm4320fwl4p5y1s44w64963kzf7";
};
patches = [./xbuild.patch];
cargoSha256 = "1pj4x8y5vfpnn8vhxqqm3vicn29870r3jh0b17q3riq4vz1a2afp";
meta = with stdenv.lib; {
description = "Automatically cross-compiles the sysroot crates core, compiler_builtins, and alloc";
homepage = "https://github.com/rust-osdev/cargo-xbuild";
license = with licenses; [ mit asl20 ];
maintainers = with maintainers; [ johntitor xrelkd ];
};
}

@ -0,0 +1,13 @@
diff --git a/src/sysroot.rs b/src/sysroot.rs
index 1f3c8d1..e5615ee 100644
--- a/src/sysroot.rs
+++ b/src/sysroot.rs
@@ -163,7 +163,7 @@ version = "0.0.0"
edition = "2018"
[dependencies.compiler_builtins]
-version = "0.1.0"
+git = "https://git.m-labs.hk/pca006132/compiler-builtins-zynq.git"
"#;
let mut stoml = TOML.to_owned();
Loading…
Cancel
Save