zc706: not actually ultrascale

2 years ago · e045837b67
parent ada3f2e704
commit e045837b67
1 changed files with 1 additions and 1 deletions
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@ -399,7 +399,7 @@ class _SatelliteBase(SoCCore):
        self.submodules.siphaser = SiPhaser7Series(
            si5324_clkin=platform.request("si5324_clkin"),
            rx_synchronizer=self.rx_synchronizer,
-            ultrascale=True,
+            ultrascale=False,
            rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
        platform.add_false_path_constraints(
            self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output)