forked from M-Labs/artiq-zynq
use new exception vectors
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parent
8c0b7cdcf2
commit
de2c2af523
@ -15,7 +15,7 @@ let
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version = "0.1.0";
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src = ./src;
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cargoSha256 = "1vapk3xjaj4q3xz312nwwbdb7c9fr4439x2rchigh21d5yqfdpr7";
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cargoSha256 = "0pzk76a47fn6haiw300084c925wx6j40i8k3kmv5rlczg30c6zk7";
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nativeBuildInputs = [
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pkgs.gnumake
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10
src/Cargo.lock
generated
10
src/Cargo.lock
generated
@ -200,7 +200,7 @@ dependencies = [
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[[package]]
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name = "libasync"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#7082e07a1857d811bcf2f6982c655c411c5a1e4f"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f68b5896ce9287900f585723e76558f4755cbd78"
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dependencies = [
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"embedded-hal",
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"libcortex_a9",
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@ -212,7 +212,7 @@ dependencies = [
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[[package]]
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name = "libboard_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#7082e07a1857d811bcf2f6982c655c411c5a1e4f"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f68b5896ce9287900f585723e76558f4755cbd78"
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dependencies = [
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"bit_field",
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"embedded-hal",
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@ -236,7 +236,7 @@ dependencies = [
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[[package]]
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name = "libcortex_a9"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#7082e07a1857d811bcf2f6982c655c411c5a1e4f"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f68b5896ce9287900f585723e76558f4755cbd78"
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dependencies = [
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"bit_field",
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"libregister",
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@ -245,7 +245,7 @@ dependencies = [
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[[package]]
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name = "libregister"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#7082e07a1857d811bcf2f6982c655c411c5a1e4f"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f68b5896ce9287900f585723e76558f4755cbd78"
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dependencies = [
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"bit_field",
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"vcell",
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@ -255,7 +255,7 @@ dependencies = [
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[[package]]
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name = "libsupport_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#7082e07a1857d811bcf2f6982c655c411c5a1e4f"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f68b5896ce9287900f585723e76558f4755cbd78"
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dependencies = [
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"compiler_builtins",
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"libboard_zynq",
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@ -1,14 +1,4 @@
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ENTRY(_boot_cores);
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/* Provide some defaults */
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PROVIDE(Reset = _boot_cores);
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PROVIDE(UndefinedInstruction = Reset);
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PROVIDE(SoftwareInterrupt = Reset);
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PROVIDE(PrefetchAbort = Reset);
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PROVIDE(DataAbort = Reset);
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PROVIDE(ReservedException = Reset);
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PROVIDE(IRQ = Reset);
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PROVIDE(FIQ = Reset);
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ENTRY(Reset);
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MEMORY
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{
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@ -1,14 +1,4 @@
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ENTRY(_boot_cores);
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/* Provide some defaults */
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PROVIDE(Reset = _boot_cores);
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PROVIDE(UndefinedInstruction = Reset);
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PROVIDE(SoftwareInterrupt = Reset);
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PROVIDE(PrefetchAbort = Reset);
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PROVIDE(DataAbort = Reset);
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PROVIDE(ReservedException = Reset);
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PROVIDE(IRQ = Reset);
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PROVIDE(FIQ = Reset);
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ENTRY(Reset);
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MEMORY
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{
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