From c6fcc4e35139ddefd1c5a9f600dab6a932ef8c73 Mon Sep 17 00:00:00 2001 From: Egor Savkin Date: Thu, 13 Apr 2023 12:03:40 +0800 Subject: [PATCH] Add ext0_synth0_80to125 option to the clocker config Signed-off-by: Egor Savkin --- src/runtime/src/rtio_clocking.rs | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs index 880cc080..c98eae69 100644 --- a/src/runtime/src/rtio_clocking.rs +++ b/src/runtime/src/rtio_clocking.rs @@ -20,6 +20,7 @@ pub enum RtioClock { Int_150, Ext0_Bypass, Ext0_Synth0_10to125, + Ext0_Synth0_80to125, Ext0_Synth0_100to125, Ext0_Synth0_125to125, } @@ -36,6 +37,7 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock { "ext0_bypass_125" => RtioClock::Ext0_Bypass, "ext0_bypass_100" => RtioClock::Ext0_Bypass, "ext0_synth0_10to125" => RtioClock::Ext0_Synth0_10to125, + "ext0_synth0_80to125" => RtioClock::Ext0_Synth0_80to125, "ext0_synth0_100to125" => RtioClock::Ext0_Synth0_100to125, "ext0_synth0_125to125" => RtioClock::Ext0_Synth0_125to125, _ => { @@ -130,6 +132,23 @@ fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) { SI5324_EXT_INPUT, ) } + RtioClock::Ext0_Synth0_80to125 => { + // 125 MHz output from 80 MHz CLKINx reference, 611 Hz BW + info!("using 80MHz reference to make 125MHz RTIO clock with PLL"); + ( + si5324::FrequencySettings { + n1_hs: 4, + nc1_ls: 10, + n2_hs: 10, + n2_ls: 250, + n31: 40, + n32: 40, + bwsel: 4, + crystal_as_ckin2: false, + }, + SI5324_EXT_INPUT, + ) + } RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth info!("using 100MHz reference to make 125MHz RTIO clock with PLL");