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@ -18,14 +18,36 @@ static CORE1_RESTART: AtomicBool = AtomicBool::new(false); |
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#[no_mangle] |
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#[naked] |
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pub unsafe extern "C" fn IRQ() { |
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asm!( |
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// setup SP, depending on CPU 0 or 1
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"mrc p15, #0, r0, c0, c0, #5", |
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"movw r1, :lower16:__stack0_start", |
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"movt r1, :upper16:__stack0_start", |
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"tst r0, #3", |
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"movwne r1, :lower16:__stack1_start", |
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"movtne r1, :upper16:__stack1_start", |
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"mov sp, r1", |
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"bl __IRQ", |
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options(noreturn) |
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); |
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} |
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#[no_mangle] |
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pub unsafe extern "C" fn __IRQ() { |
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if MPIDR.read().cpu_id() == 1 { |
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let mpcore = mpcore::RegisterBlock::mpcore(); |
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let mut gic = gic::InterruptController::gic(mpcore); |
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let id = gic.get_interrupt_id(); |
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if id.0 == 0 { |
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gic.end_interrupt(id); |
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// save the SP and set it back after exiting IRQ
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// exception unwinding expect to unwind from this function, as this is not the entrance
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// function, maybe to IRQ which cannot further unwind...
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// if we set the SP to __stack1_start, interesting exceptions would be triggered when
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// we try to unwind the stack...
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let v = SP.read(); |
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asm::exit_irq(); |
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SP.write(&mut __stack1_start as *mut _ as u32); |
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SP.write(v); |
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asm::enable_irq(); |
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CORE1_RESTART.store(false, Ordering::Relaxed); |
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notify_spin_lock(); |
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