forked from M-Labs/artiq-zynq
Add grabber module
Signed-off-by: Egor Savkin <es@m-labs.hk>
This commit is contained in:
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812aea33b3
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b768d5648c
@ -107,6 +107,7 @@ class GTPBootstrapClock(Module):
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class GenericStandalone(SoCCore):
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def __init__(self, description, acpki=False):
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self.acpki = acpki
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clk_freq = description["rtio_frequency"]
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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@ -138,7 +139,8 @@ class GenericStandalone(SoCCore):
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Instance("BUFG", i_I=clk_synth_se, o_O=clk_synth_se_buf),
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]
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fix_serdes_timing_path(platform)
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, description["rtio_frequency"])
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se_buf)
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platform.add_false_path_constraints(
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@ -229,6 +231,7 @@ class GenericMaster(SoCCore):
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pads=data_pads,
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clk_freq=clk_freq)
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self.csr_devices.append("gt_drtio")
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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txout_buf = Signal()
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gtx0 = self.gt_drtio.gtxs[0]
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@ -532,6 +535,7 @@ class GenericSatellite(SoCCore):
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rtio_clk_period = 1e9/clk_freq
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self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk"),
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163
src/libboard_artiq/src/grabber.rs
Normal file
163
src/libboard_artiq/src/grabber.rs
Normal file
@ -0,0 +1,163 @@
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use log::info;
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use crate::pl::csr;
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#[derive(PartialEq, Clone, Copy)]
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enum State {
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Reset,
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ExitReset,
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Lock,
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Align,
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Watch,
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}
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#[derive(Clone, Copy)]
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struct Info {
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state: State,
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frame_size: (u16, u16),
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}
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static mut INFO: [Info; csr::GRABBER_LEN] = [Info {
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state: State::Reset,
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frame_size: (0, 0),
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}; csr::GRABBER_LEN];
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fn get_pll_reset(g: usize) -> bool {
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unsafe { (csr::GRABBER[g].pll_reset_read)() != 0 }
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}
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fn set_pll_reset(g: usize, reset: bool) {
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let val = if reset { 1 } else { 0 };
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unsafe { (csr::GRABBER[g].pll_reset_write)(val) }
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}
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fn pll_locked(g: usize) -> bool {
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unsafe { (csr::GRABBER[g].pll_locked_read)() != 0 }
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}
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fn clock_pattern_ok(g: usize) -> bool {
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unsafe { (csr::GRABBER[g].clk_sampled_read)() == 0b1100011 }
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}
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fn clock_pattern_ok_filter(g: usize) -> bool {
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for _ in 0..128 {
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if !clock_pattern_ok(g) {
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return false;
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}
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}
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true
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}
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fn phase_shift(g: usize, direction: u8) {
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unsafe {
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(csr::GRABBER[g].phase_shift_write)(direction);
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while (csr::GRABBER[g].phase_shift_done_read)() == 0 {}
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}
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}
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fn clock_align(g: usize) -> bool {
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while clock_pattern_ok_filter(g) {
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phase_shift(g, 1);
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}
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phase_shift(g, 1);
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let mut count = 0;
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while !clock_pattern_ok_filter(g) {
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phase_shift(g, 1);
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count += 1;
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if count > 1024 {
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return false;
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}
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}
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let mut window = 1;
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phase_shift(g, 1);
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while clock_pattern_ok_filter(g) {
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phase_shift(g, 1);
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window += 1;
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}
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for _ in 0..window / 2 {
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phase_shift(g, 0);
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}
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true
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}
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fn get_last_pixels(g: usize) -> (u16, u16) {
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unsafe { ((csr::GRABBER[g].last_x_read)(), (csr::GRABBER[g].last_y_read)()) }
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}
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fn get_video_clock(g: usize) -> u32 {
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let freq_count = unsafe { (csr::GRABBER[g].freq_count_read)() } as u32;
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2 * freq_count * (csr::CONFIG_CLOCK_FREQUENCY / 1000) / (511 * 1000)
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}
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pub fn tick() {
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for g in 0..csr::GRABBER.len() {
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let next = match unsafe { INFO[g].state } {
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State::Reset => {
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set_pll_reset(g, true);
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unsafe {
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INFO[g].frame_size = (0, 0);
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}
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State::ExitReset
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}
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State::ExitReset => {
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if get_pll_reset(g) {
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set_pll_reset(g, false);
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State::Lock
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} else {
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State::ExitReset
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}
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}
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State::Lock => {
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if pll_locked(g) {
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info!("grabber{} locked: {}MHz", g, get_video_clock(g));
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State::Align
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} else {
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State::Lock
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}
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}
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State::Align => {
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if pll_locked(g) {
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if clock_align(g) {
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info!("grabber{} alignment success", g);
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State::Watch
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} else {
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info!("grabber{} alignment failure", g);
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State::Reset
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}
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} else {
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info!("grabber{} lock lost", g);
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State::Reset
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}
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}
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State::Watch => {
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if pll_locked(g) {
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if clock_pattern_ok(g) {
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let last_xy = get_last_pixels(g);
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if last_xy != unsafe { INFO[g].frame_size } {
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// x capture is on ~LVAL which is after
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// the last increment on DVAL
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// y capture is on ~FVAL which coincides with the
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// last increment on ~LVAL
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info!("grabber{} frame size: {}x{}", g, last_xy.0, last_xy.1 + 1);
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unsafe { INFO[g].frame_size = last_xy }
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}
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State::Watch
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} else {
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info!("grabber{} alignment lost", g);
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State::Reset
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}
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} else {
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info!("grabber{} lock lost", g);
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State::Reset
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}
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}
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};
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unsafe {
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INFO[g].state = next;
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}
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}
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}
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@ -31,6 +31,8 @@ pub mod mem;
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pub mod pl;
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#[cfg(has_drtio_eem)]
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pub mod drtio_eem;
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#[cfg(has_grabber)]
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pub mod grabber;
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#[cfg(has_si5324)]
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pub mod si5324;
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@ -57,6 +57,20 @@ async fn io_expanders_service(
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}
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}
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#[cfg(has_grabber)]
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mod grabber {
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use libasync::delay;
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use libboard_artiq::grabber;
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use libboard_zynq::time::Milliseconds;
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pub async fn grabber_thread(mut timer: GlobalTimer) {
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let mut countdown = timer.countdown();
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loop {
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grabber::tick();
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delay(&mut countdown, Milliseconds(200)).await;
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}
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}
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}
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static mut LOG_BUFFER: [u8; 1 << 17] = [0; 1 << 17];
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#[no_mangle]
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@ -114,6 +128,9 @@ pub fn main_core0() {
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#[cfg(has_drtio_eem)]
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drtio_eem::init(&mut timer, &cfg);
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#[cfg(has_grabber)]
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task::spawn(grabber::grabber_thread(timer));
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task::spawn(ksupport::report_async_rtio_errors());
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#[cfg(feature = "target_kasli_soc")]
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use analyzer::Analyzer;
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use dma::Manager as DmaManager;
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use embedded_hal::blocking::delay::DelayUs;
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#[cfg(has_grabber)]
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use libboard_artiq::grabber;
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#[cfg(feature = "target_kasli_soc")]
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use libboard_artiq::io_expander;
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#[cfg(has_si5324)]
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@ -698,6 +700,8 @@ fn hardware_tick(ts: &mut u64, timer: &mut GlobalTimer) {
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if now > ts_ms {
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ts_ms = now + Milliseconds(200);
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*ts = ts_ms.0;
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#[cfg(has_grabber)]
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grabber::tick();
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}
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}
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