pca006132/artiq-zynq
1
0
Fork 0
forked from M-Labs/artiq-zynq
Code Issues Pull Requests Releases Wiki Activity

increase CSR bus width to 32 bits

Browse Source 
Before:
Minimum interval for sustained TTL output switching ... 1.554e-06

After:
Minimum interval for sustained TTL output switching ... 5.17e-07
This commit is contained in:
Sebastien Bourdeauducq 2020-07-07 17:22:07 +08:00
parent 7bfe882710
commit b13da96835
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/zc706.py
View File

@ -18,7 +18,7 @@ class ZC706(SoCCore):
platform.toolchain.bitstream_commands.extend([ platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
]) ])
SoCCore.__init__(self, platform=platform, ident=self.__class__.__name__) SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=self.__class__.__name__)
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")