dma: fix endianness issues

core0-buffer
parent a9f725dd33
commit ae7ca22db9
  1. 11
      src/gateware/analyzer.py
  2. 4
      src/gateware/dma.py
  3. 21
      src/gateware/endianness.py
  4. 2
      src/gateware/test_dma.py

@ -6,14 +6,7 @@ from migen_axi.interconnect import axi
from artiq.gateware.rtio.analyzer import message_len, MessageEncoder
def convert_endianness(signal):
assert len(signal) % 8 == 0
nbytes = len(signal)//8
signal_bytes = []
for i in range(nbytes):
signal_bytes.append(signal[8*i:8*(i+1)])
return Cat(*reversed(signal_bytes))
import endianness
class AXIDMAWriter(Module, AutoCSR):
@ -64,7 +57,7 @@ class AXIDMAWriter(Module, AutoCSR):
membus.w.id.eq(0),
membus.w.valid.eq(self.sink.stb),
self.sink.ack.eq(membus.w.ready),
membus.w.data.eq(convert_endianness(self.sink.data)),
membus.w.data.eq(endianness.convert_signal(self.sink.data)),
membus.w.strb.eq(2**(dw//8)-1),
]
beat_count = Signal(max=burst_length)

@ -6,6 +6,8 @@ from migen_axi.interconnect import axi
from artiq.gateware.rtio.dma import RawSlicer, RecordConverter, RecordSlicer, TimeOffset, CRIMaster
import endianness
AXI_BURST_LEN = 16
@ -50,7 +52,7 @@ class AXIReader(Module):
self.comb += [
self.source.stb.eq(membus.r.valid),
membus.r.ready.eq(self.source.ack),
self.source.data.eq(membus.r.data),
self.source.data.eq(endianness.convert_signal(membus.r.data)),
# Note that when eop_pending=1, no new transactions are made and inflight_cnt is no longer incremented
self.source.eop.eq(eop_pending & membus.r.last & (inflight_cnt == 1))
]

@ -0,0 +1,21 @@
from migen import *
def convert_signal(signal):
assert len(signal) % 8 == 0
nbytes = len(signal)//8
signal_bytes = []
for i in range(nbytes):
signal_bytes.append(signal[8*i:8*(i+1)])
return Cat(*reversed(signal_bytes))
def convert_value(value, size):
assert size % 8 == 0
nbytes = size//8
result = 0
for i in range(nbytes):
result <<= 8
result |= value & 0xff
value >>= 8
return result

@ -10,6 +10,7 @@ from artiq.gateware import rtio
from artiq.gateware.rtio import cri
from artiq.gateware.rtio.phy import ttl_simple
import endianness
import dma
@ -47,6 +48,7 @@ class AXIMemorySim:
data = self.data[addr]
else:
data = 0
data = endianness.convert_value(data, len(self.bus.r.data))
yield from self.bus.write_r(request.id, data, last=i == request_len-1)
else:
yield

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