set up PL clocks

default.nix

@@ -15,7 +15,7 @@ let
       version = "0.1.0";
 
       src = ./src;
-      cargoSha256 = "064s5kg0hw27vibh2nih7rkg1iw7k4jkrjw41xx0dyqk4z8fy3q8";
+      cargoSha256 = "0xminds5fyp7c9vsx651zv3yzyhxnl9a02rhjl2wfxf8m679r45l";
 
       nativeBuildInputs = [
         pkgs.gnumake

src/Cargo.lock

@@ -200,7 +200,7 @@ dependencies = [
 [[package]]
 name = "libasync"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#e67efe439b4c1a535a9d784fef3547d95584a909"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
 dependencies = [
  "embedded-hal",
  "libcortex_a9",
@@ -212,7 +212,7 @@ dependencies = [
 [[package]]
 name = "libboard_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#e67efe439b4c1a535a9d784fef3547d95584a909"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
 dependencies = [
  "bit_field",
  "embedded-hal",
@@ -236,7 +236,7 @@ dependencies = [
 [[package]]
 name = "libcortex_a9"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#e67efe439b4c1a535a9d784fef3547d95584a909"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
 dependencies = [
  "bit_field",
  "libregister",
@@ -245,7 +245,7 @@ dependencies = [
 [[package]]
 name = "libregister"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#e67efe439b4c1a535a9d784fef3547d95584a909"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
 dependencies = [
  "bit_field",
  "vcell",
@@ -255,7 +255,7 @@ dependencies = [
 [[package]]
 name = "libsupport_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#e67efe439b4c1a535a9d784fef3547d95584a909"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
 dependencies = [
  "compiler_builtins",
  "libboard_zynq",
@@ -396,6 +396,7 @@ dependencies = [
  "libboard_zynq",
  "libc",
  "libcortex_a9",
+ "libregister",
  "libsupport_zynq",
  "log",
  "num-derive",

src/runtime/Cargo.toml

@@ -23,6 +23,7 @@ libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
 libsupport_zynq = { default-features = false, git = "https://git.m-labs.hk/M-Labs/zc706.git" }
 libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
 libasync = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
+libregister = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
 dyld = { path = "../libdyld" }
 dwarf = { path = "../libdwarf" }
 unwind = { path = "../libunwind" }

src/runtime/src/main.rs

@@ -11,6 +11,7 @@ use log::info;
 
 use libboard_zynq::{timer::GlobalTimer, logger, devc, slcr};
 use libsupport_zynq::ram;
+use libregister::RegisterW;
 
 mod sd_reader;
 mod config;
@@ -50,6 +51,26 @@ pub fn main_core0() {
 
     ram::init_alloc_linker();
 
+    // Set up PS->PL clocks
+    slcr::RegisterBlock::unlocked(|slcr| {
+        // As we are touching the mux, the clock may glitch, so reset the PL.
+        slcr.fpga_rst_ctrl.write(
+            slcr::FpgaRstCtrl::zeroed()
+                .fpga0_out_rst(true)
+                .fpga1_out_rst(true)
+                .fpga2_out_rst(true)
+                .fpga3_out_rst(true)
+        );
+        slcr.fpga0_clk_ctrl.write(
+            slcr::Fpga0ClkCtrl::zeroed()
+                .src_sel(slcr::PllSource::IoPll)
+                .divisor0(8)
+                .divisor1(1)
+        );
+        slcr.fpga_rst_ctrl.write(
+            slcr::FpgaRstCtrl::zeroed()
+        );
+    });
     if devc::DevC::new().is_done() {
         info!("gateware already loaded");
         // Do not load again: assume that the gateware already present is