core1: added cache flush and barriers.

src/runtime/src/kernel/core1.rs

@@ -5,7 +5,12 @@ use alloc::borrow::ToOwned;
 use log::{debug, info, error};
 use cslice::CSlice;
 
-use libcortex_a9::{enable_fpu, cache::{dcci_slice, iciallu}, sync_channel};
+use libcortex_a9::{
+    enable_fpu,
+    cache::{dcci_slice, iciallu, bpiall},
+    asm::{dsb, isb},
+    sync_channel
+};
 use dyld::{self, Library};
 use crate::eh_artiq;
 use super::{
@@ -92,7 +97,11 @@ impl KernelImage {
         // Flush data cache entries for the image in DDR, including
         // Memory/Instruction Synchronization Barriers
         dcci_slice(self.library.image.data);
+        dsb();
         iciallu();
+        bpiall();
+        dsb();
+        isb();
 
         (mem::transmute::<u32, fn()>(self.__modinit__))();