forked from M-Labs/artiq-zynq
kernel: added core1 instruction cache flush
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@ -5,7 +5,7 @@ use alloc::borrow::ToOwned;
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use log::{debug, info, error};
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use cslice::CSlice;
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use libcortex_a9::{enable_fpu, cache::dcci_slice, sync_channel};
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use libcortex_a9::{enable_fpu, cache::{dcci_slice, iciallu}, sync_channel};
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use dyld::{self, Library};
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use crate::eh_artiq;
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use super::{
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@ -92,6 +92,7 @@ impl KernelImage {
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// Flush data cache entries for the image in DDR, including
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// Memory/Instruction Synchronization Barriers
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dcci_slice(self.library.image.data);
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iciallu();
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(mem::transmute::<u32, fn()>(self.__modinit__))();
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