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@ -12,7 +12,7 @@ import endianness |
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AXI_BURST_LEN = 16 |
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class AXIReader(Module): |
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class AXIReader(Module, AutoCSR): |
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def __init__(self, membus): |
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aw = len(membus.ar.addr) |
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dw = len(membus.r.data) |
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@ -20,6 +20,8 @@ class AXIReader(Module): |
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self.sink = stream.Endpoint([("address", aw - alignment_bits)]) |
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self.source = stream.Endpoint([("data", dw)]) |
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self.bus_error = CSRStatus() |
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# # # |
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eop_pending = Signal() |
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@ -57,6 +59,17 @@ class AXIReader(Module): |
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self.source.eop.eq(eop_pending & membus.r.last & (inflight_cnt == 1)) |
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] |
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stopped = Signal(reset=1) |
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self.sync += [ |
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If(self.source.stb & self.source.ack & self.source.eop, stopped.eq(1)), |
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If(self.sink.stb & self.sink.ack, stopped.eq(0)), |
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If(stopped & (self.sink.stb & self.sink.ack), |
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# reset bus error status on new run |
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self.bus_error.status.eq(0)), |
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If(membus.r.valid & membus.r.valid & (membus.r.resp != axi.Response.okay), |
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self.bus_error.status.eq(1)) |
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] |
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class DMAReader(Module, AutoCSR): |
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def __init__(self, membus, enable): |
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