diff --git a/src/szl/build.rs b/src/szl/build.rs
index 349572db..a02dfd01 100644
--- a/src/szl/build.rs
+++ b/src/szl/build.rs
@@ -31,7 +31,7 @@ pub fn compile_unlzma() {
     cfg.flag("-ffreestanding");
     cfg.flag("-fPIC");
     cfg.flag("-fno-stack-protector");
-    cfg.flag("--target=armv7-unknown-linux");
+    cfg.flag("--target=armv7-none-eabihf");
     cfg.flag("-O2");
 
     let sources = vec![
diff --git a/src/szl/src/main.rs b/src/szl/src/main.rs
index 2570f478..56d0ea8d 100644
--- a/src/szl/src/main.rs
+++ b/src/szl/src/main.rs
@@ -1,5 +1,6 @@
 #![no_std]
 #![no_main]
+#![feature(llvm_asm)]
 
 extern crate log;
 
@@ -36,6 +37,18 @@ pub fn main_core0() {
     log::set_max_level(log::LevelFilter::Debug);
     info!("Simple Zynq Loader starting...");
 
+    unsafe {
+        llvm_asm!("
+            mrc p15, 0, r1, c1, c0, 2
+            orr r1, r1, (0b1111<<20)
+            mcr p15, 0, r1, c1, c0, 2
+
+            vmrs r1, fpexc
+            orr r1, r1, (1<<30)
+            vmsr fpexc, r1
+            ":::"r1");
+    }
+    info!("FPU enabled on Core0");
     const CPU_FREQ: u32 = 800_000_000;
 
     ArmPll::setup(2 * CPU_FREQ);