forked from M-Labs/artiq-zynq
kasli-soc: remove irrelevant comment
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@ -197,8 +197,6 @@ class GenericMaster(SoCCore):
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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# kasli_soc has no SATA, but it has 4x SFP
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# not sure yet why sfp0 is omitted in MasterMode
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data_pads = [platform.request("sfp", i) for i in range(4)]
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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