forked from M-Labs/artiq-zynq
runtime: wait longer for PLL lock
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e451598a06
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@ -76,7 +76,7 @@ fn init_rtio(timer: &mut GlobalTimer) {
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}
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// if it's not locked, it will hang at the CSR.
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timer.delay_ms(20); // wait for CPLL/QPLL/SYS PLL lock
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timer.delay_ms(50); // wait for CPLL/QPLL/SYS PLL lock
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let clk = unsafe { pl::csr::sys_crg::current_clock_read() };
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if clk == 1 {
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info!("SYS CLK switched successfully");
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@ -95,7 +95,7 @@ fn init_drtio(timer: &mut GlobalTimer) {
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pl::csr::gt_drtio::stable_clkin_write(1);
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}
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timer.delay_ms(20); // wait for CPLL/QPLL/SYS PLL lock
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timer.delay_ms(50); // wait for CPLL/QPLL/SYS PLL lock
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let clk = unsafe { pl::csr::sys_crg::current_clock_read() };
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if clk == 1 {
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info!("SYS CLK switched successfully");
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