From 3a77ddbcc9dbfd4b9acaace339ad876f4725ba52 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 24 Apr 2020 13:36:36 +0800
Subject: [PATCH] gateware: add moninj

---
 zc706.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/zc706.py b/zc706.py
index fa2eb98e..939695d3 100755
--- a/zc706.py
+++ b/zc706.py
@@ -46,6 +46,9 @@ class ZC706(SoCCore):
 
         self.comb += self.rtio.cri.connect(self.rtio_core.cri)
 
+        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
 
 def write_csr_file(soc, filename):
     with open(filename, "w") as f: