forked from M-Labs/artiq-zynq
gateware/coraz7: remove unused VARIANTS
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@ -139,9 +139,6 @@ class Simple(CoraZ7):
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self.add_rtio(rtio_channels)
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VARIANTS = {cls.__name__.lower(): cls for cls in [Simple]}
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def write_csr_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_csr_rust(
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