forked from M-Labs/artiq-zynq
Set FCLK0 for EBAZ4205
EBAZ4205 uses FCLK0 as the RTIO clock. If the user modifies the gateware to use an external clock, FCLK0 is not used. Co-authored-by: newell <newell.jensen@gmail.com> Co-committed-by: newell <newell.jensen@gmail.com>
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@ -12,9 +12,9 @@ use libboard_artiq::si549;
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use libboard_zynq::i2c::I2c;
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use libboard_zynq::i2c::I2c;
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use libboard_zynq::timer::GlobalTimer;
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use libboard_zynq::timer::GlobalTimer;
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use libconfig::Config;
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use libconfig::Config;
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#[cfg(not(feature = "target_ebaz4205"))]
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use log::{info, warn};
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use log::info;
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#[cfg(feature = "target_ebaz4205")]
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use log::warn;
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use {libboard_zynq::slcr, libregister::RegisterRW};
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#[derive(Debug, PartialEq, Copy, Clone)]
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#[derive(Debug, PartialEq, Copy, Clone)]
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#[allow(non_camel_case_types)]
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#[allow(non_camel_case_types)]
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@ -410,6 +410,38 @@ fn get_si549_setting(clk: RtioClock) -> si549::FrequencySetting {
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}
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}
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}
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}
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#[cfg(feature = "target_ebaz4205")]
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fn set_fclk0_freq(clk: RtioClock, cfg: &Config) {
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let io_pll_freq: u32 = 1_000_000_000; // Hardcoded in zynq-rs
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let mut target_freq = 0;
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let mut divisor0 = 1u8;
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match clk {
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RtioClock::Int_100 => {
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target_freq = 100_000_000;
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divisor0 = 10;
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}
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RtioClock::Int_125 => {
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target_freq = 125_000_000;
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divisor0 = 8;
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}
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_ => {
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warn!("Unsupported RTIO Clock: '{:?}'", clk);
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return;
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}
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}
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.fpga0_clk_ctrl.modify(|_, w| w.divisor0(divisor0));
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});
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info!(
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"Set FCLK0 to {:.2} MHz (target: {} MHz).",
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io_pll_freq as f64 / divisor0 as f64,
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target_freq / 1_000_000
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);
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}
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pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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let clk = get_rtio_clock_cfg(cfg);
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let clk = get_rtio_clock_cfg(cfg);
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#[cfg(has_si5324)]
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#[cfg(has_si5324)]
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@ -436,6 +468,16 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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#[cfg(not(any(has_drtio, feature = "target_ebaz4205")))]
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#[cfg(not(any(has_drtio, feature = "target_ebaz4205")))]
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init_rtio(timer);
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init_rtio(timer);
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#[cfg(feature = "target_ebaz4205")]
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{
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match clk {
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RtioClock::Int_100 | RtioClock::Int_125 => {
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set_fclk0_freq(clk, cfg);
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}
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_ => {} // Not set for external clocks
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}
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}
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#[cfg(all(has_si549, has_wrpll))]
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#[cfg(all(has_si549, has_wrpll))]
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{
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{
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// SYS CLK switch will reset CSRs that are used by WRPLL
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// SYS CLK switch will reset CSRs that are used by WRPLL
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