forked from M-Labs/artiq-zynq
DDMTD: replace 1st edge to median edge deglitcher
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@ -51,26 +51,52 @@ class DDMTDSampler(Module):
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]
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class DDMTDDeglitcherFirstEdge(Module):
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def __init__(self, input_signal, blind_period=400):
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class DDMTDDeglitcherMedianEdge(Module):
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def __init__(self, counter, input_signal, stable_0_period=100, stable_1_period=100):
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self.tag = Signal(len(counter))
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self.detect = Signal()
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rising = Signal()
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input_signal_r = Signal()
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stable_0_counter = Signal(reset=stable_0_period - 1, max=stable_0_period)
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stable_1_counter = Signal(reset=stable_1_period - 1, max=stable_1_period)
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# # #
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self.sync.helper += [
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input_signal_r.eq(input_signal),
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rising.eq(input_signal & ~input_signal_r)
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]
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blind_counter = Signal(max=blind_period)
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self.sync.helper += [
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If(blind_counter != 0, blind_counter.eq(blind_counter - 1)),
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If(input_signal_r, blind_counter.eq(blind_period - 1)),
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self.detect.eq(rising & (blind_counter == 0))
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]
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# Based on CERN's median edge deglitcher FSM
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# https://white-rabbit.web.cern.ch/documents/Precise_time_and_frequency_transfer_in_a_White_Rabbit_network.pdf (p.72)
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fsm = ClockDomainsRenamer("helper")(FSM(reset_state="WAIT_STABLE_0"))
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self.submodules += fsm
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fsm.act("WAIT_STABLE_0",
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If(stable_0_counter != 0,
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NextValue(stable_0_counter, stable_0_counter - 1)
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).Else(
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NextValue(stable_0_counter, stable_0_period - 1),
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NextState("WAIT_EDGE")
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),
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If(input_signal,
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NextValue(stable_0_counter, stable_0_period - 1)
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),
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)
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fsm.act("WAIT_EDGE",
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If(input_signal,
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NextValue(self.tag, counter),
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NextState("GOT_EDGE")
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)
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)
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fsm.act("GOT_EDGE",
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If(stable_1_counter != 0,
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NextValue(stable_1_counter, stable_1_counter - 1)
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).Else(
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NextValue(stable_1_counter, stable_1_period - 1),
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self.detect.eq(1),
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NextState("WAIT_STABLE_0")
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),
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If(~input_signal,
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NextValue(self.tag, self.tag + 1),
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NextValue(stable_1_counter, stable_1_period - 1)
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),
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)
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class DDMTD(Module):
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def __init__(self, counter, input_signal):
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@ -81,13 +107,13 @@ class DDMTD(Module):
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# # #
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deglitcher = DDMTDDeglitcherFirstEdge(input_signal)
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deglitcher = DDMTDDeglitcherMedianEdge(counter, input_signal)
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self.submodules += deglitcher
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self.sync.helper += [
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self.h_tag_update.eq(0),
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If(deglitcher.detect,
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self.h_tag_update.eq(1),
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self.h_tag.eq(counter)
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self.h_tag.eq(deglitcher.tag)
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)
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]
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