forked from M-Labs/artiq-zynq
consolidate all write..file()
into config.py
This commit is contained in:
parent
2c19f4ac31
commit
1ccae0d442
22
src/gateware/config.py
Normal file
22
src/gateware/config.py
Normal file
@ -0,0 +1,22 @@
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from misoc.integration import cpu_interface
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def write_csr_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_csr_rust(
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soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
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def write_mem_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_mem_rust(
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soc.get_memory_regions(), soc.get_memory_groups(), None))
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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for name, origin, busword, obj in soc.get_csr_regions():
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f.write("has_{}\n".format(name.lower()))
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for name, value in soc.get_constants():
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if name.upper().startswith("CONFIG_"):
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if value is None:
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f.write("{}\n".format(name.lower()[7:]))
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else:
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f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value)))
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@ -11,7 +11,6 @@ from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import kasli_soc
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from misoc.interconnect.csr import *
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from misoc.cores import virtual_leds
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from misoc.integration import cpu_interface
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from artiq.coredevice import jsondesc
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from artiq.gateware import rtio, eem_7series
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@ -27,7 +26,7 @@ import analyzer
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import acpki
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import drtio_aux_controller
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import zynq_clocking
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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eem_iostandard_dict = {
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0: "LVDS_25",
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@ -484,31 +483,6 @@ class GenericSatellite(SoCCore):
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self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
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for i, channel in enumerate(self.gt_drtio.channels)]
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def write_mem_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_mem_rust(
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soc.get_memory_regions(), soc.get_memory_groups(), None))
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def write_csr_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_csr_rust(
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soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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for name, origin, busword, obj in soc.get_csr_regions():
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f.write("has_{}\n".format(name.lower()))
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for name, value in soc.get_constants():
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if name.upper().startswith("CONFIG_"):
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if value is None:
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f.write("{}\n".format(name.lower()[7:]))
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else:
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f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value)))
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder for generic Kasli-SoC systems")
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@ -10,7 +10,6 @@ from migen.genlib.cdc import MultiReg
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from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import zc706
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from misoc.interconnect.csr import *
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from misoc.integration import cpu_interface
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from misoc.cores import gpio
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from artiq.gateware import rtio, nist_clock, nist_qc2
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@ -26,7 +25,7 @@ import analyzer
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import acpki
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import drtio_aux_controller
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import zynq_clocking
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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class SMAClkinForward(Module):
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def __init__(self, platform):
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@ -672,30 +671,6 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
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VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
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NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
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def write_csr_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_csr_rust(
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soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
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def write_mem_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_mem_rust(
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soc.get_memory_regions(), soc.get_memory_groups(), None))
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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for name, origin, busword, obj in soc.get_csr_regions():
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f.write("has_{}\n".format(name.lower()))
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for name, value in soc.get_constants():
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if name.upper().startswith("CONFIG_"):
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if value is None:
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f.write("{}\n".format(name.lower()[7:]))
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else:
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f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value)))
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ port to the ZC706 Zynq development kit")
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