analyzer: fix endianness issue

core0-buffer
parent 84630d66e3
commit 10a12245a3
  1. 11
      src/gateware/analyzer.py

@ -7,6 +7,15 @@ from migen_axi.interconnect import axi
from artiq.gateware.rtio.analyzer import message_len, MessageEncoder
def convert_endianness(signal):
assert len(signal) % 8 == 0
nbytes = len(signal)//8
signal_bytes = []
for i in range(nbytes):
signal_bytes.append(signal[8*i:8*(i+1)])
return Cat(*reversed(signal_bytes))
class AXIDMAWriter(Module, AutoCSR):
def __init__(self, membus, max_outstanding_requests):
aw = len(membus.aw.addr)
@ -55,7 +64,7 @@ class AXIDMAWriter(Module, AutoCSR):
membus.w.id.eq(0),
membus.w.valid.eq(self.sink.stb),
self.sink.ack.eq(membus.w.ready),
membus.w.data.eq(self.sink.data),
membus.w.data.eq(convert_endianness(self.sink.data)),
membus.w.strb.eq(2**(dw//8)-1),
]
beat_count = Signal(max=burst_length)

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