forked from M-Labs/artiq-zynq
zynq_clocking: add ext_async_rst to AsyncRstSYNCR
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79fc5a7789
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07044752b6
@ -65,7 +65,7 @@ class ClockSwitchFSM(Module):
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class SYSCRG(Module, AutoCSR):
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def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6):
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def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6, ext_async_rst=None):
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# assumes bootstrap clock is same freq as main and sys output
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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@ -125,10 +125,19 @@ class SYSCRG(Module, AutoCSR):
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Instance("BUFG", i_I=mmcm_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=mmcm_sys4x, o_O=self.cd_sys4x.clk),
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Instance("BUFG", i_I=mmcm_clk208, o_O=self.cd_clk200.clk),
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AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked),
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AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked),
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]
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if ext_async_rst is not None:
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self.specials += [
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AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked | ext_async_rst),
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AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked | ext_async_rst),
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]
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else:
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self.specials += [
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AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked),
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AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked),
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]
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reset_counter = Signal(4, reset=15)
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ic_reset = Signal(reset=1)
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self.sync.clk200 += \
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