2020-04-11 20:19:39 +08:00
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#![no_std]
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#![no_main]
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2020-04-25 20:45:25 +08:00
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#![recursion_limit="1024"] // for futures_util::select!
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2020-07-02 13:10:11 +08:00
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#![feature(alloc_error_handler)]
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#![feature(panic_info_message)]
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2020-07-20 14:10:46 +08:00
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#![feature(c_variadic)]
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2020-07-25 12:12:56 +08:00
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#![feature(const_btree_new)]
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2020-07-28 01:54:53 +08:00
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#![feature(ptr_offset_from)]
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2020-08-04 10:15:57 +08:00
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#![feature(const_in_array_repeat_expressions)]
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#![feature(naked_functions)]
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2020-04-11 20:19:39 +08:00
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extern crate alloc;
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2020-04-11 21:32:44 +08:00
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use core::{cmp, str};
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2020-07-13 16:06:05 +08:00
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use log::{info, warn, error};
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2020-04-11 22:24:23 +08:00
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2020-09-01 15:43:54 +08:00
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use libboard_zynq::{timer::GlobalTimer, mpcore, gic, slcr};
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2020-07-13 16:06:05 +08:00
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use libasync::{task, block_async};
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2020-05-01 08:18:36 +08:00
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use libsupport_zynq::ram;
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2020-07-13 16:06:05 +08:00
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use nb;
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use void::Void;
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2020-07-23 05:58:55 +08:00
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use embedded_hal::blocking::delay::DelayMs;
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2020-09-01 15:43:54 +08:00
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use libconfig::Config;
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use libregister::RegisterW;
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2020-04-11 21:32:44 +08:00
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2020-06-05 17:14:36 +08:00
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mod proto_core_io;
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mod proto_async;
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2020-04-13 13:48:08 +08:00
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mod comms;
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2020-06-01 18:02:21 +08:00
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mod rpc;
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2020-05-07 13:52:40 +08:00
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#[path = "../../../build/pl.rs"]
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2020-04-11 21:32:44 +08:00
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mod pl;
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2020-08-04 13:15:26 +08:00
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#[cfg(ki_impl = "csr")]
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#[path = "rtio_csr.rs"]
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mod rtio;
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#[cfg(ki_impl = "acp")]
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#[path = "rtio_acp.rs"]
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2020-04-12 20:15:01 +08:00
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mod rtio;
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2020-04-13 13:48:08 +08:00
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mod kernel;
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2020-04-24 14:37:16 +08:00
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mod moninj;
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2020-07-02 10:10:33 +08:00
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mod eh_artiq;
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2020-07-02 13:10:11 +08:00
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mod panic;
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2020-07-13 14:59:56 +08:00
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mod logger;
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2020-07-13 15:00:53 +08:00
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mod mgmt;
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2020-07-16 11:47:55 +08:00
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mod analyzer;
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2020-08-04 10:17:19 +08:00
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mod irq;
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2020-04-11 21:32:44 +08:00
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2020-07-08 19:58:13 +08:00
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fn init_gateware() {
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2020-07-07 19:40:32 +08:00
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// Set up PS->PL clocks
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slcr::RegisterBlock::unlocked(|slcr| {
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// As we are touching the mux, the clock may glitch, so reset the PL.
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slcr.fpga_rst_ctrl.write(
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slcr::FpgaRstCtrl::zeroed()
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.fpga0_out_rst(true)
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.fpga1_out_rst(true)
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.fpga2_out_rst(true)
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.fpga3_out_rst(true)
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);
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slcr.fpga0_clk_ctrl.write(
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slcr::Fpga0ClkCtrl::zeroed()
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.src_sel(slcr::PllSource::IoPll)
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.divisor0(8)
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.divisor1(1)
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);
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slcr.fpga_rst_ctrl.write(
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slcr::FpgaRstCtrl::zeroed()
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);
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});
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2020-07-08 19:58:13 +08:00
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}
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fn identifier_read(buf: &mut [u8]) -> &str {
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unsafe {
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pl::csr::identifier::address_write(0);
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let len = pl::csr::identifier::data_read();
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let len = cmp::min(len, buf.len() as u8);
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for i in 0..len {
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pl::csr::identifier::address_write(1 + i);
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buf[i as usize] = pl::csr::identifier::data_read();
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}
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str::from_utf8_unchecked(&buf[..len as usize])
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}
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}
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2020-09-01 14:43:16 +08:00
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fn init_rtio(timer: &mut GlobalTimer, cfg: &Config) {
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2020-07-08 19:58:13 +08:00
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let clock_sel =
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if let Ok(rtioclk) = cfg.read_str("rtioclk") {
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match rtioclk.as_ref() {
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"internal" => {
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info!("using internal RTIO clock");
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0
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},
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"external" => {
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info!("using external RTIO clock");
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1
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},
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other => {
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warn!("RTIO clock specification '{}' not recognized", other);
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info!("using internal RTIO clock");
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0
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},
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}
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} else {
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info!("using internal RTIO clock (default)");
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0
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};
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2020-07-25 11:15:33 +08:00
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loop {
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unsafe {
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pl::csr::rtio_crg::pll_reset_write(1);
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pl::csr::rtio_crg::clock_sel_write(clock_sel);
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pl::csr::rtio_crg::pll_reset_write(0);
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}
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timer.delay_ms(1);
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let locked = unsafe { pl::csr::rtio_crg::pll_locked_read() != 0 };
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if locked {
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info!("RTIO PLL locked");
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break;
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} else {
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warn!("RTIO PLL failed to lock, retrying...");
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timer.delay_ms(500);
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}
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2020-07-08 19:58:13 +08:00
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}
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2020-04-11 22:24:23 +08:00
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2020-04-26 11:51:21 +08:00
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unsafe {
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pl::csr::rtio_core::reset_phy_write(1);
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}
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2020-07-08 19:58:13 +08:00
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}
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2020-07-13 16:06:05 +08:00
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fn wait_for_async_rtio_error() -> nb::Result<(), Void> {
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unsafe {
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if pl::csr::rtio_core::async_error_read() != 0 {
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Ok(())
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} else {
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Err(nb::Error::WouldBlock)
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}
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}
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}
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async fn report_async_rtio_errors() {
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loop {
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let _ = block_async!(wait_for_async_rtio_error()).await;
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unsafe {
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let errors = pl::csr::rtio_core::async_error_read();
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if errors & 1 != 0 {
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error!("RTIO collision involving channel {}",
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pl::csr::rtio_core::collision_channel_read());
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}
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if errors & 2 != 0 {
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error!("RTIO busy error involving channel {}",
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pl::csr::rtio_core::busy_channel_read());
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}
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if errors & 4 != 0 {
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error!("RTIO sequence error involving channel {}",
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pl::csr::rtio_core::sequence_error_channel_read());
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}
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pl::csr::rtio_core::async_error_write(errors);
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}
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}
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}
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2020-07-13 14:59:56 +08:00
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static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17];
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2020-07-08 19:58:13 +08:00
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#[no_mangle]
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pub fn main_core0() {
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2020-07-23 05:58:55 +08:00
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let mut timer = GlobalTimer::start();
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2020-07-13 14:59:56 +08:00
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let buffer_logger = unsafe {
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logger::BufferLogger::new(&mut LOG_BUFFER[..])
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};
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buffer_logger.set_uart_log_level(log::LevelFilter::Debug);
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buffer_logger.register();
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2020-07-08 19:58:13 +08:00
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log::set_max_level(log::LevelFilter::Debug);
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2020-07-13 14:59:56 +08:00
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2020-07-08 19:58:13 +08:00
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info!("NAR3/Zynq7000 starting...");
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2020-08-04 10:15:57 +08:00
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ram::init_alloc_core0();
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2020-08-18 01:17:15 +08:00
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gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts();
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2020-07-08 19:58:13 +08:00
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init_gateware();
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info!("detected gateware: {}", identifier_read(&mut [0; 64]));
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2020-09-01 14:43:16 +08:00
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let cfg = match Config::new() {
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2020-07-08 19:24:26 +08:00
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Ok(cfg) => cfg,
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Err(err) => {
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warn!("config initialization failed: {}", err);
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2020-09-01 14:43:16 +08:00
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Config::new_dummy()
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2020-07-08 19:24:26 +08:00
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}
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};
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2020-07-08 19:58:13 +08:00
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2020-07-23 05:58:55 +08:00
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init_rtio(&mut timer, &cfg);
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2020-07-13 16:06:05 +08:00
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task::spawn(report_async_rtio_errors());
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2020-07-08 19:58:13 +08:00
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2020-07-08 19:24:26 +08:00
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comms::main(timer, &cfg);
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2020-04-11 20:19:39 +08:00
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}
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