occheung

occheung pushed to master at sinara-hw/datasheets

2022-07-26 13:11:46 +08:00

7d993a4800 2238: remove min input edge rate

77d31568b1 5108: specify noise in RMS

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occheung commented on issue sinara-hw/datasheets#52

2022-07-26 13:10:26 +08:00

5108 ADC Sampler Noise spec units

Should be RMS.

occheung commented on issue sinara-hw/datasheets#48

2022-07-26 10:43:16 +08:00

2238 MCX-TTL Input edge rate

It implies the input waveform can have ideal edges. I think this spec is only meant to state that the rate has to be faster than a certain threshold (reciprocal of the maximum). Discussing ideal…

occheung commented on issue sinara-hw/datasheets#46

2022-07-25 17:41:48 +08:00

Sampler input with termination enabled shall never exceed 5V regardless of gain setting

Removed the gain setting condition in df564d2. It should be obvious enough that input should be limited to +-5V for other gain settings when there are stricter bounds in the spec.

occheung closed issue sinara-hw/datasheets#41

2022-07-25 17:38:24 +08:00

document Urukul nonlinearity

occheung closed issue sinara-hw/datasheets#45

2022-07-25 17:37:30 +08:00

change "expected" to "ideal" in Urukul Fig 6

occheung commented on issue sinara-hw/datasheets#45

2022-07-25 17:37:27 +08:00

change "expected" to "ideal" in Urukul Fig 6

Fixed in b8e89f4.

occheung commented on issue sinara-hw/datasheets#44

2022-07-25 17:36:09 +08:00

Clocker "rise time" spec is likely incorrect

Removed in a14aa89. The rise time from -400 mV to +400 mV is estimated to be ~100 ps in the testing thread. But there aren't any good plot there (except a blurry plot with the cursors not at the…

occheung commented on issue sinara-hw/datasheets#43

2022-07-25 17:31:32 +08:00

Clocker has no "differential" signals

5d8dc38. Removed the "differential" wording from the spec.

occheung closed issue sinara-hw/datasheets#42

2022-07-25 17:29:45 +08:00

clocker can drive Phaser as well

occheung pushed to master at sinara-hw/datasheets

2022-07-25 17:29:45 +08:00

df564d2375 5108: remove gain condition for terminated voltage spec

b8e89f4d01 4410/linearity: expected -> ideal

8138e793d7 7210: cite waveform plot

a14aa89a76 7210: fix specs

5d8dc38db7 7210: clarify on clock in/out format

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occheung pushed to master at sinara-hw/datasheets

2022-07-22 17:50:17 +08:00

3a6ed63f0a 2118-2128: add RTIO constraint

occheung created pull request M-Labs/zynq-rs#99

2022-07-20 16:52:33 +08:00

szl: change CPU frequency of Kasli-SoC to 1 GHz

occheung pushed to master at occheung/zynq-rs

2022-07-20 15:18:37 +08:00

043a152b91 szl: change CPU frequency of Kasli-SoC to 1 GHz

occheung pushed to fix_clk_freq at occheung/zynq-rs

2022-07-20 15:16:29 +08:00

043a152b91 szl: change CPU frequency of Kasli-SoC to 1 GHz

occheung created branch fix_clk_freq in occheung/zynq-rs

2022-07-20 15:16:29 +08:00

occheung created repository occheung/zynq-rs

2022-07-20 15:12:58 +08:00

occheung pushed to master at sinara-hw/datasheets

2022-06-24 11:31:45 +08:00

c1388a53a8 4410: remove dead titles

af0fca61e2 4410: replot voltage measured vs expected

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occheung commented on issue sinara-hw/datasheets#41

2022-06-23 17:02:36 +08:00

document Urukul nonlinearity

6d9faa7b Added plots to demonstrate the impact of attenuation on linearity. Chose 15dB attenuation just for consistency with the SU-Servo example, which chose 15dB attenuation to maintain…

occheung pushed to master at sinara-hw/datasheets

2022-06-23 16:58:25 +08:00

6d9faa7bb9 4410: add asf vs v_rms