forked from M-Labs/zynq-rs
120 lines
3.3 KiB
Rust
120 lines
3.3 KiB
Rust
#[allow(unused)]
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use crate::{register, register_bit, register_bits, register_at, regs::RegisterW, regs::RegisterRW};
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pub enum PllSource {
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IoPll = 0b00,
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ArmPll = 0b10,
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DdrPll = 0b11,
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}
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pub fn with_slcr<F: FnMut() -> R, R>(mut f: F) -> R {
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unsafe { SlcrUnlock::new() }.unlock();
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let r = f();
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unsafe { SlcrLock::new() }.lock();
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r
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}
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register!(slcr_lock, SlcrLock, WO, u32);
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register_bits!(slcr_lock, lock_key, u16, 0, 15);
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register_at!(SlcrLock, 0xF8000004, new);
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impl SlcrLock {
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pub fn lock(&self) {
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unsafe {
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self.write(
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Self::zeroed()
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.lock_key(0x767B)
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);
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}
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}
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}
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register!(slcr_unlock, SlcrUnlock, WO, u32);
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register_bits!(slcr_unlock, unlock_key, u16, 0, 15);
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register_at!(SlcrUnlock, 0xF8000008, new);
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impl SlcrUnlock {
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pub fn unlock(&self) {
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unsafe {
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self.write(
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Self::zeroed()
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.unlock_key(0xDF0D)
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);
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}
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}
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}
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register!(aper_clk_ctrl, AperClkCtrl, RW, u32);
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register_bit!(aper_clk_ctrl, uart1_cpu_1xclkact, 21);
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register_bit!(aper_clk_ctrl, uart0_cpu_1xclkact, 20);
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register_at!(AperClkCtrl, 0xF800012C, new);
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impl AperClkCtrl {
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pub fn enable_uart0(&self) {
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self.modify(|_, w| w.uart0_cpu_1xclkact(true));
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}
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pub fn enable_uart1(&self) {
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self.modify(|_, w| w.uart1_cpu_1xclkact(true));
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}
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}
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register!(uart_clk_ctrl, UartClkCtrl, RW, u32);
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register_bit!(uart_clk_ctrl, clkact0, 0);
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register_bit!(uart_clk_ctrl, clkact1, 1);
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register_bits!(uart_clk_ctrl, divisor, u8, 8, 13);
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register_bits!(uart_clk_ctrl, srcsel, u8, 4, 5);
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register_at!(UartClkCtrl, 0xF8000154, new);
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impl UartClkCtrl {
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pub fn enable_uart0(&self) {
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self.modify(|_, w| {
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// a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14.
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// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
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// c. Enable the UART 0 Reference clock, slcr.UART_CLK_CTRL [CLKACT0] = 1.
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w.divisor(0x14)
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.srcsel(PllSource::IoPll as u8)
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.clkact0(true)
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})
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}
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pub fn enable_uart1(&self) {
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self.modify(|_, w| {
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// a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14.
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// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
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// c. Enable the UART 1 Reference clock, slcr.UART_CLK_CTRL [CLKACT1] = 1.
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w.divisor(0x14)
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.srcsel(PllSource::IoPll as u8)
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.clkact1(true)
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})
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}
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}
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register!(uart_rst_ctrl, UartRstCtrl, RW, u32);
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register_bit!(uart_rst_ctrl, uart0_ref_rst, 3);
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register_bit!(uart_rst_ctrl, uart1_ref_rst, 2);
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register_bit!(uart_rst_ctrl, uart0_cpu1x_rst, 1);
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register_bit!(uart_rst_ctrl, uart1_cpu1x_rst, 0);
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register_at!(UartRstCtrl, 0xF8000228, new);
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impl UartRstCtrl {
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pub fn reset_uart0(&self) {
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self.modify(|_, w|
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w.uart0_ref_rst(true)
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.uart0_cpu1x_rst(true)
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);
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self.modify(|_, w|
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w.uart0_ref_rst(false)
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.uart0_cpu1x_rst(false)
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);
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}
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pub fn reset_uart1(&self) {
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self.modify(|_, w|
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w.uart1_ref_rst(true)
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.uart1_cpu1x_rst(true)
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);
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self.modify(|_, w|
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w.uart1_ref_rst(false)
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.uart1_cpu1x_rst(false)
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);
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}
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}
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