forked from M-Labs/zynq-rs
boot: prepare core1 bootup
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parent
4a1d0fc0c3
commit
49901d1b8a
39
src/boot.rs
39
src/boot.rs
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@ -1,6 +1,7 @@
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use r0::zero_bss;
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use r0::zero_bss;
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use crate::regs::{RegisterR, RegisterW};
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use crate::regs::{RegisterR, RegisterW};
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use crate::cortex_a9::{asm, regs::*, mmu};
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use crate::cortex_a9::{asm, regs::*, mmu};
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use crate::zynq::mpcore;
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extern "C" {
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extern "C" {
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static mut __bss_start: u32;
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static mut __bss_start: u32;
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@ -8,6 +9,8 @@ extern "C" {
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static mut __stack_start: u32;
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static mut __stack_start: u32;
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}
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}
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static mut CORE1_STACK: u32 = 0;
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#[link_section = ".text.boot"]
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[no_mangle]
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#[naked]
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#[naked]
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@ -19,10 +22,19 @@ pub unsafe extern "C" fn _boot_cores() -> ! {
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SP.write(&mut __stack_start as *mut _ as u32);
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SP.write(&mut __stack_start as *mut _ as u32);
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boot_core0();
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boot_core0();
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}
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}
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_ => loop {
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1 => {
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// if not core0, infinitely wait for events
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// Wait for a first `sev` so that `CORE1_STACK` is cleared
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// by `zero_bss()` on core 0.
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asm::wfe();
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asm::wfe();
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},
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while CORE1_STACK == 0 {
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asm::wfe();
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}
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SP.write(CORE1_STACK);
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boot_core1();
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}
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_ => unreachable!(),
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}
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}
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}
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}
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@ -30,16 +42,37 @@ pub unsafe extern "C" fn _boot_cores() -> ! {
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#[inline(never)]
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#[inline(never)]
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unsafe fn boot_core0() -> ! {
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unsafe fn boot_core0() -> ! {
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l1_cache_init();
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l1_cache_init();
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let mpcore = mpcore::RegisterBlock::new();
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mpcore.scu_invalidate.invalidate_all_cores();
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zero_bss(&mut __bss_start, &mut __bss_end);
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zero_bss(&mut __bss_start, &mut __bss_end);
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let mmu_table = mmu::L1Table::get()
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let mmu_table = mmu::L1Table::get()
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.setup_flat_layout();
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.setup_flat_layout();
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mmu::with_mmu(mmu_table, || {
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mmu::with_mmu(mmu_table, || {
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mpcore.scu_control.start();
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crate::main();
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crate::main();
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panic!("return from main");
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panic!("return from main");
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});
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});
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}
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}
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#[naked]
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#[inline(never)]
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unsafe fn boot_core1() -> ! {
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l1_cache_init();
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let mpcore = mpcore::RegisterBlock::new();
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mpcore.scu_invalidate.invalidate_core1();
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let mmu_table = mmu::L1Table::get();
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mmu::with_mmu(mmu_table, || {
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crate::main_core1();
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panic!("return from main_core1");
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});
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}
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fn l1_cache_init() {
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fn l1_cache_init() {
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use crate::cortex_a9::cache::*;
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use crate::cortex_a9::cache::*;
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@ -10,6 +10,12 @@ pub fn wfe() {
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unsafe { asm!("wfe" :::: "volatile") }
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unsafe { asm!("wfe" :::: "volatile") }
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}
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}
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/// Send Event
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#[inline]
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pub fn sev() {
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unsafe { asm!("sev" :::: "volatile") }
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}
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/// Data Memory Barrier
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/// Data Memory Barrier
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#[inline]
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#[inline]
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pub fn dmb() {
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pub fn dmb() {
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@ -1,14 +1,15 @@
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///! Register definitions for Application Processing Unit (mpcore)
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///! Register definitions for Application Processing Unit (mpcore)
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use volatile_register::{RO, RW, WO};
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use volatile_register::{RO, RW};
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use crate::{register, register_at, register_bit};
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use crate::{register, register_at, register_bit, register_bits,
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regs::RegisterW, regs::RegisterRW};
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#[repr(C)]
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#[repr(C)]
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pub struct RegisterBlock {
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pub struct RegisterBlock {
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pub scu_control: ScuControl,
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pub scu_control: ScuControl,
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pub scu_config: RO<u32>,
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pub scu_config: RO<u32>,
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pub scu_cpu_power: RW<u32>,
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pub scu_cpu_power: RW<u32>,
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pub scu_invalidate: WO<u32>,
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pub scu_invalidate: ScuInvalidate,
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reserved0: [u32; 12],
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reserved0: [u32; 12],
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pub filter_start: RW<u32>,
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pub filter_start: RW<u32>,
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pub filter_end: RW<u32>,
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pub filter_end: RW<u32>,
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@ -27,3 +28,32 @@ register_bit!(scu_control, scu_speculative_linefill_enable, 3);
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register_bit!(scu_control, scu_rams_parity_enable, 2);
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register_bit!(scu_control, scu_rams_parity_enable, 2);
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register_bit!(scu_control, address_filtering_enable, 1);
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register_bit!(scu_control, address_filtering_enable, 1);
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register_bit!(scu_control, enable, 0);
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register_bit!(scu_control, enable, 0);
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impl ScuControl {
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pub fn start(&mut self) {
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self.modify(|_, w| w.enable(true));
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}
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}
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register!(scu_invalidate, ScuInvalidate, WO, u32);
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register_bits!(scu_invalidate, cpu0_ways, u8, 0, 3);
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register_bits!(scu_invalidate, cpu1_ways, u8, 4, 7);
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register_bits!(scu_invalidate, cpu2_ways, u8, 8, 11);
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register_bits!(scu_invalidate, cpu3_ways, u8, 12, 15);
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impl ScuInvalidate {
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pub fn invalidate_all_cores(&mut self) {
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self.write(ScuInvalidate::zeroed()
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.cpu0_ways(0xf)
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.cpu1_ways(0xf)
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.cpu2_ways(0xf)
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.cpu3_ways(0xf)
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);
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}
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pub fn invalidate_core1(&mut self) {
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self.write(ScuInvalidate::zeroed()
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.cpu1_ways(0xf)
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);
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}
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}
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