add Kasli-SOC

config.toml

@@ -3,9 +3,11 @@ title = "M-Labs"
 description = "Open tools for open physics."
 
 compile_sass = true
-highlight_code = true
 insert_anchor_links = true
 build_search_index = false
 
+[markdown]
+highlight_code = true
+
 [extra]
 author = "M-Labs"

content/about-us/company.md

@@ -16,7 +16,7 @@ In the summer of 2007, Sébastien Bourdeauducq, while a student at <a href="http
 
 Components of the Milkymist SoC soon found many other uses, such as <a href="/images/jpl_letter.jpg" target="_blank" rel="noopener noreferrer">software-defined radio</a> on board the International Space Station. The community grew and activities diversified, with the development of a <a href="http://www.ohwr.org/projects/tdc-core/wiki" target="_blank" rel="noopener noreferrer">TDC core</a> for CERN (using a variant of the Milkymist SoC for integration), the <a href="/gateware/migen/">Migen</a> logic design system and its application to the Rhino software-defined radio platform, and the <a href="/other/mixxeo">Mixxeo</a> digital video mixer. In 2013, Milkymist was renamed to M-Labs to match the more varied activities, and formally incorporated as M-Labs Limited.
 
-Since 2014, the company's main project is <a href="/experiment-control/artiq/">ARTIQ</a>, a leading-edge open source control system for quantum information experiments. In 2016, Robert Jördens joined the directorate of the company to further develop ARTIQ and other physics-related projects. Commercial hardware developed specifically for ARTIQ, codenamed Sinara, started appearing in 2017.
+Since 2014, the company's main project is <a href="/experiment-control/artiq/">ARTIQ</a>, a leading-edge open source control system for quantum information experiments. In 2016, Robert Jördens joined the directorate of the company to further develop ARTIQ and other physics-related projects. Commercial hardware developed specifically for ARTIQ, codenamed Sinara, started appearing in 2017 thanks to a collaboration with Grzegorz Kasprowicz from the Warsaw Insitute of Technology.
 
 Over 200 major quantum physics experiments have been relying on ARTIQ as their main control and data acquisition system.
 

content/experiment-control/publications.md

@@ -59,9 +59,15 @@ template = "page.html"
 - **Precise PID controller for quantum applications**<br />
   Jakub Matyas<br />
   [Warsaw University of Technology, Engineer's thesis](https://repo.pw.edu.pl/info/bachelor/WUTe90de3461b53456c9d63c55d80d34220/) | [local copy](/JMatyas_inz_v6.pdf)
+- **Controller module for real-time quantum applications**<br />
+  Paweł Kulik<br />
+  [Warsaw University of Technology, Masters's diploma thesis](https://repo.pw.edu.pl/info/master/WUT6212c3c3cdcd40ea9095f4ead6482596/) | [local copy](/pawel_kulik_kasli_thesis_2019_compressed.pdf)
 - **Driver module for quantum computer experiments: Kasli**<br />
   Paweł Kulik, Grzegorz Kasprowicz and Michał Gąska<br />
   [Proceedings Volume 10808, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2018](https://doi.org/10.1117/12.2501709) | [slides](https://raw.githubusercontent.com/wiki/sinara-hw/meta/talks/pawel_kasli_mgr2.pdf)
+- **Control system for ion Penning traps at the AEgIS experiment at CERN**<br />
+  Dorota Nowicka<br />
+  [TIPP 2021 Poster](https://indico.cern.ch/event/981823/contributions/4295432/attachments/2250078/3816845/poster_445.pdf)
 - **Sayma: Agile RF for Coherent Quantum Control Using ARTIQ**<br />
    Joseph W. Britton, David T. C. Allcock, Chris Ballance, Tom P. Harty, Robert Jordens, Greg Kasprowicz, Pawel Kulik, Daniel H. Slichter, Weida Zhang, Sebastien Bourdeauducq<br />
    APS Division of Atomic and Molecular Physics Meeting 2019, abstract id.E01.164

content/experiment-control/resources.md

@@ -78,9 +78,9 @@ template = "page.html"
 
 
 {% layout_card(src="images/irc@2x.png", css="col-12 col-md-4 text-center") %}
-<a href="https://webchat.freenode.net/" target="_blank" rel="noopener noreferrer">IRC: #m-labs</a>
+<a href="https://webchat.oftc.net/" target="_blank" rel="noopener noreferrer">IRC: #m-labs</a>
 
-<small>on Freenode</small>
+<small>on OFTC</small>
 {% end %}
 
 

content/experiment-control/sinara-core.md

@@ -30,9 +30,15 @@ One of the main devices in the Sinara family is the 1124 Carrier (codenamed Kasl
 
 {% end %}
 
+{% layout_text_img(src="images/kasli-soc@2x.png", popup="images/origin/kasli-soc.jpg", alt="", textleft=true, shadow=false) %}
 
+##### Sinara 1125 Carrier "Kasli-SoC"
 
-{% layout_text_img(src="images/isolated-ttl@2x.png", popup="images/origin/dio.jpg", alt="", textleft=true, shadow=false) %}
+Based on a Zynq-7000 SoC, Kasli-SoC can execute kernels on a 1GHz CPU with a hardware FPU. This enables much heavier software computations to be performed on the core device with a low-latency path to the experiment. Network transfer rates are also greatly increased. Features are otherwise similar as Kasli's.
+
+{% end %}
+
+{% layout_text_img(src="images/isolated-ttl@2x.png", popup="images/origin/dio.jpg", alt="", shadow=false) %}
 
 ##### Sinara 2118/2128/2138 8-channel isolated TTL cards
 
@@ -42,7 +48,7 @@ More information: <a href="https://github.com/sinara-hw/DIO_BNC/wiki" target="_b
 
 {% end %}
 
-{% layout_text_img(src="images/DIOMCX@2x.png", popup="images/origin/dio_mcx.jpg", alt="", shadow=false) %}
+{% layout_text_img(src="images/DIOMCX@2x.png", popup="images/origin/dio_mcx.jpg", alt="", textleft=true, shadow=false) %}
 
 ##### Sinara 2238 16-channel non-isolated MCX TTL card
 
@@ -54,7 +60,7 @@ When higher densities or faster speeds are required, the Sinara 2238 MCX card is
 
 
 
-{% layout_text_img(src="images/LVDS@2x.png", popup="images/origin/dio_rj45.jpg", alt="", textleft=true, shadow=false) %}
+{% layout_text_img(src="images/LVDS@2x.png", popup="images/origin/dio_rj45.jpg", alt="", shadow=false) %}
 
 
 ##### Sinara 2245 16-channel non-isolated LVDS RJ45 TTL card
@@ -68,7 +74,7 @@ Each RJ45 supplies 4 LVDS DIOs. The direction (input/output) is individually sel
 
 
 
-{% layout_text_img(src="images/Banker-TTL-1@2x.png", popup="images/origin/banker1.jpg", alt="", shadow=false) %}
+{% layout_text_img(src="images/Banker-TTL-1@2x.png", popup="images/origin/banker1.jpg", alt="", textleft=true, shadow=false) %}
 
 ##### Sinara 3128 TTL I/O expander "Banker"
 
@@ -84,7 +90,7 @@ Interfaces include:
 
 
 
-{% layout_text_img(src="images/Banker-TTL-2@2x.png", popup="images/origin/banker2.jpg", alt="", textleft=true, shadow=false) %}
+{% layout_text_img(src="images/Banker-TTL-2@2x.png", popup="images/origin/banker2.jpg", alt="", shadow=false) %}
 
 All outputs can be configured either as 3.3 or 5V. They can drive 50&#8486; load when set to 5V. FPGA can is configured from on-board FLASH. FLASH can be updated over I2C or with the on-board SPI connector.
 
@@ -105,7 +111,7 @@ There are several DIN-rail compatible modules for use with Banker. They are inte
 
 
 
-{% layout_text_img(src="images/Urukul-DDS@2x.png", popup="images/origin/urukul.jpg", alt="", shadow=false) %}
+{% layout_text_img(src="images/Urukul-DDS@2x.png", popup="images/origin/urukul.jpg", alt="", textleft=true, shadow=false) %}
 
 ##### Sinara 4410/4412 DDS "Urukul"
 
@@ -121,7 +127,7 @@ In regular mode, various DDS features are supported, including frequency, phase
 
 
 
-{% layout_text_img(src="images/Mirny-Synth@2x.png", popup="images/origin/mirny.jpg", alt="", textleft=true, shadow=false) %}
+{% layout_text_img(src="images/Mirny-Synth@2x.png", popup="images/origin/mirny.jpg", alt="", shadow=false) %}
 
 ##### Sinara 4456 synthesizer "Mirny"
 
@@ -145,7 +151,7 @@ Comparing Mirny to Urukul:
 
 
 
-{% layout_text_img(src="images/Zotino-DAC@2x.png", popup="images/origin/zotino.jpg", alt="", shadow=false) %}
+{% layout_text_img(src="images/Zotino-DAC@2x.png", popup="images/origin/zotino.jpg", alt="", textleft=true, shadow=false) %}
 
 ##### Sinara 5432 DAC "Zotino"
 
@@ -155,6 +161,8 @@ Zotino connects the 32 channels to both (a) a HD68 connector on its front panel
 
 It is also possible to connect the Zotino using a HD68 cable to an external crate containing BNC-IDC or SMA-IDC cards.
 
+The temperature of the DAC can be stabilized using the [Sinara 8451 Thermostat](../control-loops) to reduce output voltage drifts.
+
 <a href="https://github.com/sinara-hw/Zotino/wiki" target="_blank" rel="noopener noreferrer">More information</a>
 
 ##### Sinara 5632 DAC "Fastino"
@@ -169,7 +177,7 @@ Note that reaching this maximum hardware speed requires gateware acceleration; n
 
 
 
-{% layout_text_img(src="images/Sampler-ADC@2x.png", popup="images/origin/sampler.jpg", alt="", textleft=true, shadow=false) %}
+{% layout_text_img(src="images/Sampler-ADC@2x.png", popup="images/origin/sampler.jpg", alt="", shadow=false) %}
 
 ##### Sinara 5108 Sampler
 
@@ -185,7 +193,7 @@ Note that update rate specification on this page is for the hardware only; ARTIQ
 
 
 
-{% layout_text_img(src="images/Grabber-camera-interface@2x.png", popup="images/origin/grabber.jpg", alt="", shadow=false) %}
+{% layout_text_img(src="images/Grabber-camera-interface@2x.png", popup="images/origin/grabber.jpg", alt="", textleft=true, shadow=false) %}
 
 ##### Sinara 6302 Grabber
 
@@ -199,7 +207,7 @@ In the FPGA, frame data streamed through "ROI engines". Each ROI engine gates on
 
 
 
-{% layout_text_img(src="images/clocker@2x.png", popup="images/origin/clocker.jpg", alt="", textleft=true, shadow=false) %}
+{% layout_text_img(src="images/clocker@2x.png", popup="images/origin/clocker.jpg", alt="", shadow=false) %}
 
 ##### Sinara 7210 Clocker
 
@@ -210,7 +218,7 @@ The Sinara 7210 is a low-noise clock distribution module that can be used to dis
 {% end %}
 
 
-{% layout_text_img(src="images/phaser@2x.png", popup="images/origin/phaser.jpg", alt="", shadow=false) %}
+{% layout_text_img(src="images/phaser@2x.png", popup="images/origin/phaser.jpg", alt="", textleft=true, shadow=false) %}
 
 ##### Sinara 4624 AWG "Phaser"
 

static/js/shop_data.js

@@ -114,7 +114,6 @@ const shop_data = {
         '4 SFP 12Gb/s slots for DRTIO.',
         '12 EEM connectors.',
         '4 MMCX clock outputs.',
-        'WARNING: early access card. Price and specifications may be subject to change. Long lead time.',
       ],
       size: 'big',
       type: 'kasli',
@@ -430,7 +429,8 @@ const shop_data = {
         '1 MSPS shared between all channels.',
         'Output voltage +-10V.',
         'HD68 connector with all channels.',
-        'Channels can also be broken out to BNC or SMA using IDC-BNC, IDC-SMA or IDC-MCX cards.'
+        'Channels can also be broken out to BNC or SMA using IDC-BNC, IDC-SMA or IDC-MCX cards.',
+        'DAC temperature can be stabilized using the Sinara 8451 Thermostat (sold separately).'
       ],
       size: 'small',
       type: 'zotino',

templates/includes/footer_contact_direction.html

@@ -15,7 +15,7 @@
     <h5 class="pb-3">Technical inquiries</h5>
 
     <p>
-      Ask on the <a href="https://chat.m-labs.hk/" target="_blank" rel="noopener noreferrer">live chat room</a> (bridged to the IRC channel #m-labs on Freenode), or go to <a href="https://forum.m-labs.hk/" rel="noopener noreferrer" target="_blank">forum.m-labs.hk</a>, a place to discuss all things ARTIQ, (n)Migen, MiSoC and HeavyX with the community. If you prefer contacting us privately, use the sales@m-***s.hk email.
+      Ask on the <a href="https://chat.m-labs.hk/" target="_blank" rel="noopener noreferrer">live chat room</a> (bridged to the IRC channel #m-labs on OFTC), or go to <a href="https://forum.m-labs.hk/" rel="noopener noreferrer" target="_blank">forum.m-labs.hk</a>, a place to discuss all things ARTIQ, (n)Migen, MiSoC and HeavyX with the community. If you prefer contacting us privately, use the sales@m-***s.hk email.
     </p>
 
   </div>