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@@ -28,7 +28,7 @@ ARTIQ was initiated by the [Ion Storage Group](https://www.nist.gov/pml/time-and
 
 The [University of Oxford](https://www2.physics.ox.ac.uk/research/ion-trap-quantum-computing-group) funded major improvements to the RTIO infrastructure: the Distributed RTIO (DRTIO) system that allows clock synchronization and RTIO command transfer between FPGAs using cost-effective high-speed serial links (e.g. over fiber optics), and changes to the RTIO architecture to improve scalability. They also funded the Sinara Sampler hardware and software, the [SU-Servo](https://m-labs.hk/artiq/manual-beta/core_drivers_reference.html?highlight=suservo#artiq.coredevice.suservo.SUServo) integrated laser intensity servo, parts of Urukul and Zotino, firmware development on the Sinara Thermostat, the Kasli v2.0 ARTIQ support, the Fastino ARTIQ support, parts of the Sinara Phaser gateware and software development, and significant parts of the Booster RF amplifier.
 
-[![logo ise](/images/logo_ise.png)](http://www.ise.pw.edu.pl)
+[![logo wut](/images/logo_wut.png)](http://www.ise.pw.edu.pl)
 
 [Warsaw University of Technology](http://www.ise.pw.edu.pl) contributed most of the hardware designs and prototypes for the Sinara ecosystem.
 
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