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add Kasli-SoC links

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Sebastien Bourdeauducq 2023-03-12 09:31:48 +08:00
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content/experiment-control/sinara-core.md
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@ -36,6 +36,10 @@ One of the main devices in the Sinara family is the 1124 Carrier (codenamed Kasl
Based on a Zynq-7000 SoC, Kasli-SoC can execute kernels on a 1GHz CPU with a hardware FPU. This enables much heavier software computations to be performed on the core device with a low-latency path to the experiment. Network transfer rates are also greatly increased. Features are otherwise similar as Kasli's.
See our paper <a href="https://arxiv.org/abs/2111.15290" target="_blank" rel="noopener noreferrer">Combining processing throughput, low latency and timing accuracy in experiment control</a> for information about what Kasli-SoC enables compared to previous ARTIQ platforms.
<a href="https://github.com/sinara-hw/Kasli-SoC/wiki" target="_blank" rel="noopener noreferrer">More information</a>
{% end %}
{% layout_text_img(src="images/isolated-ttl@2x.png", popup="images/origin/dio.jpg", alt="", shadow=false) %}