Go to file

Robert Jördens 70852006eb cfg: add div to configure clock divider

Keeping the two bits at 0 will ensure backwards compatible default operation.
Other settings force the divider to the respective value.

* 0: en_ad9910: divide-by-4, ~en_ad9910: divide-by-1
* 1: divide-by-1
* 2: divide-by-2
* 3: divide-by-4

c.f. #3

2019-01-15 10:18:04 +00:00

.gitignore

init

2017-09-03 20:34:40 +02:00

flash_xc3.sh

flash: increase sleep

2018-10-09 15:17:08 +00:00

flash.cmd

fix flashing

2017-12-12 11:24:35 +00:00

flash.sh

[WIP, untested] add some flash script stubs

2017-12-12 11:47:13 +01:00

LICENSE.GPL-3

license

2018-10-17 15:31:45 +02:00

Makefile

add tests

2017-10-27 18:53:27 +02:00

README.md

license

2018-10-17 15:31:45 +02:00

urukul_cpld.py

urukul/v1.3 changes: add osc_en_n and mmcx_osc_sel

2018-10-09 17:11:27 +02:00

urukul_impl.py

add forgotten file

2017-12-12 11:25:20 +01:00

urukul_sim.py

test: fix somewhat

2018-10-17 15:32:24 +02:00

urukul.py

cfg: add div to configure clock divider

2019-01-15 10:18:04 +00:00

README.md

Urukul CPLD code

Urukul overview

Urukul Schematics

NU-Servo

Building

Needs migen and ISE.

make
# and then look at/use flash.sh or make flash

# or use fxload and xc3sprog:
/sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-3/devnum` && sleep 10 && \
xc3sprog -c xpc -m /opt/Xilinx/14.7/ISE_DS/ISE/xbr/data -v build/urukul.jed:w
# look for "Verify: Success"

License

GPLv3+