hartytp fccf64d392 urukul/v1.3 changes: add osc_en_n and mmcx_osc_sel
* tp3 and tp4 connected to mmcx_osc_sel and osc_en_n in hardware
    * improve docs
2018-10-09 17:11:27 +02:00
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2018-03-07 18:45:16 +00:00
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2018-02-12 14:02:43 +00:00
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Urukul CPLD code

Urukul overview

Urukul Schematics

NU-Servo

Building

Needs migen and ISE.

make
# and then look at/use flash.sh or make flash

# or use fxload and xc3sprog:
/sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-3/devnum` && sleep 10 && \
xc3sprog -c xpc -m /opt/Xilinx/14.7/ISE_DS/ISE/xbr/data -v build/urukul.jed:w
# look for "Verify: Success"
Description
CPLD/FPGA gateware on Urukul. Forked from https://github.com/quartiq/urukul
Readme 573 KiB
Languages
Python 97.4%
Makefile 1.3%
Shell 0.8%
Batchfile 0.5%