forked from M-Labs/urukul-pld
123 lines
3.5 KiB
Python
123 lines
3.5 KiB
Python
from collections import namedtuple
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from migen import *
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from migen.fhdl.specials import Tristate
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from migen.build.generic_platform import ConstraintError
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from urukul import Urukul
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from urukul_cpld import Platform
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class SimTristate:
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@staticmethod
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def lower(dr):
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return SimTristateImpl(dr.i, dr.o, dr.oe, dr.target)
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class SimTristateImpl(Module):
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def __init__(self, i, o, oe, target):
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self.i = i
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self.o = o
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self.oe = oe
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self.target = target
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self.comb += [
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# If(oe, target.eq(o)),
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# i.eq(Mux(oe, o, target))
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i.eq(target)
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]
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class SimInstance:
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@staticmethod
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def lower(dr):
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return Module()
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class TB(Module):
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def __init__(self, platform, dut):
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self.platform = platform
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self.submodules.dut = dut
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for k in "tp dds dds_common dds_sync clk ifc_mode att eem".split():
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v = []
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while True:
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try:
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v.append(platform.lookup_request(k, len(v)))
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except ConstraintError:
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break
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if len(v) == 1:
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v = v[0]
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setattr(self, k, v)
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self.cs = Signal(3)
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self.comb += [
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Cat(self.eem[3].io, self.eem[4].io, self.eem[5].io).eq(
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self.cs)
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]
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def spi(self, cs, n, mosi):
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# while (yield self.dut.cd_sck0.clk):
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# pass
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yield self.cs.eq(cs)
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miso = 0
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for i in range(n - 1, -1, -1):
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yield self.eem[1].io.eq((mosi >> i) & 1)
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yield self.eem[0].io.eq(0)
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yield
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yield self.eem[0].io.eq(1)
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# miso = (miso << 1) | (yield self.eem[2].io)
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miso = (miso << 1) | (yield self.dut.eem[2].o)
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yield
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yield self.eem[0].io.eq(0)
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yield
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yield self.cs.eq(0)
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yield
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yield
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yield
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return miso
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def test(self):
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p = self.platform
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dut = self.dut
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yield self.ifc_mode[0].eq(1) # en_9910
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yield self.ifc_mode[1].eq(0) # en_nu
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yield self.ifc_mode[2].eq(1) # en_eemb
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yield self.eem[12].io.eq(1) # rf_sw[0]
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yield self.dds[1].smp_err.eq(1)
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yield self.dds[0].pll_lock.eq(1)
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yield
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yield from self.spi(1, 24, 0x123456)
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for i in range(4):
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sw = yield self.dds[i].rf_sw
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assert sw == ((0x6 | 1) >> i) & 1, (i, sw)
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led = yield self.dds[i].led[1]
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assert led == ((0x5 | 0xe | 0x2) >> i) & 1, (i, led)
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profile = yield self.dds_common.profile
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assert profile == 0x4
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att_le = yield self.att.le
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assert att_le == 0
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ret = yield from self.spi(1, 24, 0x123456)
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assert ret & 0xf == 1, hex(ret)
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assert ret & 0xff0000 == 0x050000
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ret = yield from self.spi(1, 24, 0x123456)
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assert ret & 0xf == 0x6 | 1, hex(ret)
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assert ret & 0xff0000 == 0x050000
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yield from self.spi(2, 32, 0xf0f0f0f0) # ATT
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yield from self.spi(4, 16, 0x1234)
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yield from self.spi(3, 8 + 64, 0x12345678abcdef0123)
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yield
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def main():
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p = Platform()
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dut = Urukul(p)
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tb = TB(p, dut)
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run_simulation(tb, [tb.test()], vcd_name="urukul.vcd",
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# just operate on sck0
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clocks={"sys": 8, "sck1": (16, 4), "sck0": (16, 12)},
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special_overrides={Tristate: SimTristate, Instance: SimInstance})
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if __name__ == "__main__":
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main()
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