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Robert Jördens 86f3465fa7 revert cpld gateware to backwards compatible

* to a strictly backwards compatible (to v1.3 proto rev 8) implementation for v1.4 hardware
* exception: OSK (which is high now and was low in v1.3)
* to make the transition to a future v1.4-specific gateware and ARTIQ
  coredevice driver smoother and is a fallback.

close #8

2019-12-17 17:30:28 +00:00

.gitignore

init

2017-09-03 20:34:40 +02:00

flash_xc3.sh

udpdate bus

2019-09-11 12:29:25 +00:00

flash.cmd

fix flashing

2017-12-12 11:24:35 +00:00

flash.sh

[WIP, untested] add some flash script stubs

2017-12-12 11:47:13 +01:00

LICENSE.GPL-3

license

2018-10-17 15:31:45 +02:00

Makefile

add tests

2017-10-27 18:53:27 +02:00

README.md

README: update urls

2019-10-29 10:58:18 +01:00

urukul_cpld.py

urukul v1.4 minimum

2019-08-26 18:36:59 +00:00

urukul_impl.py

add forgotten file

2017-12-12 11:25:20 +01:00

urukul_sim.py

test: fix somewhat

2018-10-17 15:32:24 +02:00

urukul.py

revert cpld gateware to backwards compatible

2019-12-17 17:30:28 +00:00

README.md

Urukul CPLD code

Urukul overview

Urukul Schematics/Layout

NU-Servo

Building

Needs migen and ISE.

make
# and then look at/use flash.sh or make flash

# or use fxload and xc3sprog:
/sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-3/devnum` && sleep 10 && \
xc3sprog -c xpc -m /opt/Xilinx/14.7/ISE_DS/ISE/xbr/data -v build/urukul.jed:w
# look for "Verify: Success"

License

GPLv3+