forked from M-Labs/urukul-pld
532 lines
21 KiB
Python
532 lines
21 KiB
Python
from migen import *
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# increment this if the behavior (LEDs, registers, EEM pins) changes
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__proto_rev__ = 9
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class SR(Module):
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"""
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Shift register, SPI slave
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* CPOL = 0 (clock idle low during ~SEL)
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* CPHA = 0 (sample on first edge, shift on second)
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* SPI mode 0
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* samples SDI on rising clock edges (SCK1 domain)
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* shifts out SDO on falling clock edges (SCK0 domain)
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* MSB first
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* the first output bit (MSB) is undefined
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* the first output bit is available from the start of the SEL cycle until
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the first falling edge
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* the first input bit is sampled on the first rising edge
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* on the first rising edge with SEL assered, the parallel data DO
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is loaded into the shift register
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* following at least one rising clock edge, on the deassertion of SEL,
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the shift register is loaded into the parallel data register DI
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"""
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def __init__(self, width):
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self.sdi = Signal()
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self.sdo = Signal()
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self.sel = Signal()
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self.di = Signal(width)
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self.do = Signal(width)
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# # #
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sr = Signal(width)
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self.clock_domains.cd_le = ClockDomain("le", reset_less=True)
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# clock the latch domain from selection deassertion but only after
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# there was a serial clock edge with asserted select (i.e. ignore
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# glitches).
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self.specials += Instance("FDPE", p_INIT=1,
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i_D=0, i_C=ClockSignal("sck1"), i_CE=self.sel, i_PRE=~self.sel,
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o_Q=self.cd_le.clk)
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self.sync.sck0 += [
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If(self.sel,
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self.sdo.eq(sr[-1]),
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)
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]
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self.sync.sck1 += [
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If(self.sel,
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sr[0].eq(self.sdi),
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If(self.cd_le.clk,
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sr[1:].eq(self.do[:-1])
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).Else(
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sr[1:].eq(sr[:-1])
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)
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)
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]
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self.sync.le += [
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self.di.eq(sr)
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]
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class CFG(Module):
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"""Configuration register
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The configuration register is updated from the SPI shift register on the
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deselection of the CPLD at the end of the SPI transaction.
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The initial state is 0 (all bits cleared).
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The bits in the configuration register (from LSB to MSB) are:
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| Name | Width | Function |
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|-----------+-------+-------------------------------------------------|
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| RF_SW | 4 | Activates RF switch (per channel) |
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| LED | 4 | Activates the red LED (per channel) |
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| PROFILE | 4 * 3 | Controls DDS.PROFILE[0:2] (per channel) |
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| OSK | 4 | Asserts DDS.OSK (per channel) |
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| DRCTL | 4 | Asserts DDS.DRCTL (per channel) |
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| DRHOLD | 4 | Asserts DDS.DRHOLD (per channel) |
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| IO_UPDATE | 4 | Asserts DDS.IO_UPDATE (per channel), where |
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| | | CFG.MASK_NU is high |
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| MASK_NU | 4 | Disables DDS from QSPI interface, disables |
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| | | IO_UPDATE control through IO_UPDATE EEM signal, |
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| | | enables access through CS=3, enables control of |
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| | | IO_UPDATE through CFG.IO_UPDATE[0:3] |
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| CLK_SEL0 | 1 | Selects CLK source: 0 MMCX/OSC, 1 SMA |
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| SYNC_SEL | 1 | Selects SYNC source |
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| RST | 1 | Asserts DDS[0:3].RESET, DDS[0:3].MASTER_RESET, |
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| | | ATT[0:3].RST |
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| IO_RST | 1 | Asserts DDS[0:3].IO_RESET |
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| CLK_SEL1 | 1 | Selects CLK source: 0 OSC, 1 MMCX |
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| DIV | 2 | Clock divider configuration: 0: default, |
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| | | 1: divide-by-one, 2: divider-by-two, |
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| | | 3: divide-by-four |
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| ATT_EN | 4 | Enable ATT (per channel) |
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"""
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def __init__(self, platform, n=4):
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self.data = Record(
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[
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("rf_sw", n),
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("led", n),
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("profile", 3 * n),
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("osk", n),
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("drctl", n),
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("drhold", n),
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("io_update", n),
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("mask_nu", 4),
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("clk_sel0", 1),
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("sync_sel", 1),
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("rst", 1),
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("io_rst", 1),
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("clk_sel1", 1),
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("div", 2),
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("att_en", n),
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]
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)
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dds_common = platform.lookup_request("dds_common")
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dds_sync = platform.lookup_request("dds_sync")
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att = platform.lookup_request("att")
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clk = platform.lookup_request("clk")
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self.en_9910 = Signal()
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self.comb += [
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clk.in_sel.eq(self.data.clk_sel0),
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clk.mmcx_osc_sel.eq(self.data.clk_sel1),
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clk.osc_en_n.eq(clk.in_sel | clk.mmcx_osc_sel),
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dds_sync.sync_sel.eq(self.data.sync_sel),
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dds_common.master_reset.eq(self.data.rst),
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dds_common.io_reset.eq(self.data.io_rst),
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att.rst_n.eq(~self.data.rst),
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]
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for i in range(n):
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sw = platform.request("eem", 12 + i)
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dds = platform.lookup_request("dds", i)
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self.comb += [
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sw.oe.eq(0),
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dds.rf_sw.eq(sw.io | self.data.rf_sw[i]),
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dds.led[0].eq(dds.rf_sw), # green
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dds.led[1].eq(self.data.led[i] | (self.en_9910 & (
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dds.smp_err | ~dds.pll_lock))), # red
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dds.profile.eq(self.data.profile[3 * i : 3 * i + 3]),
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dds.osk.eq(self.data.osk[i]),
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dds.drhold.eq(self.data.drhold[i]),
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dds.drctl.eq(self.data.drctl[i]),
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]
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class Status(Module):
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"""Status register.
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The status data is loaded into the SPI shift register on the first
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rising SCK edge while the CPLD is selected. The bits from LSB to MSB
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are:
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| Name | Width | Function |
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|-----------+-------+-------------------------------------------|
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| RF_SW | 4 | Actual RF switch and green LED activation |
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| | | (including that by EEM1.SW[0:3]) |
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| SMP_ERR | 4 | DDS.SMP_ERR per channel |
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| PLL_LOCK | 4 | DDS.PLL_LOCK per channel |
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| IFC_MODE | 4 | IFC_MODE[0:3] |
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| PROTO_REV | 7 | Protocol revision (see __proto_rev__) |
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| DROVER | 4 | DDS.DROVER per channel |
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"""
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def __init__(self, platform, n=4):
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self.data = Record(
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[
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("rf_sw", n),
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("smp_err", n),
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("pll_lock", n),
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("ifc_mode", 4),
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("proto_rev", 7),
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("drover", n),
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]
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)
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self.comb += [
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self.data.ifc_mode.eq(platform.lookup_request("ifc_mode")),
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self.data.proto_rev.eq(__proto_rev__),
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# self.data.hw_rev.eq(platform.request("hw_rev")),
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]
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for i in range(n):
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dds = platform.lookup_request("dds", i)
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self.comb += [
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self.data.rf_sw[i].eq(dds.rf_sw),
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self.data.smp_err[i].eq(dds.smp_err),
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self.data.pll_lock[i].eq(dds.pll_lock),
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self.data.drover[i].eq(dds.drover),
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]
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class Urukul(Module):
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"""
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Urukul IO router and configuration/status
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=========================================
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The CPLD controls/monitors:
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* the four AD9912 or AD9910 DDS (SPI, status, reset, IO update)
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* the four digitally controlled RF step attenuators (SPI, reset)
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* the four RF switches
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* the clock input tree (division and clock selection)
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* the synchronization tree (sync source selection, sync clock output,
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sync drive)
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* the eight LEDs
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* the two EEM connectors
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* the test pads
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* the four configuration switches
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Pin Out
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-------
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Urukul operates from one or two EEM connectors. In standard SPI mode, the
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complete Urukul functionality can be accessed using only that interface.
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Standard SPI mode only needs the second EEM connector to interface with
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high resolution RF switching and synchronization signals. NU-Servo mode
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always requires two EEM connectors.
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| EEM | LVDS pair | PCB net | Function |
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|------+-----------+---------+-------------------------|
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| EEM0 | 0 | A0 | SCLK |
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| EEM0 | 1 | A1 | MOSI |
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| EEM0 | 2 | A2 | MISO, NU_CLK |
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| EEM0 | 3 | A3 | CS0 |
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| EEM0 | 4 | A4 | CS1 |
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| EEM0 | 5 | A5 | CS2, NU_CS |
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| EEM0 | 6 | A6 | IO_UPDATE |
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| EEM0 | 7 | A7 | DDS_RESET, SYNC_OUT |
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| EEM1 | 0 | B8 | SYNC_CLK, NU_MOSI0 |
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| EEM1 | 1 | B9 | SYNC_IN, NU_MOSI1 |
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| EEM1 | 2 | B10 | IO_UPDATE_RET, NU_MOSI2 |
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| EEM1 | 3 | B11 | NU_MOSI3 |
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| EEM1 | 4 | B12 | SW0 |
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| EEM1 | 5 | B13 | SW1 |
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| EEM1 | 6 | B14 | SW3 |
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| EEM1 | 7 | B15 | SW4 |
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IFC_MODE
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--------
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DIP switches are used to configure the operation of the Urukul CPLD. The
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four IFC mode switches are assigned as:
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| IFC_MODE | Name | Function |
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|----------+---------+-------------------------------------------------|
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| 0 | EN_9910 | On if AD9910 is populated (OR VARIANT) |
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| 1 | EN_NU | On if NU-Servo mode is used |
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| 2 | EN_EEM1 | On if the SYNC signals on EEM1 should be driven |
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| 3 | UNUSED | Unusable on Urukul/v1.0 |
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On Urukul/v1.0, IFC_MODE[0] | IFC_MODE[3] drive EN_9910.
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On Urukul/v1.1, IFC_MODE[0] | VARIANT (board population) drive EN_9910.
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See :class:`Urukul`
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SPI
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---
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An SPI interface is provided to access any of the six serial devices (the
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configuration/status SPI interface, the attenuator SPI interface, and the
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four DDS SPI interfaces). It comprises the SCLK, MOSI, MISO, CS0, CS1, and
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CS2 signals. With EN_NU, both MISO and CS2 (and the functionality provided
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by them) are unavailable. I.e. CS >= 4 (the individual DDS access) are only
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available outside of EN_NU or through CS = 3 (and CFG.MASK_NU).
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The target chip (or set of chips) is selected by CS0/CS1/CS2 (CS2 being the
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MSB). The encoding is as follows:
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| CS | chip |
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|-----------+--------------------------------------------|
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| 0 = 0b000 | None |
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| 1 = 0b001 | CFG |
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| 2 = 0b010 | ATT |
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| 3 = 0b011 | Multiple DDS (those masked by CFG.MASK_NU) |
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| 4 = 0b100 | DDS0 |
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| 5 = 0b101 | DDS1 |
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| 6 = 0b110 | DDS2 |
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| 7 = 0b111 | DDS3 |
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The SPI interface is CPOL=0, CPHA=0, SPI mode 0, 4-wire, full fuplex. Clock
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cycles during CS[0:2] = 0 are ignored (but may still be visible on the DDS
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SCK outputs).
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See :class:`Urukul` and :class:`SR`
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CFG
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---
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The configuration status register controls the overall operation of Urukul,
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allows some configuration options to be changed and the status of some
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signals to be monitored.
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It is 24 bits wide, MSB first.
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See :class:`SR`
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CFG write
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.........
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See :class:`CFG`
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CFG read
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........
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See :class:`Status`
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QSPI
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----
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If EN_NU is activated, the four DDS are additionally exposed through a
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quad-SPI write-only interface defined by the signals NU_CLK, NU_CS, and
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NU_MOSI[0:3].
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Only those DDS which are **not** masked by CFG.MASK_NU can be accessed
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through the QSPI interface. This allows initial setup and configuration of
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the DDS individually through the "regular" SPI interface in EN_NU mode.
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DDS[0:3].CS is driven by NU_CS (for those DDS not masked)
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DDS[0:3].SCK is driven by NU_CLK (for those DDS not masked)
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DDS[0:3].MOSI is driven by NU_MOSI[0:3] (for those DDS not masked)
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DDS[0:3].MISO is unavailable
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DDS[0:3].IO_UPDATE is driven by IO_UPDATE (for those DDS not masked)
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See :class:`Urukul`
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ATT
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---
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The digital step attenuators are daisy-chained (ATT[n].S_OUT driving the
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next ATT[n+1].S_IN) and form a 32 bit SPI compatible shift register. The
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data from the attenuator shift register is transferred to the active
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attenuation register on the de-selection of the attenuators after shifting.
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Clocking
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--------
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CFG.CLK_SEL selects the clock source for the clock fanout to the DDS.
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Valid clocking options are:
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- 0x00: on-board 100MHz oscillator
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- 0x01: front-panel SMA
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- 0x02: internal MMCX (hardware version >= 1.3 only)
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For hardware revisions prior to v1.3, 0x00 selects either the on-board
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oscillator or the MMCX, dependent on component population. In these
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hardware revisions, the oscillator must be manually powered down to avoid
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RF leakage through the clock switch.
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If CFG.DIV is 0 the clock division is determined EN_9910. If it is on,
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the clock to the DDS (from the XCO, the internal MMCX or the external
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SMA) is divided by 4.
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If CFG.DIV is 1, 2, or 3 it determines the clock divisor (1, 2, 4).
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Synchronization
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---------------
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IO_UPDATE_RET is provided to determine the round trip time for IO_UPDATE.
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DDS_RESET (not EN_9910) and SYNC_OUT (EN_9910) share an EEM signal.
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DDS_RESET provides a way to deterministically reset all AD9912 DDS SYNC_CLK
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divider. (https://ez.analog.com/docs/DOC-14472)
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SYNC_OUT is an input to the SYNC fanout (input to Urukul, output from the
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controlling FPGA upstream) to externally and actively synchronize the
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AD9910 SYNC_CLK dividers. The SYNC fanout can be driven using either
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EEM1.SYNC_OUT or DDS0.SYNC_OUT (selected by CFG.SYNC_SEL).
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SYNC_CLK and SYNC_IN are available with EN_9910 & EN_EEM1 to synchronize
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external logic to the DDS. A round-trip time measurement using
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IO_UPDATE_RET would need to be performed. SYNC_IN is an output from Urukul,
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an input to the controlling upstream FPGA, and an input to all DDS.
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RF switches
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-----------
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The RF switches are activated with CFG.RF_SW or (logic OR) SW[0:3].
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EEM1.SW[0:3] provide a high resolution and high-bandwidth port to RF
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switching.
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LEDs
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----
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The green channel LEDs mirror the status of the RF switches. The red LEDs
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are activated by ``CFG.LED | (EN_9910 & (DDS[0:3].SMP_ERR |
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~DDS[0:3].PLL_LOCK))``. I.e. they are lit by the register or (logic OR) an
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synchronization/PLL error on that channel's DDS.
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Test points
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-----------
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The test points expose miscellaneous signals for debugging and are not part
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of the protocol revision.
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"""
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def __init__(self, platform):
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clk = platform.request("clk")
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dds_sync = platform.request("dds_sync")
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dds_common = platform.request("dds_common")
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ifc_mode = platform.request("ifc_mode")
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variant = platform.request("variant")
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att = platform.request("att")
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fsen = platform.request("fsen")
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dds = [platform.request("dds", i) for i in range(4)]
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ts_clk_div = TSTriple()
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self.specials += [
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ts_clk_div.get_tristate(clk.div)
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]
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self.eem = eem = []
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for i in range(12):
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tsi = TSTriple()
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eemi = platform.request("eem", i)
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tsi._pin = eemi.io
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self.specials += tsi.get_tristate(eemi.io)
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self.comb += eemi.oe.eq(tsi.oe)
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eem.append(tsi)
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# AD9910 only
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self.clock_domains.cd_sys = ClockDomain("sys", reset_less=True)
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self.clock_domains.cd_sck0 = ClockDomain("sck0", reset_less=True)
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self.clock_domains.cd_sck1 = ClockDomain("sck1", reset_less=True)
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platform.add_period_constraint(eem[0]._pin, 8.)
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platform.add_period_constraint(eem[2]._pin, 8.)
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self.specials += [
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Instance("BUFG", i_I=eem[0].i, o_O=self.cd_sck1.clk),
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]
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en_9910 = Signal() # AD9910 populated (instead of AD9912)
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en_nu = Signal() # NU-Servo operation with quad SPI
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en_eem1 = Signal() # EEM1 connected and sync outputs used
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self.comb += [
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fsen.eq(1),
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en_9910.eq(ifc_mode[0] | variant),
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en_nu.eq(ifc_mode[1]),
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en_eem1.eq(ifc_mode[2]),
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[eem[i].oe.eq(0) for i in range(12) if i not in (2, 10)],
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eem[2].oe.eq(~en_nu),
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eem[10].oe.eq(~en_nu & en_eem1),
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eem[10].o.eq(eem[6].i),
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self.cd_sck0.clk.eq(~self.cd_sck1.clk),
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dds_sync.clk_out_en.eq(~en_nu & en_eem1 & en_9910),
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dds_sync.sync_out_en.eq(~en_nu & en_eem1 & en_9910),
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]
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cfg = CFG(platform)
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stat = Status(platform)
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sr = SR(52)
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assert len(cfg.data) <= len(sr.di)
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assert len(stat.data) <= len(sr.do)
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self.submodules += cfg, stat, sr
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sel = Signal(8)
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cs = Signal(3)
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miso = Signal(8)
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mosi = eem[1].i
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|
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|
self.specials += [Instance("FDPE", p_INIT=1,
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i_D=0, i_C=ClockSignal("sck1"), i_CE=sel[2],
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i_PRE=~(sel[2] & cfg.data.att_en[i]), o_Q=att.le[i]) for i in range(4)]
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|
|
|
self.comb += [
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|
cfg.en_9910.eq(en_9910),
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|
# Important note regarding the chip-select (CS) signals (`eem[3].i`, `eem[4].i`, `eem[5].i`):
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# These CS signals are generated by the Kasli SPI controller and used to select specific Urukul SPI targets.
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|
# Some of these SPI targets rely on the CS signals to drive asynchronous inputs, meaning improper handling
|
|
# could introduce glitches.
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|
#
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|
# We are reasonably confident that the following combinatorial equation does not introduce glitches because:
|
|
#
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|
# * The Kasli SPI controller drives the CS signals from DFFs on the same clock, ensuring synchronization.
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|
# * The `en_nu` signal, controlled by a DIP switch, is a constant. As a result, `~en_nu & eem[5].i`
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|
# should not create differences in gate propagation delays.
|
|
#
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|
# NOTE: As long as the combinatorial logic below remains well-formed and does not introduce unintended
|
|
# asynchronous behavior, the signals should remain glitch-free. However, modifications to this logic
|
|
# should be made with caution to avoid potential hazards or race conditions that could lead to glitches.
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|
cs.eq(Cat(eem[3].i, eem[4].i, ~en_nu & eem[5].i)),
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|
|
|
Array(sel)[cs].eq(1), # one-hot
|
|
eem[2].o.eq(Array(miso)[cs]),
|
|
miso[3].eq(miso[4]), # for all-DDS take DDS0:MISO
|
|
|
|
att.clk.eq(sel[2] & self.cd_sck1.clk),
|
|
Cat(att.s_in, miso[2]).eq(Cat(mosi, att.s_out)),
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|
|
|
sr.sel.eq(sel[1]),
|
|
sr.sdi.eq(mosi),
|
|
miso[1].eq(sr.sdo),
|
|
|
|
cfg.data.raw_bits().eq(sr.di),
|
|
sr.do.eq(stat.data.raw_bits()),
|
|
|
|
# dividers: z: 1, 0: 2, 1: 4
|
|
# 1: div-by-4 for AD9910
|
|
# z: div-by-1 for AD9912
|
|
ts_clk_div.oe.eq(Array([en_9910, 0, 1, 1])[cfg.data.div]),
|
|
ts_clk_div.o.eq(Array([1, 1, 0, 1])[cfg.data.div]),
|
|
]
|
|
for i, ddsi in enumerate(dds):
|
|
sel_spi = Signal()
|
|
sel_nu = Signal()
|
|
self.comb += [
|
|
sel_spi.eq(sel[i + 4] | (sel[3] & cfg.data.mask_nu[i])),
|
|
sel_nu.eq(en_nu & ~cfg.data.mask_nu[i]),
|
|
ddsi.cs_n.eq(~Mux(sel_nu, eem[5].i, sel_spi)),
|
|
ddsi.sck.eq(Mux(sel_nu, eem[2].i, self.cd_sck1.clk)),
|
|
ddsi.sdi.eq(Mux(sel_nu, eem[i + 8].i, mosi)),
|
|
miso[i + 4].eq(ddsi.sdo),
|
|
ddsi.io_update.eq(Mux(cfg.data.mask_nu[i],
|
|
cfg.data.io_update[i], eem[6].i)),
|
|
ddsi.reset.eq(cfg.data.rst | (~en_9910 & eem[7].i)),
|
|
]
|
|
|
|
tp = [platform.request("tp", i) for i in range(5)]
|
|
self.comb += [
|
|
tp[0].eq(dds[0].cs_n),
|
|
tp[1].eq(dds[0].sck),
|
|
tp[2].eq(dds[0].sdi),
|
|
tp[3].eq(dds[0].sdo),
|
|
tp[4].eq(dds[0].drover),
|
|
]
|