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urukul v1.4 minimum

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This commit is contained in:
Robert Jördens
2019-08-26 20:32:51 +02:00
parent e9daf63af9
commit 8dd508013a
2 changed files with 141 additions and 112 deletions
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36
urukul.py
View File

@@ -2,7 +2,7 @@ from migen import *
# increment this if the behavior (LEDs, registers, EEM pins) changes
__proto_rev__ = 8
__proto_rev__ = 0
class SR(Module):
@@ -122,7 +122,6 @@ class CFG(Module):
self.en_9910 = Signal()
self.comb += [
dds_common.profile.eq(self.data.profile),
clk.in_sel.eq(self.data.clk_sel0),
clk.mmcx_osc_sel.eq(self.data.clk_sel1),
clk.osc_en_n.eq(clk.in_sel | clk.mmcx_osc_sel),
@@ -141,6 +140,10 @@ class CFG(Module):
dds.led[0].eq(dds.rf_sw), # green
dds.led[1].eq(self.data.led[i] | (self.en_9910 & (
dds.smp_err | ~dds.pll_lock))), # red
dds.profile.eq(self.data.profile),
dds.osk.eq(1),
dds.drhold.eq(0),
dds.drctl.eq(0),
]
@@ -158,7 +161,8 @@ class Status(Module):
| SMP_ERR | 4 | DDS[0:3].SMP_ERR |
| PLL_LOCK | 4 | DDS[0:3].PLL_LOCK |
| IFC_MODE | 4 | IFC_MODE[0:3] |
| PROTO_REV | 7 | Protocol revision (see __proto_rev__) |
| PROTO_REV | 3 | Protocol revision (see __proto_rev__) |
| HW_REV | 4 | Hardware revision |
| DUMMY | 1 | Not used, not usable, undefined |
"""
def __init__(self, platform, n=4):
@@ -167,19 +171,23 @@ class Status(Module):
("smp_err", n),
("pll_lock", n),
("ifc_mode", 4),
("proto_rev", 7),
("proto_rev", 3),
("hw_rev", 4),
("dummy", 1)
])
self.comb += [
self.data.ifc_mode.eq(platform.lookup_request("ifc_mode")),
self.data.proto_rev.eq(__proto_rev__)
self.data.proto_rev.eq(__proto_rev__),
self.data.hw_rev.eq(platform.request("hw_rev")),
]
for i in range(n):
dds = platform.lookup_request("dds", i)
self.comb += [
self.data.rf_sw[i].eq(dds.rf_sw),
self.data.smp_err[i].eq(dds.smp_err),
self.data.pll_lock[i].eq(dds.pll_lock),
self.data.pll_lock[i].eq(dds.pll_lock
| dds.drover # FIXME debug
),
]
@@ -451,9 +459,9 @@ class Urukul(Module):
miso = Signal(8)
mosi = eem[1].i
self.specials += Instance("FDPE", p_INIT=1,
self.specials += [Instance("FDPE", p_INIT=1,
i_D=0, i_C=ClockSignal("sck1"), i_CE=sel[2], i_PRE=~sel[2],
o_Q=att.le)
o_Q=att.le[i]) for i in range(4)]
self.comb += [
cfg.en_9910.eq(en_9910),
@@ -463,8 +471,7 @@ class Urukul(Module):
miso[3].eq(miso[4]), # for all-DDS take DDS0:MISO
att.clk.eq(sel[2] & self.cd_sck1.clk),
att.s_in.eq(mosi),
miso[2].eq(att.s_out),
Cat(att.s_in, miso[2]).eq(Cat(mosi, att.s_out)),
sr.sel.eq(sel[1]),
sr.sdi.eq(mosi),
@@ -473,8 +480,6 @@ class Urukul(Module):
cfg.data.raw_bits().eq(sr.di),
sr.do.eq(stat.data.raw_bits()),
dds_common.reset.eq(cfg.data.rst | (~en_9910 & eem[7].i)),
# dividers: z: 1, 0: 2, 1: 4
# 1: div-by-4 for AD9910
# z: div-by-1 for AD9912
@@ -493,11 +498,14 @@ class Urukul(Module):
miso[i + 4].eq(ddsi.sdo),
ddsi.io_update.eq(Mux(cfg.data.mask_nu[i],
cfg.data.io_update, eem[6].i)),
ddsi.reset.eq(cfg.data.rst | (~en_9910 & eem[7].i)),
]
tp = [platform.request("tp", i) for i in range(3)]
tp = [platform.request("tp", i) for i in range(5)]
self.comb += [
tp[0].eq(dds[0].cs_n),
tp[1].eq(dds[0].sck),
tp[2].eq(dds[0].sdi)
tp[2].eq(dds[0].sdi),
tp[3].eq(dds[0].sdo),
tp[4].eq(dds[0].drover),
]

217
urukul_cpld.py
View File

@@ -3,146 +3,167 @@ from migen.build.xilinx import XilinxPlatform
from migen.build.xilinx.ise import XilinxISEToolchain
_io = [
("tp", 0, Pins("P143")),
("tp", 1, Pins("P140")),
("tp", 2, Pins("P138")),
# ("tp", 3, Pins("P136")), # mmcx_osc_sel
# ("tp", 4, Pins("P134")), # osc_en_n
("tp", 0, Pins("A4")),
("tp", 1, Pins("A5")),
("tp", 2, Pins("B5")),
("tp", 3, Pins("A6")),
("tp", 4, Pins("A7")),
# P112 is open on Urukul/v1.0
("ifc_mode", 0, Pins("P104 P105 P110 P112")),
("ifc_mode", 0, Pins("E14 B16 A16 B15")),
("hw_rev", 0, Pins("C16 D15 E15 E16")),
# P111 is IFC_MODE_SEL3 on Urukul/v1.0
# 10k low: AD9912, 0R high: AD9910
("variant", 0, Pins("P111")),
("variant", 0, Pins("A15")),
# fail save LVDS enable, LVDS mode selection
# high: type 2 receiver, failsafe low
("fsen", 0, Pins("P115")),
("fsen", 0, Pins("N15")),
("clk", 0,
Subsignal("div", Pins("P11")),
Subsignal("in_sel", Pins("P12")),
Subsignal("mmcx_osc_sel", Pins("P136")),
Subsignal("osc_en_n", Pins("P134"))),
("att", 0,
Subsignal("clk", Pins("P95")),
Subsignal("le", Pins("P94")),
Subsignal("rst_n", Pins("P96")),
Subsignal("s_in", Pins("P133")),
Subsignal("s_out", Pins("P97"))),
Subsignal("div", Pins("E5")),
Subsignal("in_sel", Pins("G5")),
Subsignal("mmcx_osc_sel", Pins("C11")),
Subsignal("osc_en_n", Pins("B6"))),
("dds_common", 0,
Subsignal("master_reset", Pins("P102")),
Subsignal("reset", Pins("P120")),
Subsignal("io_reset", Pins("P129")),
Subsignal("profile", Pins("P130 P131 P132"))),
Subsignal("master_reset", Pins("F16")),
Subsignal("io_reset", Pins("B9"))),
("dds_sync", 0,
Subsignal("clk0", Pins("P38"), Misc("PULLUP")), # DDS_SYNC_CLK0
Subsignal("clk_out_en", Pins("P86")), # DDS_SYNC_CLK_OUTEN
Subsignal("sync_sel", Pins("P60")), # DDS_SYNC_CLKSEL
Subsignal("sync_out_en", Pins("P92"))), # DDS_SYNC_OUTEN
Subsignal("clk0", Pins("P5"), Misc("PULLUP")), # DDS_SYNC_CLK0
Subsignal("clk_out_en", Pins("T5")), # DDS_SYNC_CLK_OUTEN
Subsignal("sync_sel", Pins("T10")), # DDS_SYNC_CLKSEL
Subsignal("sync_out_en", Pins("R6"))), # DDS_SYNC_OUTEN
("att", 0,
Subsignal("clk", Pins("E9")),
Subsignal("rst_n", Pins("N9")),
Subsignal("le", Pins("E10 P8 C8 K4")),
Subsignal("s_in", Pins("B7 D8 D7 L5")),
Subsignal("s_out", Pins("C10 C9 E8 R9"))),
("dds", 0,
Subsignal("rf_sw", Pins("P103")),
Subsignal("led", Pins("P128 P126")),
Subsignal("smp_err", Pins("P19"), Misc("PULLUP")),
Subsignal("pll_lock", Pins("P21"), Misc("PULLUP")),
Subsignal("io_update", Pins("P4")),
Subsignal("sck", Pins("P3")),
Subsignal("sdo", Pins("P113"), Misc("PULLUP")),
Subsignal("sdi", Pins("P2")),
Subsignal("cs_n", Pins("P119"))),
Subsignal("rf_sw", Pins("D13")),
Subsignal("led", Pins("E11 B10")),
Subsignal("smp_err", Pins("D4"), Misc("PULLUP")),
Subsignal("pll_lock", Pins("E4"), Misc("PULLUP")),
Subsignal("io_update", Pins("B1")),
Subsignal("profile", Pins("A9 B8 A8")),
Subsignal("osk", Pins("C13")),
Subsignal("drover", Pins("D11")),
Subsignal("drhold", Pins("E13")),
Subsignal("drctl", Pins("C14")),
Subsignal("reset", Pins("B13")),
Subsignal("sck", Pins("A2")),
Subsignal("sdo", Pins("A3"), Misc("PULLUP")),
Subsignal("sdi", Pins("B2")),
Subsignal("cs_n", Pins("B3"))),
("dds", 1,
Subsignal("rf_sw", Pins("P101")),
Subsignal("led", Pins("P118 P125")),
Subsignal("smp_err", Pins("P28"), Misc("PULLUP")),
Subsignal("pll_lock", Pins("P35"), Misc("PULLUP")),
Subsignal("io_update", Pins("P10")),
Subsignal("sck", Pins("P9")),
Subsignal("sdo", Pins("P6"), Misc("PULLUP")),
Subsignal("sdi", Pins("P7")),
Subsignal("cs_n", Pins("P5"))),
Subsignal("rf_sw", Pins("C12")),
Subsignal("led", Pins("A13 A11")),
Subsignal("smp_err", Pins("J1"), Misc("PULLUP")),
Subsignal("pll_lock", Pins("K2"), Misc("PULLUP")),
Subsignal("io_update", Pins("P4")),
Subsignal("profile", Pins("D3 D2 E2")),
Subsignal("osk", Pins("C3")),
Subsignal("drover", Pins("B4")),
Subsignal("drhold", Pins("C7")),
Subsignal("drctl", Pins("C4")),
Subsignal("reset", Pins("F2")),
Subsignal("sck", Pins("K3")),
Subsignal("sdo", Pins("J3"), Misc("PULLUP")),
Subsignal("sdi", Pins("K5")),
Subsignal("cs_n", Pins("J4"))),
("dds", 2,
Subsignal("rf_sw", Pins("P100")),
Subsignal("led", Pins("P116 P117")),
Subsignal("smp_err", Pins("P40"), Misc("PULLUP")),
Subsignal("pll_lock", Pins("P41"), Misc("PULLUP")),
Subsignal("io_update", Pins("P14")),
Subsignal("sck", Pins("P13")),
Subsignal("sdo", Pins("P17"), Misc("PULLUP")),
Subsignal("sdi", Pins("P15")),
Subsignal("cs_n", Pins("P16"))),
Subsignal("rf_sw", Pins("D10")),
Subsignal("led", Pins("A14 B14")),
Subsignal("smp_err", Pins("P6"), Misc("PULLUP")),
Subsignal("pll_lock", Pins("N7"), Misc("PULLUP")),
Subsignal("io_update", Pins("H5")),
Subsignal("profile", Pins("M1 M6 M5")),
Subsignal("osk", Pins("L1")),
Subsignal("drover", Pins("L2")),
Subsignal("drhold", Pins("L4")),
Subsignal("drctl", Pins("K1")),
Subsignal("reset", Pins("R10")),
Subsignal("sck", Pins("H4")),
Subsignal("sdo", Pins("J2"), Misc("PULLUP")),
Subsignal("sdi", Pins("H3")),
Subsignal("cs_n", Pins("H1"))),
("dds", 3,
Subsignal("rf_sw", Pins("P98")),
Subsignal("led", Pins("P121 P124")),
Subsignal("smp_err", Pins("P39"), Misc("PULLUP")),
Subsignal("pll_lock", Pins("P49"), Misc("PULLUP")),
Subsignal("io_update", Pins("P25")),
Subsignal("sck", Pins("P22")),
Subsignal("sdo", Pins("P23"), Misc("PULLUP")),
Subsignal("sdi", Pins("P26")),
Subsignal("cs_n", Pins("P24"))),
Subsignal("rf_sw", Pins("D9")),
Subsignal("led", Pins("A12 B11")),
Subsignal("smp_err", Pins("N6"), Misc("PULLUP")),
Subsignal("pll_lock", Pins("P7"), Misc("PULLUP")),
Subsignal("io_update", Pins("E3")),
Subsignal("profile", Pins("N3 P1 P2")),
Subsignal("osk", Pins("N2")),
Subsignal("drover", Pins("N5")),
Subsignal("drhold", Pins("N4")),
Subsignal("drctl", Pins("N1")),
Subsignal("reset", Pins("T8")),
Subsignal("sck", Pins("H2")),
Subsignal("sdo", Pins("G3"), Misc("PULLUP")),
Subsignal("sdi", Pins("F5")),
Subsignal("cs_n", Pins("G4"))),
("eem", 0,
Subsignal("io", Pins("P30")),
Subsignal("oe", Pins("P58"))),
Subsignal("io", Pins("M2" )),
Subsignal("oe", Pins("P15"))),
("eem", 1,
Subsignal("io", Pins("P53")),
Subsignal("oe", Pins("P52"))),
Subsignal("io", Pins("R13")),
Subsignal("oe", Pins("M15"))),
("eem", 2,
Subsignal("io", Pins("P45")),
Subsignal("oe", Pins("P57"))),
Subsignal("io", Pins("T16")),
Subsignal("oe", Pins("K15"))),
("eem", 3,
Subsignal("io", Pins("P50")),
Subsignal("oe", Pins("P61"))),
Subsignal("io", Pins("R16")),
Subsignal("oe", Pins("N16"))),
("eem", 4,
Subsignal("io", Pins("P43")),
Subsignal("oe", Pins("P64"))),
Subsignal("io", Pins("R15")),
Subsignal("oe", Pins("L15"))),
("eem", 5,
Subsignal("io", Pins("P51")),
Subsignal("oe", Pins("P59"))),
Subsignal("io", Pins("R14")),
Subsignal("oe", Pins("M16"))),
("eem", 6,
Subsignal("io", Pins("P54")),
Subsignal("oe", Pins("P68"))),
Subsignal("io", Pins("R12")),
Subsignal("oe", Pins("L16"))),
("eem", 7,
Subsignal("io", Pins("P56")),
Subsignal("oe", Pins("P69"))),
Subsignal("io", Pins("T15")),
Subsignal("oe", Pins("P16"))),
("eem", 8,
Subsignal("io", Pins("P32")),
Subsignal("oe", Pins("P80"))),
Subsignal("io", Pins("M3")),
Subsignal("oe", Pins("R7"))),
("eem", 9,
Subsignal("io", Pins("P71")),
Subsignal("oe", Pins("P85"))),
Subsignal("io", Pins("J5")),
Subsignal("oe", Pins("T4"))),
("eem", 10,
Subsignal("io", Pins("P74")),
Subsignal("oe", Pins("P82"))),
Subsignal("io", Pins("R3")),
Subsignal("oe", Pins("R4"))),
("eem", 11,
Subsignal("io", Pins("P78")),
Subsignal("oe", Pins("P77"))),
Subsignal("io", Pins("R2")),
Subsignal("oe", Pins("R5"))),
("eem", 12,
Subsignal("io", Pins("P70")),
Subsignal("oe", Pins("P79"))),
Subsignal("io", Pins("R1")),
Subsignal("oe", Pins("M7"))),
("eem", 13,
Subsignal("io", Pins("P87")),
Subsignal("oe", Pins("P81"))),
Subsignal("io", Pins("T1")),
Subsignal("oe", Pins("R8"))),
("eem", 14,
Subsignal("io", Pins("P76")),
Subsignal("oe", Pins("P91"))),
Subsignal("io", Pins("T2")),
Subsignal("oe", Pins("T7"))),
("eem", 15,
Subsignal("io", Pins("P88")),
Subsignal("oe", Pins("P83"))),
Subsignal("io", Pins("T3")),
Subsignal("oe", Pins("M8"))),
]
class Platform(XilinxPlatform):
def __init__(self):
XilinxPlatform.__init__(self, "xc2c128-6-tq144", _io)
XilinxPlatform.__init__(self, "xc2c256-6-ft256", _io)
self.toolchain.xst_opt = "-ifmt MIXED"
self.toolchain.par_opt = ("-optimize speed -unused pullup "
"-iostd LVCMOS33")