add tests

Makefile

@@ -1,11 +1,15 @@
 .PHONY: all
 all: build
 
+.PHONY: test
+test:
+	python urukul_sim.py
+
 .PHONY: build
 build: build/urukul.vm6
 
 build/urukul.vm6: urukul.py urukul_cpld.py
-	python urukul.py
+	python urukul_impl.py
 
 REV:=$(shell git describe --always --abbrev=8 --dirty)
 

urukul.py

@@ -33,13 +33,15 @@ class SR(Module):
         self.sync.sck0 += [
                 If(self.sel,
                     If(cnt_done,
-                        self.di.eq(sr),
+                        self.di.eq(Cat(i, sr)),
                         sr.eq(self.do),
                         cnt.eq(cnt.reset)
                     ).Else(
                         sr.eq(Cat(i, sr)),
                         cnt.eq(cnt - 1)
                     )
+                ).Else(
+                    cnt.eq(cnt.reset)
                 )
         ]
 
@@ -53,14 +55,13 @@ class CFG(Module):
             ("profile", 3),
 
             ("att_le", 1),
+            ("io_update", 1),
 
             ("mask_nu", 4),
 
             ("clk_sel", 1),
             ("sync_sel", 1),
 
-            ("io_update", 1),
-
             ("rst", 1),
             ("io_rst", 1),
         ])
@@ -85,7 +86,7 @@ class CFG(Module):
             dds = platform.lookup_request("dds", i)
             self.comb += [
                     sw.oe.eq(0),
-                    dds.rf_sw.eq(sw.io ^ self.data.rf_sw[i]),
+                    dds.rf_sw.eq(sw.io | self.data.rf_sw[i]),
                     dds.led[0].eq(dds.rf_sw),  # green
                     dds.led[1].eq(self.data.led[i] | (en_9910 & (
                         dds.smp_err | ~dds.pll_lock))),  # red
@@ -155,7 +156,7 @@ class Urukul(Module):
 
         en_9910 = Signal()  # AD9910 populated (instead of AD9912)
         en_nu = Signal()  # NU-Servo operation with quad SPI
-        en_eemb = Signal()  # EEM-B connected
+        en_eemb = Signal()  # EEM-B connected and used
         en_unused = Signal()
         self.comb += Cat(en_9910, en_nu, en_eemb, en_unused).eq(ifc_mode)
 
@@ -205,15 +206,15 @@ class Urukul(Module):
                     (~en_9910 & eem[7].i)),
         ]
         for i, ddsi in enumerate(dds):
-            seli = Signal()
+            sel_spi = Signal()
             nu_mosi = eem[i + 8].i
-            en_nu_i = Signal()
+            sel_nu = Signal()
             self.comb += [
-                    seli.eq(sel[i + 4] | (sel[3] & cfg.data.mask_nu[i])),
-                    en_nu_i.eq(~seli & (en_nu & ~cfg.data.mask_nu[i])),
-                    ddsi.cs_n.eq(~(seli | (en_nu_i & eem[5].i))),
-                    ddsi.sck.eq(Mux(en_nu_i, nu_sck, self.cd_sck1.clk)),
-                    ddsi.sdi.eq(Mux(en_nu_i, nu_mosi, mosi)),
+                    sel_spi.eq(sel[i + 4] | (sel[3] & cfg.data.mask_nu[i])),
+                    sel_nu.eq(~sel_spi & (en_nu & ~cfg.data.mask_nu[i])),
+                    ddsi.cs_n.eq(~(sel_spi | (sel_nu & eem[5].i))),
+                    ddsi.sck.eq(Mux(sel_nu, nu_sck, sel_spi & self.cd_sck1.clk)),
+                    ddsi.sdi.eq(Mux(sel_nu, nu_mosi, mosi)),
                     miso[i + 4].eq(ddsi.sdo),
                     ddsi.io_update.eq(Mux(cfg.data.mask_nu[i],
                         cfg.data.io_update, eem[6].i)),
@@ -229,12 +230,4 @@ class Urukul(Module):
         ]
 
 
-def main():
-    from urukul_cpld import Platform
-    p = Platform()
-    urukul = Urukul(p)
-    p.build(urukul, build_name="urukul", mode="cpld")
 
-
-if __name__ == "__main__":
-    main()

urukul_sim.py

@@ -0,0 +1,101 @@
+from collections import namedtuple
+
+from migen import *
+from migen.fhdl.specials import Tristate
+from migen.build.generic_platform import ConstraintError
+
+from urukul import Urukul
+from urukul_cpld import Platform
+
+
+class SimTristate:
+    @staticmethod
+    def lower(dr):
+        return SimTristateImpl(dr.i, dr.o, dr.oe, dr.target)
+
+
+class SimTristateImpl(Module):
+    def __init__(self, i, o, oe, target):
+        self.i = i
+        self.o = o
+        self.oe = oe
+        self.target = target
+        self.comb += [
+                # If(oe, target.eq(o)),
+                # i.eq(Mux(oe, o, target))
+                i.eq(target)
+        ]
+
+
+class SimInstance:
+    @staticmethod
+    def lower(dr):
+        return Module()
+
+
+class TB(Module):
+    def __init__(self, platform, dut):
+        self.platform = platform
+        self.submodules.dut = dut
+        for k in "tp dds dds_common dds_sync clk ifc_mode att eem".split():
+            v = []
+            while True:
+                try:
+                    v.append(platform.lookup_request(k, len(v)))
+                except ConstraintError:
+                    break
+            if len(v) == 1:
+                v = v[0]
+            setattr(self, k, v)
+        self.cs = Signal(3)
+        self.comb += [
+                Cat(self.eem[3].io, self.eem[4].io, self.eem[5].io).eq(
+                    self.cs)
+        ]
+
+    def spi(self, cs, n, mosi):
+        # while (yield self.dut.cd_sck0.clk):
+        #     pass
+        yield self.cs.eq(cs)
+        miso = 0
+        for i in range(n - 1, -1, -1):
+            yield self.eem[1].io.eq((mosi >> i) & 1)
+            yield self.eem[0].io.eq(0)
+            yield
+            yield self.eem[0].io.eq(1)
+            miso = (miso << 1) | (yield self.eem[2].io)
+            yield
+            yield self.eem[0].io.eq(0)
+        yield
+        yield self.cs.eq(0)
+        yield
+        return miso
+
+    def test(self):
+        p = self.platform
+        dut = self.dut
+        yield self.ifc_mode[0].eq(1)  # en_9910
+        yield self.ifc_mode[1].eq(0)  # en_nu
+        yield self.ifc_mode[2].eq(1)  # en_eemb
+        yield self.eem[12].io.eq(1)  # rf_sw[0]
+        yield self.dds[1].smp_err.eq(1)
+        yield self.dds[0].pll_lock.eq(1)
+        yield
+        yield from self.spi(1, 24, 0x123456)
+        yield from self.spi(2, 32, 0xf0f0f0f0)  # ATT
+        yield from self.spi(4, 16, 0x1234)
+        yield
+
+
+def main():
+    p = Platform()
+    dut = Urukul(p)
+    tb = TB(p, dut)
+    run_simulation(tb, [tb.test()], vcd_name="urukul.vcd",
+            # just operate on sck0
+            clocks={"sys": 8, "sck1": (16, 4), "sck0": (16, 12)},
+            special_overrides={Tristate: SimTristate, Instance: SimInstance})
+
+
+if __name__ == "__main__":
+    main()