forked from sinara-hw/datasheets
562 lines
23 KiB
TeX
562 lines
23 KiB
TeX
\documentclass[10pt]{datasheet}
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\usepackage{palatino}
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\usepackage{textgreek}
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\usepackage{minted}
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\usepackage{tcolorbox}
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\usepackage{etoolbox}
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\BeforeBeginEnvironment{minted}{\begin{tcolorbox}[colback=white]}%
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\AfterEndEnvironment{minted}{\end{tcolorbox}}%
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\usepackage[justification=centering]{caption}
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\usepackage[utf8]{inputenc}
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\usepackage[english]{babel}
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\usepackage[english]{isodate}
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\usepackage{graphicx}
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\usepackage{subfigure}
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\usepackage{tikz}
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\usepackage{pgfplots}
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\usepackage{circuitikz}
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\usetikzlibrary{calc}
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\usetikzlibrary{fit,backgrounds}
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\title{4410/4412 Urukul}
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\author{M-Labs Limited}
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\date{November 2021}
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\revision{Revision 1}
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\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
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\begin{document}
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\maketitle
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\section{Features}
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\begin{itemize}
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\item{4 channels 1GS/s DDS.}
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\item{Output frequency ranges from \textless 1 to \textgreater 400 MHz.}
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\item{Sub-Hz frequency resolution.}
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\item{Controlled phase steps.}
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\item{Accurate output amplitude control.}
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\end{itemize}
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\section{Applications}
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\begin{itemize}
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\item{Agile local oscillator (LO) frequency synthesis.}
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\item{Programmable clock generators.}
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\item{Fast frequency hopping.}
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\end{itemize}
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\section{General Description}
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The 4410/4412 Urukul card is a 4hp EEM module part of the ARTIQ Sinara family.
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It adds frequency generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
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It provides 4 channels of DDS at 1GS/s.
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Output frequency from \textless 1 to \textgreater 400 MHz are supported.
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The nominal maximum output power of each channel is 10dBm.
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Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator.
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RF switches (1ns temporal resolution) on each channel provides 70 dB isolation.
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4410 Urukul comes with AD9910 chips, while 4412 Urukul comes with AD9912 chips instead.
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% Switch to next column
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\vfill\break
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\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
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\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
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\begin{figure}[h]
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\centering
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\scalebox{0.88}{
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\begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
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\begin{scope}[]
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% Node to pin-point the locations of SMA symbols
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\draw[color=white, text=black] (-0.1, 0) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (ext_clk) {};
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\draw[color=white, text=black] (-0.1, -0.35) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx) {};
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\draw[color=white, text=black] (-0.1, -1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf0) {};
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\draw[color=white, text=black] (-0.1, -2.45) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf1) {};
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\draw[color=white, text=black] (-0.1, -3.15) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf2) {};
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\draw[color=white, text=black] (-0.1, -3.85) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf3) {};
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% Labels for female EXT_CLK, MMCX, RF {0, 1, 2, 3}
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\node [label=left:\tiny{EXT CLK}] at (0.35, 0) {};
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\node [label=left:\tiny{MMCX}] at (0.35, -0.35) {};
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\node [label=left:\tiny{RF 0}] at (0.35, -1.75) {};
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\node [label=left:\tiny{RF 1}] at (0.35, -2.45) {};
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\node [label=left:\tiny{RF 2}] at (0.35, -3.15) {};
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\node [label=left:\tiny{RF 3}] at (0.35, -3.85) {};
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% draw female EXT_CLK, MMCX, RF {0, 1, 2, 3}
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\begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=2cm]
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\draw (0,0.65) -- (0,3);
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\clip (-1.5,0) rectangle (1.5,1.5);
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\draw (0,0) circle(1.5);
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\clip (-0.8,0) rectangle (0.8,0.8);
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\draw (0,0) circle(0.8);
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\end{scope}
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\begin{scope}[scale=0.07 , rotate=-90, xshift=5cm, yshift=2cm]
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\draw (0,0.65) -- (0,3);
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\clip (-1.5,0) rectangle (1.5,1.5);
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\draw (0,0) circle(1.5);
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\clip (-0.8,0) rectangle (0.8,0.8);
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\draw (0,0) circle(0.8);
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\end{scope}
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\begin{scope}[scale=0.07 , rotate=-90, xshift=25cm, yshift=2cm]
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\draw (0,0.65) -- (0,3);
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\clip (-1.5,0) rectangle (1.5,1.5);
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\draw (0,0) circle(1.5);
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\clip (-0.8,0) rectangle (0.8,0.8);
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\draw (0,0) circle(0.8);
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\end{scope}
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\begin{scope}[scale=0.07 , rotate=-90, xshift=35cm, yshift=2cm]
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\draw (0,0.65) -- (0,3);
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\clip (-1.5,0) rectangle (1.5,1.5);
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\draw (0,0) circle(1.5);
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\clip (-0.8,0) rectangle (0.8,0.8);
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\draw (0,0) circle(0.8);
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\end{scope}
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\begin{scope}[scale=0.07 , rotate=-90, xshift=45cm, yshift=2cm]
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\draw (0,0.65) -- (0,3);
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\clip (-1.5,0) rectangle (1.5,1.5);
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\draw (0,0) circle(1.5);
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\clip (-0.8,0) rectangle (0.8,0.8);
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\draw (0,0) circle(0.8);
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\end{scope}
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\begin{scope}[scale=0.07 , rotate=-90, xshift=55cm, yshift=2cm]
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\draw (0,0.65) -- (0,3);
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\clip (-1.5,0) rectangle (1.5,1.5);
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\draw (0,0) circle(1.5);
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\clip (-0.8,0) rectangle (0.8,0.8);
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\draw (0,0) circle(0.8);
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\end{scope}
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% Draw the internal oscillator
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\draw (0.02, -0.8) node[twoportshape, t={OSC}, circuitikz/bipoles/twoport/width=0.8, scale=0.4] (xo) {};
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% Draw the clock buffers as selector
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% \tikzset{demux/.style={muxdemux, muxdemux def={Lh=6, Rh=6, NL=3, NT=1, NB=0, NR=1, w=2.5}, no input leads, scale=0.4}};
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% \draw (1.55, -0.35) node[demux]{\rotatebox[origin=c]{-90}{CLK BUFFERS}};
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\draw (1.45, -0.35) node[twoportshape, t={CLK Buffers}, circuitikz/bipoles/twoport/width=2.2, scale=0.4, rotate=-90] (clk_buf) {};
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% Connect CLK_IN to DDS clock buffers
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\draw [-latexslim] (ext_clk.east) -- ++(1,0);
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\draw [-latexslim] (mmcx.east) -- ++(1,0);
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\draw [-latexslim] (xo.east) -- ++(1,0);
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% Connect CPLD clk_sel to DDS clock buffers
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\draw [-latexslim] (clk_buf.east) -- ++(0,-0.42);
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% Signal path: From control signals / clock of DDS to output of the RF switches
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\draw (1.35, -1.75) node[twoportshape, t={DDS Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.4] (sig0) {};
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\draw (1.35, -2.45) node[twoportshape, t={DDS Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.4] (sig1) {};
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\draw (1.35, -3.15) node[twoportshape, t={DDS Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.4] (sig2) {};
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\draw (1.35, -3.85) node[twoportshape, t={DDS Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.4] (sig3) {};
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% Extra node to expand the dotted area eastward
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\draw[color=white, text=black] (2.1, -3.85) node[twoportshape, circuitikz/bipoles/twoport/width=0.4, scale=0.4 ] (sig3_east) {};
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% Connect RF to DDS block
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\draw [latexslim-] (rf0.east) -- (sig0.west);
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\draw [latexslim-] (rf1.east) -- (sig1.west);
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\draw [latexslim-] (rf2.east) -- (sig2.west);
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\draw [latexslim-] (rf3.east) -- (sig3.west);
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% DDS signal path dotted area
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\node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(rf3)(sig0)(sig3_east.east)] (abs_dds) {};
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\node[fill=white, rotate=-90, scale=0.7] at (abs_dds.west) {DDS Channels};
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% CPLD
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\draw (3.8, -0.35) node[twoportshape, t={CPLD}, circuitikz/bipoles/twoport/width=1.1, scale=0.8, rotate=-90] (cpld) {};
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% Synthronization clock buffer for DDS block
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\draw (3.5, -2.5) node[twoportshape, t=\MymyLabel{Sync}{Buffer}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (sync_buf) {};
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% Connect CPLD to:
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% DDS clock buffer
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\draw [latexslim-] (clk_buf.north) -- (cpld.south);
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% DDS signal path
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\draw [latexslim-latexslim] (3.4, -0.7) -- ++ (-1.5, 0) -- ++ (0,-0.72);
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% Draw to intersection point, then complete the connection to sync buffer
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\draw [-] (4.2, -0.7) -- (4.55, -0.7) -- (4.55, -2.5);
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\draw [-latexslim] (4.55, -2.5) -- (sync_buf.east);
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% Connect sync buffer to DDS block
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\draw [-latexslim] (sig0.east) -- (3.35, -1.75) -- ++ (0, -0.5);
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\draw [-latexslim] (sync_buf.south) -- ++ (0, -0.3) -- ++ (-1.05, 0);
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% LVDS Transceivers
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\draw (6, 0) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds0) {};
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\draw (6, -0.7) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds1) {};
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\draw (6, -2.5) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds2) {};
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\draw (6, -3.2) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds3) {};
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% Connect CPLD to transceivers
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\draw [latexslim-latexslim] (lvds0.west) -- ++ (-1.13, 0);
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\draw [latexslim-latexslim] (lvds1.west) -- ++ (-0.35, 0) -- ++ (0, 0.6) -- ++ (-0.78, 0);
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\draw [latexslim-latexslim] (lvds2.west) -- ++ (-0.45, 0) -- ++ (0, 2.3) -- ++ (-0.68, 0);
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\draw [latexslim-latexslim] (lvds3.west) -- ++ (-0.55, 0) -- ++ (0, 2.9) -- ++ (-0.58, 0);
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% EEPROMs
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\draw (6, -1.4) node[twoportshape, t={EEPROM}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (eeprom0) {};
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\draw (6, -3.9) node[twoportshape, t={EEPROM}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (eeprom1) {};
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% Repeaters for DDS0 sync clock & DDS sync output from sync buffer
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\draw (3.5, -3.85) node[twoportshape, t={Repeaters}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (rep) {};
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% Connect DDS0 to repeaters
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\draw [-latexslim] (sig0.east) -- ++ (0.3, 0) -- ++ (0, -1.55) -- (3.35, -3.3) -- ++ (0, -0.3);
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% Connect sync_buf to repeaters
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\draw [-latexslim] (sync_buf.south) -- ++ (0, -0.3) -- ++ (0.15, 0) -- ++ (0, -0.55);
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% EEMs
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\draw (8, -0.9) node[twoportshape, t={EEM Port 0}, circuitikz/bipoles/twoport/width=3.2, scale=0.5, rotate=-90] (eem0) {};
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\draw (8, -3.4) node[twoportshape, t={EEM Port 1}, circuitikz/bipoles/twoport/width=3.2, scale=0.5, rotate=-90] (eem1) {};
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% Connect LVDS and EEM
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\draw [latexslim-latexslim] (lvds0.east) -- (7.75, 0);
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\draw [latexslim-latexslim] (lvds1.east) -- (7.75, -0.7);
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\draw [latexslim-latexslim] (lvds2.east) -- (7.75, -2.5);
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\draw [latexslim-latexslim] (lvds3.east) -- (7.75, -3.2);
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% Connect EEPROM to EEM
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\draw [latexslim-latexslim] (eeprom0.east) -- (7.75, -1.4);
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\draw [latexslim-latexslim] (eeprom1.east) -- (7.75, -3.9);
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% Connect EEM0 to sync_buf
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\draw [latexslim-] (3.65, -2.25) -- (3.65, -1.85) -- (7.75, -1.85);
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% Connect repeaters output to EEM1
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\draw [-latexslim] (rep.south) -- (3.5, -4.35) -- (7.75, -4.35);
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% Synchronization ICs encased in another dotted area
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\node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(rep.south west)(sync_buf.north east)] (sync_path) {};
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\node[fill=white, rotate=-90, scale=0.5] at (sync_path.east) {AD9910 Only};
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\end{scope}
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\end{circuitikz}
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}
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\caption{Simplified Block Diagram}
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\end{figure}
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\begin{figure}[h]
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\centering
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\scalebox{0.88}{
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\begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
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\begin{scope}[]
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% RF switches {0, 1, 2, 3} for SMA {0, 1, 2, 3}
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\draw (1.4, 0) node[twoportshape, t={RF Switch}, circuitikz/bipoles/twoport/width=1.5, scale=0.6] (sw) {};
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% Amplifiers {0, 1, 2, 3} for RF switches {0, 1, 2, 3}
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\draw (3, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) {};
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% Attenuators {0, 1, 2, 3} for amplifiers {0, 1, 2, 3}
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\draw (4.6, 0) node[twoportshape, t=\MymyLabel{Digital}{Attenuator}, circuitikz/bipoles/twoport/width=2, scale=0.6, rotate=-90] (att) {};
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% DDS {0, 1, 2, 3} for attenuators {0, 1, 2, 3}
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\draw (6.6, 0) node[twoportshape, t={DDS}, circuitikz/bipoles/twoport/width=1.2, scale=0.7] (dds) {};
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% Connect main signal path
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\draw [-latexslim] (dds.west) -- (att.north);
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\draw [-latexslim] (att.south) -- (amp.west);
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\draw [-latexslim] (amp.east) -- (sw.east);
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% Connect abstract DDS clock input
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\node [label=above:\tiny{CLK Buffers}] at (8, -0.2) {};
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\draw [latexslim-] (dds.east) -- (8, 0);
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% Insert CPLD signal to relevant components
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\node [label=above:\tiny{CPLD}] at (8, 1.1) {};
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\draw [-] (1.4, 1.3) -- (8, 1.3);
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\draw [-latexslim] (1.4, 1.3) -- (sw.north);
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\draw [-latexslim] (4.6, 1.3) -- (att.west);
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\draw [-latexslim] (6.6, 1.3) -- (dds.north);
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% Connect sync_buf signal to DDS
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\draw [latexslim-] (6.9, -1.35) -- (6.9, -0.35);
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\draw [-latexslim] (6.3, -1.35) -- (6.3, -0.35);
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\node [label=below:\tiny{Sync Buffer /}] at (6.6, -1.15) {};
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\node [label=below:\tiny{Repeaters}] at (6.6, -1.4) {};
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\node [label={[rotate=-90]above:\tiny{DDS 0}}] at (6.8, -0.9) {};
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\node [label={[rotate=-90]above:\tiny{Only}}] at (6.55, -0.9) {};
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\end{scope}
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\end{circuitikz}
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}
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\caption{Simplified DDS Signal Path}
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\end{figure}
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\begin{figure}[h]
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\centering
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\includegraphics[width=1.78in]{photo4410.jpg}
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\caption{Urukul Card photo}
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\end{figure}
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% For wide tables, a single column layout is better. It can be switched
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% page-by-page.
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\onecolumn
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\section{Electrical Specifications}
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\begin{table}[h]
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\begin{threeparttable}
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\caption{Recommended Operating Conditions}
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\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
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\thickhline
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\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
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\textbf{Unit} & \textbf{Conditions} \\
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\hline
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Clock input & & & & & &\\
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\hspace{3mm} Input frequency & & 10 & & 1000 & MHz & PLL disabled \\
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& & 3.2 & & 60 & MHz & AD9910, PLL enabled, no clock division \\
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& & 12.8 & & 240 & MHz & AD9910, PLL enabled, 4x clock division \\
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& & 11 & & 200 & MHz & AD9912, PLL enabled, no clock division \\
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& & 44 & & 800 & MHz & AD9912, PLL enabled, 4x clock division \\
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\hspace{3mm} Nominal input power & & & 10 & & dBm & \\
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\thickhline
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\end{tabularx}
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\end{threeparttable}
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\end{table}
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\begin{table}[h]
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\begin{threeparttable}
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\caption{RF Output Specifications}
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\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
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\thickhline
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\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
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\textbf{Unit} & \textbf{Conditions} \\
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\hline
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Low frequency power & & & & -20 & dBm & 100 kHz output \\
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& & & & 10 & dBm & 1 MHz output \\
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\hline
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Frequency & & 1 & & 400 & MHz & \\
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\hline
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Attenuation & & -31.5 & & 0 & dB & \\
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\hline
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Resolution & & & & & & \\
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\hspace{3mm} Frequency & & & 0.25 & & Hz & AD9910 \\
|
|
& & & 8 & & $\mu$Hz & AD9912 \\
|
|
\hspace{3mm} Phase offset & & & 16 & & bits & AD9910 \\
|
|
& & & 14 & & bits & AD9912 \\
|
|
\hspace{3mm} Digital amplitude & & & 14 & & bits & AD9910 \\
|
|
\hspace{3mm} DAC full scale current & & & 8 & & bits & AD9910 \\
|
|
& & & 10 & & bits & AD9912 \\
|
|
\hspace{3mm} Temporal (I/O Update) & & & 4 & & ns & \\
|
|
\hspace{3mm} Digital attenuation & & & 0.5 & & dB & \\
|
|
\thickhline
|
|
\end{tabularx}
|
|
\end{threeparttable}
|
|
\end{table}
|
|
|
|
\newpage
|
|
|
|
All performance data are produced using the following setup unless otherwise noted.
|
|
\begin{itemize}
|
|
\item 100 MHz input clock into SMA, 10 dBm.
|
|
\item Input clock divided by 4.
|
|
\item PLL with x40 multiplier.
|
|
\item Output frequency at 80 MHz or 81 MHz.
|
|
\end{itemize}
|
|
|
|
\begin{table}[h]
|
|
\begin{threeparttable}
|
|
\caption{Electrical Characteristics}
|
|
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
|
\thickhline
|
|
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
|
\textbf{Unit} & \textbf{Conditions} \\
|
|
\hline
|
|
Digital attenuator glitch duration & & & 100 & & ns & \\
|
|
\hline
|
|
RF switch & & & & & &\\
|
|
\hspace{3mm} Rise to 90\% & $t_{on}$ & & 100 & & ns & \\
|
|
\hspace{3mm} Isolation & & & 70 & & dB & \\
|
|
\hspace{3mm} Turn-on chirp & $\gamma$ & & & 0.1 & deg/s & Excluding the first $\mu$s\\
|
|
\hline
|
|
Crosstalk & & & -84 & & dB & Victim RF switch opened \\
|
|
& & & -110 & & dB & Victim RF switch closed \\
|
|
\hline
|
|
Cross-channel-intermodulation & & & -90 & & dB & \\
|
|
\hline
|
|
Phase noise & & & -85 & & dBc/Hz & 0.1 Hz \\
|
|
& & & -95 & & dBc/Hz & 1 Hz \\
|
|
& & & -107 & & dBc/Hz & 10 Hz \\
|
|
& & & -116 & & dBc/Hz & 100 Hz \\
|
|
& & & -126 & & dBc/Hz & 1 kHz \\
|
|
& & & -133 & & dBc/Hz & 10 kHz \\
|
|
& & & -135 & & dBc/Hz & 100 kHz \\
|
|
& & & -128 & & dBc/Hz & 1 MHz \\
|
|
& & & -149 & & dBc/Hz & 10 MHz \\
|
|
\hline
|
|
Second-order harmonics & & & -40 & & dB & 6 dBm output \\
|
|
& & & -34 & & dB & 10.5 dBm output \\
|
|
\hline
|
|
Third-order harmonics & & & -54 & & dB & 6 dBm output \\
|
|
& & & -28 & & dB & 10.5 dBm output \\
|
|
\hline
|
|
Power consumption (AD9910) & & & 7 & & W & 4x 400 MHz, 10.5 dBm, 52\degree C\\
|
|
Power consumption (AD9912) & & & 6.5 & & W & 4x 400 MHz, 10.5 dBm, 52\degree C\\
|
|
\thickhline
|
|
\end{tabularx}
|
|
\end{threeparttable}
|
|
\end{table}
|
|
|
|
\newpage
|
|
|
|
\section{Example ARTIQ code}
|
|
The sections below demonstrate simple usage scenarios of the 4410 Urukul card with the ARTIQ control system.
|
|
They do not exhaustively demonstrate all the features of the ARTIQ system.
|
|
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
|
|
|
|
\subsection{10 MHz Sinusoidal Wave}
|
|
Generate a 10MHz sinusoid from RF0 with full scale amplitude, attenuated by 6 dB.
|
|
Both the CPLD and the DDS channels should be initialized.
|
|
|
|
\begin{minted}{python}
|
|
@kernel
|
|
def run(self):
|
|
self.core.reset()
|
|
self.cpld.init()
|
|
self.dds0.init()
|
|
self.dds0.cfg_sw(True)
|
|
self.dds0.set_att(6.)
|
|
self.dds0.set(10*MHz, amplitude=1.0)
|
|
\end{minted}
|
|
|
|
If the synchronization feature of AD9910 was enabled, RF signal across different channels of the same Urukul can be synchronized.
|
|
For example, phase-coherent RF signal can be produced on both channel 0 and channel 1 after configuring an appropriate phase mode.
|
|
\begin{minted}{python}
|
|
@kernel
|
|
def run(self):
|
|
self.core.reset()
|
|
self.cpld.init()
|
|
|
|
self.dds0.init()
|
|
self.dds0.cfg_sw(True)
|
|
self.dds0.set_phase_mode(PHASE_MODE_TRACKING)
|
|
self.dds0.set_att(6.)
|
|
self.dds1.init()
|
|
self.dds1.cfg_sw(True)
|
|
self.dds1.set_phase_mode(PHASE_MODE_TRACKING)
|
|
self.dds1.set_att(6.)
|
|
|
|
self.dds0.set(10*MHz, phase=0.0)
|
|
self.dds1.set(10*MHz, phase=0.25) # 0.25 turns phase offset
|
|
\end{minted}
|
|
Note that the phase difference between the 2 channels might not be exactly 0.25 turns, but it is a constant.
|
|
It can be negated by adjusting the \texttt{phase} parameter.
|
|
|
|
\newpage
|
|
\subsection{DDS RAM Modulation (AD9910 Only)}
|
|
This examples demonstrates that the RF signal can be modulated by amplitude using the RAM modulation feature of AD9910.
|
|
By default, RAM profiles are programmed to profile 0.
|
|
|
|
\begin{minted}{python}
|
|
from artiq.coredevice.ad9910 import RAM_MODE_CONT_RAMPUP
|
|
|
|
def prepare(self):
|
|
self.amp = [0.0, 0.0, 0.0, 0.7, 0.0, 0.7, 0.7] # Reversed Order
|
|
self.asf_ram = [0] * len(self.amp)
|
|
|
|
@kernel
|
|
def init_dds(self, dds):
|
|
self.core.break_realtime()
|
|
dds.init()
|
|
dds.set_att(6.)
|
|
dds.cfg_sw(True)
|
|
|
|
@kernel
|
|
def configure_ram_mode(self, dds):
|
|
self.core.break_realtime()
|
|
dds.set_cfr1(ram_enable=0)
|
|
self.cpld.io_update.pulse_mu(8)
|
|
self.cpld.set_profile(0) # Enable the corresponding RAM profile
|
|
# Profile 0 is the default
|
|
dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,
|
|
step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
|
|
self.cpld.io_update.pulse_mu(8)
|
|
dds.amplitude_to_ram(self.amp, self.asf_ram)
|
|
dds.write_ram(self.asf_ram)
|
|
|
|
dds.set(10*MHz, profile=-1)
|
|
# Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
|
|
dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
|
|
|
|
self.cpld.io_update.pulse_mu(8)
|
|
|
|
@kernel
|
|
def run(self):
|
|
self.core.reset()
|
|
self.core.break_realtime()
|
|
self.cpld.init()
|
|
|
|
self.init_dds(self.dds0)
|
|
self.configure_ram_mode(self.dds0)
|
|
\end{minted}
|
|
|
|
The generated RF output of the above example consists of the following features in sequence:
|
|
\begin{enumerate}
|
|
\item A 10 MHz RF pulse for 2 microseconds.
|
|
\item No signal for 1 microseconds.
|
|
\item A 10 MHz RF pulse for 1 microseconds.
|
|
\item No signal for 3 microseconds.
|
|
\item Go back to item 1.
|
|
\end{enumerate}
|
|
The expected waveform is plotted on the following figure.
|
|
|
|
\begin{figure}[h]
|
|
\centering
|
|
\includegraphics[width=\textwidth]{ad9910_amp_mod.png}
|
|
\caption{Expected waveform from the RAM modulation example}
|
|
\end{figure}
|
|
|
|
Multiple RAM channels can also be synchronized.
|
|
Similar to the 10 MHz single-tone RF signals, specify \texttt{phase} when calling \texttt{dds.set()} in \texttt{configure\char`_ram\char`_mode}.
|
|
For example, set phase to 0 for the channels (\texttt{phase=0.0}).
|
|
\begin{minted}{python}
|
|
dds.set(10*MHz, phase=0.0, profile=-1)
|
|
\end{minted}
|
|
Then, replace the \texttt{run()} function with the following.
|
|
\begin{minted}{python}
|
|
@kernel
|
|
def run(self):
|
|
self.core.reset()
|
|
self.core.break_realtime()
|
|
self.cpld.init()
|
|
|
|
self.init_dds(self.dds0)
|
|
self.init_dds(self.dds1)
|
|
self.dds0.set_phase_mode(PHASE_MODE_TRACKING)
|
|
self.dds1.set_phase_mode(PHASE_MODE_TRACKING)
|
|
|
|
self.configure_ram_mode(self.dds0)
|
|
self.configure_ram_mode(self.dds1)
|
|
\end{minted}
|
|
Two phase-coherent RF signal with the same waveform as the previous figure should be generated.
|
|
|
|
\newpage
|
|
|
|
\section{Ordering Information}
|
|
To order, please visit \url{https://m-labs.hk} and select the 4410 Urukul in the ARTIQ Sinara crate configuration tool.
|
|
The default chip is AD9910 (4410 Urukul), which supports more features.
|
|
If you need the higher frequency resolution of the AD9912 (4412 Urukul), leave us a note when placing the order.
|
|
The cards may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
|
|
|
\section*{}
|
|
\vspace*{\fill}
|
|
|
|
\begin{footnotesize}
|
|
Information furnished by M-Labs Limited is believed to be accurate and reliable. However, no responsibility is assumed by M-Labs Limited for its use, nor for any infringements of patents or other rights of third parties that may result from its use.
|
|
Specifications subject to change without notice.
|
|
\end{footnotesize}
|
|
|
|
\end{document}
|