forked from sinara-hw/datasheets
36 lines
745 B
Python
36 lines
745 B
Python
from artiq.experiment import *
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class CachePut(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("core_cache")
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@kernel
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def put(self, key, value):
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self.core_cache.put(key, value)
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# First experiment
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@kernel
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def run(self):
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self.put("data", [0xCAFE, 0xDEAD, 0xBEEF])
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class CacheGet(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("core_cache")
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@kernel
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def get(self, key):
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return self.core_cache.get(key)
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@rpc(flags={"async"})
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def p(self, p):
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print([hex(_) for _ in p])
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# Second experiment
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@kernel
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def run(self):
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self.p(self.get("data"))
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