\input{preamble}
\input{shared/coredevice}
\graphicspath{{images/1125}{images}}

\title{1125 Carrier Kasli-SoC}
\author{M-Labs Limited}
\date{December 2024}
\revision{Revision 1} % potentially publishable pending whether block diagram is necessary
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}

\begin{document}
\maketitle

\section{Features}

\begin{itemize}
    \item{RJ45 10/100/1000T Ethernet connector}
    \item{4 SFP 12Gb/s slots for DRTIO at 2.5Gb/s}
    \item{12 EEM ports for daughtercards}
    \item{Xilinx Zynq-7000 SoC with Kintex-7 FPGA}
    \item{SD card flash memory}
\end{itemize}

\section{Applications}

\begin{itemize}
    \item{Run ARTIQ kernels}
    \item{Communicate with the host}
    \item{Control other Sinara EEM cards}
    \item{Distributed Real-Time I/O}
\end{itemize}

\section{General Description}

    The 1125 Kasli-SoC Carrier card is an 8hp EEM module, designed to run ARTIQ-Zynq kernels sent over the network from a host machine. Kasli-SoC is built around a Xilinx Zynq-7000 SoC, capable of running more complex computations at high speed than its sister card 1124 Kasli 2.0. It supports up to 12 EEM connections to other EEM cards in the ARTIQ-Sinara family and up four SFP connections for comunications with other carriers. A dedicated Ethernet port is used for communications with the host.

    Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO system. 1ns temporal resolution can be achieved for TTL events.

    4 SFP 12Gb/s slots are provided. These can be used by the ARTIQ Distributed Real-Time Input/Output (DRTIO) system, which allows for the use of additional core devices (e.g. Kasli or other Kasli-SoCs) as satellite cards, capable of running subkernels or relaying commands to a larger number of peripherals.

% Switch to next column
\vfill\break

% TODO, possibly: block diagram

\begin{figure}[hbt!]
    \centering
    \includegraphics[height=3in]{photo1125.jpg}
    \caption{Kasli-SoC card}
    \includegraphics[angle=90,height=1in]{Kasli-SoC_FP.pdf}
    \caption{Kasli-SoC front panel}
\end{figure}

% END PAGE ONE (for wide pages a single-column layout is preferable)
\onecolumn

\sourcesection{Kasli-SoC}{https://github.com/sinara-hw/Kasli-SOC/}

\section{Electrical Specifications}

    External clock parameters are derived based on the internal termination specified in
    UG471\footnote{\label{ug471}\url{https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO}}
    and the voltage range specified in
    DS191\footnote{\label{ds191}\url{https://docs.amd.com/v/u/en-US/ds191-XC7Z030-XC7Z045-data-sheet}}. These figures account for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}\url{https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}}).

    \spectable

\section{SoC}

    Kasli-SoC features a XC7Z030-3FFG676E Xilinx Zynq-7000 System-on-Chip with a Kintex-7 FGPA and an Cortex-A9 dual-core processor to facilitate high-speed real-time control of inputs and outputs. The use of the SoC allows for more complex computations at higher speed than Kasli 2.0's purely on-FPGA CPU. Usually, the SoC is flashed with firmware and gateware binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with the ability to control other Sinara EEMs and run ARTIQ experiment kernels.

    A micro-USB located on the front panel is equipped for JTAG, I2C, and UART serial output. The serial interface runs at 115200bps 8-N-1.

\artiqsection

    ARTIQ-supported core devices based on Zynq-7000 SoCs, including Kasli-SoC, require firmware and gateware compiled from the ARTIQ-Zynq port, which can be found in the repository \url{https://git.m-labs.hk/M-Labs/artiq-zynq}.

    \noteondrtio{Kasli-SoC}

\section{Communication Interfaces}

    Communication between core devices is implemented with 1000Base-T small form-factor pluggable (SFP) interfaces. Four are available on 1125 Kasli-SoC. Each SFP connector possesses an indicator LED.

    Transceiver maximum speed is 12.5 Gb/s\footnote{\url{https://www.amd.com/en/products/adaptive-socs-and-fpgas/technologies/high-speed-serial.html}}. DRTIO is normally run at 2.5 Gb/s with 8b10b encoding.

    Additionally, a RJ45 10/100/1000T Ethernet port is featured for network connection to a host machine.

    \subsection{Upstream connection}

    \begin{itemize}
        \item \textbf{Standalone/Master} \\
        A network-connected Ethernet cable should be attached the front panel Ethernet port to enable communication with a host machine.
        \item \textbf{Satellite} \\
        Satellites must acquire an upstream connection to another satellite or the master. The \texttt{SFP0} port should be connected to one of the free SFP slots on an upstream core device, using a cable or fibre connection with SFP transceivers.
    \end{itemize}

    \subsection{Downstream connection}
    Kasli-SoC supports up to 4 DRTIO satellite connections per device. Any of the 4 downstream SFP ports (i.e. \texttt{SFP0}, \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) may be freely used. Port \texttt{SFPn} normally receives the destination number \texttt{n + 1}.

\clockingsection{Kasli-SoC}{SoC}

\newpage

\section{Configuring Boot Mode}

    Kasli-SoC is capable of booting either remotely, over JTAG USB, or directly from the SD card. See the ARTIQ manual for more instructions on how to correctly flash and boot a core device. Boot mode must be configured by flipping physical switches on the board. The boot mode DIP switches are located in the middle of the board. To boot from USB, flip both switches towards the label \texttt{JTAG}. To boot from the SD card, flip both switches towards the label \texttt{SD}.

    \begin{figure}[hbt!]
        \centering
        \includegraphics[height=3in]{kasli-soc_dip_switches.jpg}
        \caption{Position of DIP switches, SD card, and POR pins}
    \end{figure}

    \subsection{POR jumpers and POR reset}

    A known Xilinx hardware bug prevents repeatedly booting over JTAG without a POR reset. If necessary, repeated boots can be made possible by physically setting a jumper on the POR pins (marked above) and triggering a reset over JTAG, see also the M-Labs POR reset script.\footnote{\url{https://git.m-labs.hk/M-Labs/zynq-rs/src/branch/master/kasli_soc_por.py}}

\section{User LEDs}

    Kasli-SoC designates two user LEDs for debugging purposes. One is located on the PCB; it can be found at the very bottom left of the board, below the SFP cage, labeled \texttt{USER0}. The second is located on the front panel, besides the Ethernet port, labeled \texttt{L1}.

\sysdescsection

    An example description file for a system using 1125 Kasli-SoC as a master core device might begin:

    \begin{tcolorbox}[colback=white]
        \begin{minted}{json}
            "target": "kasli_soc",
            "variant": "my_variant",
            "hw_rev": "v1.0",
            "base": "master",
            "peripherals": [    ]
        \end{minted}
    \end{tcolorbox}

    \coresysdesc

\coredevicecode{1125 Kasli-SoC carrier}

\ordersection{1125 Carrier Kasli-SoC}

\finalfootnote

\end{document}
