occheung
/
sinarads
forked from sinara-hw/datasheets
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
179 Commits 2 Branches 0 Tags 8.1 MiB
Commit Graph

179 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq cd7d118f7c update disclaimers 2022-01-14 11:55:48 +08:00
occheung b0551b94a0 ttl: reduce image size for switches 
Make the same edits on the original photos, then compress with jpegoptim.
Should look better as well.
 2022-01-11 17:18:30 +08:00
occheung 6b24b54f60 ttl: add switch desc section 
Closes #20.
Closes #22.
 2022-01-11 16:56:38 +08:00
occheung 439edc4302 4410-4412: fix caption punctuation again 2022-01-11 14:54:26 +08:00
occheung e4ceb32134 4410: confirm that dds amplitude at net positive input 2022-01-10 16:15:10 +08:00
occheung ca6caa8e1d 4410: leave space at the top of suservo graph 2022-01-10 16:06:56 +08:00
occheung d9ac9d3d18 4410-4412: add DIP switch doc 
plus minor reformatting
 2022-01-10 15:20:21 +08:00
occheung 876291025b 4410: fix front panel caption 
Inconsistent punctuation
 2022-01-10 15:18:33 +08:00
occheung 282b7bf244 move drawings in front of ARTIQ examples 
And some additional reformatting.
 2022-01-07 17:25:34 +08:00
occheung 3c21ccd4a0 4410: update su-servo example 
The example works after gateware fix in ARTIQ.
9d493028e5
Closes #2.
 2022-01-07 16:54:36 +08:00
occheung 05eba6faef 4410-4412: add symbols in spec table 
There are very limited usage/mentions of symbols on RF power specs (harmonics, attenuations, etc).
 2022-01-07 16:16:08 +08:00
occheung ae4015fbd7 2238: simplify diagram 
Merging a transiceiver on the baseboard and another transceiver on the mezzanine into 2x transceivers.
So the EEM line does not split into odd/even transceivers, and no more jumping lines/hyper-abstract connections.

The termination switches still repsect the physical configuration, so it is not the cleanest.
Though. the connections should be easily understood.
 2022-01-07 13:57:22 +08:00
occheung 39b10ecbd2 slightly enlarge FP drawings 2022-01-07 10:37:16 +08:00
occheung 1727c73e9a 5432: add front panel 2022-01-07 10:33:14 +08:00
occheung ffa71dc40c FP dimen -> FP drawings 2022-01-06 17:32:36 +08:00
occheung 026aa4cf1f 4410: add front panel drawings 2022-01-06 17:29:38 +08:00
occheung 02e9cce585 2118-2128: add front panel figures 
Missing BNC-TTL FP drawings.
 2022-01-06 11:46:30 +08:00
occheung e82e798964 4410: add SU-Servo 
ARTIQ example for SU-Servo is using API prior to artiq PR 1500.
Will need to update to the latest beta at some point.
 2022-01-05 16:19:21 +08:00
occheung ca5db31d8d 2245: remove channel-to-channel skew 
There are mismatch among traces, some by approximately 20mm.
 2022-01-04 13:48:40 +08:00
occheung db1db9335c 5432: specify the waveform is low frequency 2022-01-04 13:21:24 +08:00
occheung 80ff743583 2238: remove capacitance & quiet output specs 2022-01-04 13:18:58 +08:00
occheung 01aba236ed 4410-4412: microwave source -> RF source 2022-01-04 13:17:48 +08:00
occheung fc728b842d 2238: fix typo of mezzanine 2022-01-04 09:44:50 +08:00
occheung 087663d7e0 2238: add photo 2022-01-03 17:21:34 +08:00
occheung 05b7f12c2b 2238: init 2022-01-03 17:21:05 +08:00
occheung 09b07575e0 2245: clarify single EEM 2022-01-03 17:13:49 +08:00
occheung 0ca9115088 2245: remove ESD spec 
This spec refers to the LVDS repeaters only, other ICs may have lower ESD specs.
 2022-01-03 09:59:12 +08:00
occheung dfb1d8028c 2245: fix I/O direction line on CH8-15 2021-12-31 17:40:04 +08:00
occheung 325585db97 2245: fix switch symbol position 2021-12-31 17:36:19 +08:00
occheung 12c0114189 2245: init 2021-12-31 17:34:16 +08:00
occheung b583eef5f6 5432: add plots 2021-12-30 15:00:43 +08:00
occheung a84ba87184 5432: add additional plots 
https://github.com/sinara-hw/Zotino/issues/21
Step response & FEXT.
 2021-12-30 14:33:54 +08:00
occheung a231d13d7a 5432: update applications 2021-12-30 14:33:04 +08:00
occheung f86b663e1d 4410-4412: add figures 2021-12-24 16:49:45 +08:00
occheung 337ecbd6ae 4410-4412: add more specs 2021-12-24 16:36:58 +08:00
occheung e6674c76e4 4410-4412: add harmonic content with generic output frequencies 
https://github.com/sinara-hw/Urukul/issues/29
Other harmonic content info may become obsolete.
 2021-12-24 16:34:30 +08:00
occheung cd8c211462 4410-4412: update applications 2021-12-24 16:33:20 +08:00
occheung 3ff0209452 2118: add photo 2021-12-23 12:56:49 +08:00
occheung a32c43c0b8 2128 -> 2118/2128 2021-12-23 12:56:11 +08:00
occheung 534ef5c6ed 4410-4412: fix layout 2021-12-22 17:19:27 +08:00
occheung bc4e11cdf6 4410-4412: separate RAM SYNC example 2021-12-22 17:17:03 +08:00
occheung 9251da4ce0 4410-4412/RAM: add amplitude ramp example 2021-12-22 17:16:21 +08:00
occheung 4b3f0c5612 4410-4412/RAM: replace screenshot with plot 2021-12-22 17:14:57 +08:00
occheung 1ce032605a 4410-4412/RAM: lower background frequency to 5MHz 
It is to make the plot easier for our eyes.
 2021-12-22 17:12:48 +08:00
occheung d26fe0f5d5 4410-4412: configure_ram_mode add slack 
When the RAM data is larger, extra slack is needed to avoid underflow.
 2021-12-22 17:10:57 +08:00
occheung 9b40af6c6a 4410-4412: add graphs for phase noise/harmonic contents 2021-12-22 12:17:23 +08:00
occheung 82521ff909 4410-4412: enlarge photo 
And prevent the photo from jumping to the next page.
 2021-12-22 09:53:06 +08:00
occheung 3c633dfa27 5432: clarify op-amp label 
In case the x32 notation (somehow) looks like 32 op-amps in series.
 2021-12-09 12:42:17 +08:00
occheung ce04f3f749 5432: fix order info 2021-12-09 12:35:39 +08:00
occheung 6beaac676d 5432: init 2021-12-09 12:33:42 +08:00