From 5837353cab8bcd81f585ff1aea52749ac1ae9138 Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Thu, 2 Dec 2021 10:13:14 +0800
Subject: [PATCH] 4410: fix table/text sequence

---
 4410.tex | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/4410.tex b/4410.tex
index 5f63a3c..f4833ff 100644
--- a/4410.tex
+++ b/4410.tex
@@ -357,6 +357,8 @@ Urukul comes with either AD9910 or AD9912 chips.
 \end{threeparttable}
 \end{table}
 
+\newpage
+
 All performance data are produced using 1 GHz PLL unless otherwise noted.
 
 \begin{table}[h]
@@ -443,8 +445,8 @@ def run(self):
 \end{minted}
 
 \newpage
-\subsection{DDS RAM Modulation}
-Only available to AD9910 variants. Set field \texttt{dds} as an Urukul channel, \texttt{cpld} as the corresponding Urukul CPLD.
+\subsection{DDS RAM Modulation (AD9910 Only)}
+Set field \texttt{dds} as an Urukul channel, \texttt{cpld} as the corresponding Urukul CPLD.
 
 \begin{minted}{python}
 from artiq.coredevice.ad9910 import RAM_MODE_CONT_RAMPUP