forked from sinara-hw/datasheets
50 lines
2.0 KiB
Python
50 lines
2.0 KiB
Python
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from artiq.experiment import *
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from artiq.coredevice import spi2 as spi
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SPI_CONFIG = (0 * spi.SPI_OFFLINE | 0 * spi.SPI_END |
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0 * spi.SPI_INPUT | 0 * spi.SPI_CS_POLARITY |
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0 * spi.SPI_CLK_POLARITY | 0 * spi.SPI_CLK_PHASE |
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0 * spi.SPI_LSB_FIRST | 0 * spi.SPI_HALF_DUPLEX)
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CLK_DIV = 125
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class SPIWrite(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.spi = self.get_device("dio_spi0")
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@kernel
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def run(self):
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self.core.reset()
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self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b110)
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self.spi.write(0x13 << 24) # Shift the bits to the MSBs.
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# Since SPI_LSB_FIRST is NOT set,
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# SPI Machine will shift out bits from
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# the MSB of the `data` register.`
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self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END, 32, CLK_DIV, 0b110)
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self.spi.write(0xDEADBEEF)
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class SPIRead(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.spi = self.get_device("dio_spi0")
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@kernel
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def run(self):
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self.core.reset()
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self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b001)
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self.spi.write(0x81 << 24) # Shift the bits to the MSBs.
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# Since SPI_LSB_FIRST is NOT set,
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# SPI Machine will shift out bits from
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# the MSB of the `data` register.`
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self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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32, CLK_DIV, 0b001)
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self.spi.write(0) # write() performs the SPI transfer.
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# As suggested by the timing diagram,
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# the exact value of this argument
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# does not matter.
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print(self.spi.read())
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