123 lines
3.6 KiB
Python
123 lines
3.6 KiB
Python
from migen import *
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from sync_serdes import MultiLineRX, MultiLineTX
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from migen.genlib.fifo import SyncFIFO
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from migen.build.platforms.sinara import kasli
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from kasli_crg import KasliCRG
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from eem_helpers import generate_pads
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from uart import UART
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from io_loopback import SingleIOLoopback, IOLoopBack
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class MultiSerDesLoopBack(Module):
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def __init__(self, io_pads, sys_clk_freq):
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self.uart_rx = Signal()
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self.uart_tx = Signal()
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self.submodules.uart = UART(round((115200/sys_clk_freq)*2**32))
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self.comb += [
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self.uart.phy_rx.eq(self.uart_rx),
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self.uart_tx.eq(self.uart.phy_tx),
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]
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self.submodules.tx = MultiLineTX()
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self.submodules.rx = MultiLineRX()
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# The actual channel
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self.submodules.channel = IOLoopBack(io_pads)
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# Attach FIFO to UART TX, send rate is too slow w.r.t sysclk
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self.submodules.tx_fifo = SyncFIFO(8, 64)
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self.comb += [
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# Repetitively send 0b00100
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# Note: Replicate() doesn't work, 0b00100 is lowered into 3'd4
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# I need 5'd4 for the replicate operator in Verilog
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self.tx.txdata.eq(0b00100001000010000100),
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# Loopback channel
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self.channel.i.eq(self.tx.ser_out),
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self.channel.t.eq(self.tx.t_out),
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self.rx.ser_in_no_dly.eq(self.channel.o),
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# TX path
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self.uart.tx_data.eq(self.tx_fifo.dout),
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self.uart.tx_stb.eq(self.tx_fifo.readable),
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self.tx_fifo.re.eq(self.uart.tx_ack),
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]
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self.submodules.fsm = FSM(reset_state="WAIT_SELF_ALIGN")
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self.fsm.act("WAIT_SELF_ALIGN",
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If(self.rx.align_done,
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NextState("SAMPLE_RXDATA"),
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),
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)
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sampled_rxdata = Signal(20)
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self.fsm.act("SAMPLE_RXDATA",
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NextValue(sampled_rxdata, self.rx.rxdata),
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NextState("WRITE_PATTERN_FIRST_UPPER"),
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)
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self.fsm.act("WRITE_PATTERN_FIRST_UPPER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[8:10]),
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NextState("WRITE_PATTERN_FIRST_LOWER"),
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),
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)
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self.fsm.act("WRITE_PATTERN_FIRST_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[:8]),
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NextState("WRITE_PATTERN_SECOND_UPPER"),
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),
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)
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self.fsm.act("WRITE_PATTERN_SECOND_UPPER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[18:20]),
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NextState("WRITE_PATTERN_SECOND_LOWER"),
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),
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)
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self.fsm.act("WRITE_PATTERN_SECOND_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[10:18]),
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NextState("TERMINATE"),
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),
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)
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self.fsm.act("TERMINATE",
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NextState("TERMINATE"),
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)
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if __name__ == "__main__":
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platform = kasli.Platform(hw_rev="v2.0")
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# Generate pads for the I/O blocks
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eem = 3
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generate_pads(platform, eem)
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pads = [
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platform.request("dio{}".format(eem), i) for i in range(4)
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]
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# pad = platform.request("dio{}".format(eem), 0)
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crg = KasliCRG(platform)
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top = MultiSerDesLoopBack(pads, crg.sys_clk_freq)
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# Wire up UART core to the pads
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uart_pads = platform.request("serial")
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top.comb += [
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top.uart_rx.eq(uart_pads.rx),
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uart_pads.tx.eq(top.uart_tx),
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]
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top.submodules += crg
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platform.build(top)
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